CN117650172A - Enhanced HEMT device structure and manufacturing method thereof - Google Patents

Abstract

The invention discloses an enhanced HEMT device structure and a manufacturing method thereof. The enhanced HEMT device structure comprises a heterojunction, a source electrode, a drain electrode and a grid electrode, wherein the heterojunction comprises a channel layer and a barrier layer which are stacked, the barrier layer is formed by a semiconductor material containing Al, and the thickness of the barrier layer is smaller than the critical thickness of the barrier layer capable of forming two-dimensional electron gas with the channel layer; the enhanced HEMT device structure further comprises a two-dimensional electron gas recovery layer, the two-dimensional electron gas recovery layer is arranged on the barrier layer in a layer-by-layer mode, the source electrode and the drain electrode are arranged on the two-dimensional electron gas recovery layer, and the two-dimensional electron gas recovery layer is used for recovering the concentration of two-dimensional electron gas in the channel. According to the invention, the relation between the thickness of the barrier layer and the concentration of the 2DEG is utilized, the thickness of the adopted barrier layer is lower than the critical thickness for forming the 2DEG, so that the channel of the device is in a depletion state initially, the initial concentration of the 2DEG is changed by changing the Al component and the thickness of the barrier layer, and the threshold voltage regulation and control can be realized.

Description

Enhanced HEMT device structure and manufacturing method

Technical field

The invention particularly relates to an enhanced HEMT device structure and a manufacturing method thereof, and belongs to the technical fields of micro-nano manufacturing and semiconductor devices.

Background technique

The traditional AlGaN/GaN HEMT is a depletion mode device, which requires an external negative gate voltage to make the device in the off state. This makes it easy to turn on accidentally during use, which poses a safety hazard. Secondly, in the drive circuit design There is greater difficulty in it. Therefore, enhanced devices are often more needed in actual industries. Firstly, using enhanced devices can improve system security and stability and simplify the design of drive power supplies. Secondly, in the field of digital logic circuits, E/D-mode inverters can be prepared . At present, there are mainly the following methods to realize enhanced AlGaN/GaN HEMT devices, namely p-type gate structure devices, groove gate structure devices, fluorine ion implantation structure devices and thin barrier structure devices.

Existing method 1: Insert a layer of p-type doped GaN-based material under the gate of a traditional HEMT device as a cap layer, and use the p-type doped material to raise the energy band of the device, making the two-dimensional electron gas in the channel Depletion can also occur at zero gate voltage to achieve enhanced characteristics. References: GRECO G, IUCOLANO F, ROCCAFORTE F. Review of technology for normally-off HEMTs with p-GaN gate[J]. Materials Science in Semiconductor Processing, 2018, 78: 96-106.

Existing method 2: Etch the AlGaN barrier layer under the gate to reduce the concentration of 2DEG in the channel under the gate, causing the threshold voltage to shift forward, thereby achieving enhancement-mode characteristics. References: OKA T, NOZAWA T.AlGaN/GaN recessedMIS-gate HFET with high-threshold-voltage normally-off operation for powerelectronics applications[J]. IEEE Electron Device Letters, 2008, 29(7): 668-670.

Existing method 3: Injecting ^F- ions under the gate can increase the Schottky barrier height under the gate, deplete the 2DEG under the gate, and enable the device to achieve enhanced characteristics. References: CAI Y, ZHOU YG, CHEN KJ, et al. High-performance enhancement-mode AlGaN/GaN HEMTs using fluoride-based plasmatreatment[J]. IEEE Electron Device Letters, 2005, 26(7): 435-437.

Existing method 4: Use ultra-thin barrier A1GaN/GaN heterojunction to achieve low channel 2DEG concentration, use LPCVD to deposit SiN _x as the 2DEG recovery layer, and then use plasma to etch away SiN _x under the gate to achieve enhancement mode characteristic. References: Huang S, Liu X, Wang -1620.

However, the current enhancement-mode structure has more or less problems. First, the gate voltage swing of the device in the p-type gate structure is small and the gate driving capability is limited. Secondly, the special structure of the p-type gate causes the device to have a series of gate Reliability issues. The barrier layer of the grooved gate structure needs to be etched, and etching damage will introduce large gate leakage. It usually requires the growth of a gate dielectric layer, which is a complex process and difficult to control. The F ^- ions injected into the fluorine ion implantation structure are unstable at high temperatures, and the threshold voltage of the device will drift negatively at high temperatures. The existing thin barrier structure overcomes the technical shortcomings of the previous methods, but its use of etching methods to remove SiN _x under the gate brings inevitable etching damage. Secondly, the recovery carrier concentration is not high enough, resulting in saturation current density. It is difficult to achieve a higher breakthrough.

Contents of the invention

The main purpose of the present invention is to provide an enhanced HEMT device structure and a manufacturing method thereof, thereby overcoming the deficiencies in the prior art.

In order to achieve the foregoing invention objectives, the technical solutions adopted by the present invention include:

In one aspect, the present invention provides an enhanced HEMT device structure, including a heterojunction and a source, a drain and a gate that match the heterojunction. The heterojunction includes a stacked channel layer and a potential. barrier layer;

The barrier layer is formed of a semiconductor material containing Al, and the thickness of the barrier layer is less than a critical thickness capable of forming a two-dimensional electron gas with the channel layer;

And, the enhanced HEMT device structure further includes a two-dimensional electron gas recovery layer, the two-dimensional electron gas recovery layer is stacked on the barrier layer, and the source electrode and the drain electrode are arranged on the two On the two-dimensional electron gas recovery layer, the two-dimensional electron gas recovery layer is used to restore the concentration of the two-dimensional electron gas in the channel, wherein the gate region of the two-dimensional electron gas recovery layer has a gate groove structure, and the gate groove The groove bottom of the structure is located in the barrier layer, the groove opening is located in the two-dimensional electron gas recovery layer, and the gate electrode is arranged in the gate groove structure.

On the other hand, the present invention also provides a method for manufacturing an enhanced HEMT device structure, including:

Making a heterojunction, the heterojunction includes a stacked channel layer and a barrier layer, the barrier layer is formed of a semiconductor material containing A1, and the thickness of the barrier layer is smaller than the thickness of the barrier layer itself and the channel layer. The channel layer forms the critical thickness of the two-dimensional electron gas;

A two-dimensional electron gas recovery layer is formed in the non-gate area of the barrier layer. The two-dimensional electron gas recovery layer is used to recover the concentration of the channel two-dimensional electron gas, and the two-dimensional electron gas recovery layer is The barrier layer also encloses a gate groove structure, and the groove bottom of the gate groove structure is located in the barrier layer;

A source electrode and a drain electrode are formed on the two-dimensional electron gas recovery layer. The source electrode and the drain electrode are electrically connected through the two-dimensional electron gas recovery layer. On the two-dimensional electron gas recovery layer and the gate trench structure A gate dielectric layer is formed inside, and a gate electrode is formed on the gate dielectric layer.

Compared with the existing technology, the advantages of the present invention include:

1) The present invention utilizes the relationship between the thickness of the barrier layer and the concentration of 2DEG. The thickness of the barrier layer is lower than the critical thickness for forming 2DEG, so that the device channel is initially in a depletion state. By changing the A1 of the barrier layer The initial 2DEG concentration is changed by composition and thickness, and threshold voltage regulation can be achieved;

2) The present invention grows a thin Si layer on the surface of the barrier layer as a 2DEG recovery layer. Compared with the SiNx layer, the Si layer has a higher Si doping efficiency and can increase the 2DEG concentration to a greater extent, thus increasing the saturation current of the device. density;

3) The present invention uses wet etching to remove the Si layer in the area below the gate, thereby avoiding the impact of etching damage.

Description of drawings

Figure 1 is a schematic structural diagram of an enhanced HEMT device structure provided in a typical implementation case of the present invention;

FIG. 2 is a schematic structural diagram of the manufacturing process of an enhanced HEMT device structure provided in a typical implementation case of the present invention.

Detailed ways

In view of the deficiencies in the prior art, the inventor of this case was able to propose the technical solution of the present invention after long-term research and extensive practice. The technical solution, its implementation process and principles will be further explained below.

Explanation of terms involved in this invention:

Gate area/under-gate area, orthographic projection area of the gate.

Source area, the orthographic projection area of the source.

Drain area, the orthographic projection area of the drain.

In one aspect, the present invention provides an enhanced HEMT device structure, including a heterojunction and a source, a drain and a gate that match the heterojunction. The heterojunction includes a stacked channel layer and a potential. barrier layer;

The barrier layer is formed of a semiconductor material containing Al, and the thickness of the barrier layer is less than a critical thickness capable of forming a two-dimensional electron gas with the channel layer;

And, the enhanced HEMT device structure further includes a two-dimensional electron gas recovery layer, the two-dimensional electron gas recovery layer is stacked on the barrier layer, and the source electrode and the drain electrode are arranged on the two On the two-dimensional electron gas recovery layer, the two-dimensional electron gas recovery layer is used to restore the concentration of the two-dimensional electron gas in the channel, wherein the gate region of the two-dimensional electron gas recovery layer has a gate groove structure, and the gate groove The groove bottom of the structure is located in the barrier layer, the groove opening is located in the two-dimensional electron gas recovery layer, and the gate electrode is arranged in the gate groove structure.

Further, the thickness of the barrier layer is not less than 2 nm.

Further, the A1 component content of the barrier layer is 3at.% to 30at.%.

Further, the thickness of the barrier layer ranges from 2 nm to 52 nm.

It should be noted that the thickness of the barrier layer corresponds to its own Al component content. For example, when the Al component content of the barrier layer is 3at.%, the barrier layer has The critical thickness is 52.00805913nm, and the thickness of the barrier layer can be selected to be any value greater than or equal to 2nm and less than 52.00805913nm.

Further, the material of the barrier layer includes AlGaN, and the material of the channel layer includes GaN.

Further, the material of the two-dimensional electron gas recovery layer includes Si.

Further, the thickness of the two-dimensional electron gas recovery layer is 1 nm to 10 nm.

In a more specific embodiment, the enhanced HEMT device structure further includes a protective layer, the protective layer is stacked on the two-dimensional electron gas recovery layer, and the protective layer is at least used to protect the two-dimensional electron gas recovery layer. The electron gas recovery layer is not oxidized.

Further, the protective layer is disposed between the gate electrode, the source electrode, and the drain electrode, and the notch of the gate trench structure is located in the protective layer.

Further, the material of the protective layer includes SiNx or AlN.

Further, the thickness of the protective layer is 20 nm to 30 nm.

In a more specific implementation, the enhancement mode HEMT device structure further includes a gate dielectric layer, the gate dielectric layer is at least disposed within the gate trench structure, and the gate electrode is disposed on the gate dielectric layer.

Furthermore, the material of the gate dielectric layer includes a Si-free compound.

Further, the material of the gate dielectric layer includes hafnium oxide, aluminum nitride or aluminum oxide.

On the other hand, the present invention also provides a method for manufacturing an enhanced HEMT device structure, including:

Making a heterojunction, the heterojunction includes a stacked channel layer and a barrier layer, the barrier layer is formed of a semiconductor material containing Al, and the thickness of the barrier layer is smaller than the thickness of the barrier layer that can be connected to the channel layer. The channel layer forms the critical thickness of the two-dimensional electron gas;

A two-dimensional electron gas recovery layer is formed in the non-gate area of the barrier layer. The two-dimensional electron gas recovery layer is used to recover the concentration of the channel two-dimensional electron gas, and the two-dimensional electron gas recovery layer is The barrier layer also encloses a gate groove structure, and the groove bottom of the gate groove structure is located in the barrier layer;

A source electrode and a drain electrode are formed on the two-dimensional electron gas recovery layer. The source electrode and the drain electrode are electrically connected through the two-dimensional electron gas recovery layer. On the two-dimensional electron gas recovery layer and the gate trench structure A gate dielectric layer is formed inside, and a gate electrode is formed on the gate dielectric layer.

Further, the Al component content of the barrier layer is 3 at.% to 30 at.%.

Further, the thickness of the barrier layer ranges from 2 nm to 52 nm.

Further, the material of the barrier layer includes AlGaN, and the material of the channel layer includes GaN.

Further, the manufacturing method specifically includes: forming a two-dimensional electron gas recovery layer on the barrier layer, and then removing the two-dimensional electron gas recovery layer located in the gate region, thereby forming the gate trench structure. .

Further, the manufacturing method specifically includes: removing the two-dimensional electron gas recovery layer located in the gate region by wet etching.

Further, the material of the two-dimensional electron gas recovery layer includes Si.

Further, the thickness of the two-dimensional electron gas recovery layer is 1 nm to 10 nm.

In a more specific embodiment, the manufacturing method further includes: forming a protective layer on the two-dimensional electron gas recovery layer, and the protective layer is disposed between the gate region, the source region, and the drain region. , the protective layer is at least used to protect the two-dimensional electron gas recovery layer from being oxidized, and the protective layer, the two-dimensional electron gas recovery layer, and the barrier layer together form the gate trench structure, The notch of the gate groove structure is located on the protective layer.

In a more specific embodiment, the manufacturing method specifically includes: sequentially forming a stacked two-dimensional electron gas recovery layer and a protective layer on the barrier layer, and removing the protective layer and the protective layer located in the gate region. the two-dimensional electron gas recovery layer to form the gate trench structure;

Remove the protective layer located in the source region and the drain region, and form a source electrode on the two-dimensional electron gas recovery layer located in the source region, and form a source electrode on the two-dimensional electron gas recovery layer located in the drain region. A drain electrode is formed on the gas recovery layer.

In a more specific embodiment, the manufacturing method specifically includes: removing the protective layer and the two-dimensional electron gas recovery layer located in the gate region by wet etching.

Further, the material of the protective layer includes SiNx or AlN.

Further, the thickness of the protective layer is 20 nm to 30 nm.

In a more specific embodiment, the manufacturing method further includes: forming a gate dielectric layer in the gate trench structure, and the gate electrode is disposed on the gate dielectric layer.

Furthermore, the material of the gate dielectric layer includes a Si-free compound.

Further, the material of the gate dielectric layer includes hafnium oxide, aluminum nitride or aluminum oxide.

The technical solution, its implementation process and principles will be further explained below with reference to the accompanying drawings and specific implementation examples. Unless otherwise specified, methods such as PECVD (Plasma Enhanced Chemical Vapor Deposition) used in the embodiments of the present invention ), PEALD (Plasma Enhanced Atomic Layer Deposition) and other epitaxial growth processes and their equipment, photolithography, dry etching and wet etching, metal deposition and other processes and their equipment are all known to those skilled in the art. The specific process is not specifically limited.

Example 1

Please refer to Figure 1. An enhancement mode HEMT device structure includes an epitaxial structure and a source electrode 410, a drain electrode 420 and a gate electrode 430 that match the epitaxial structure. The epitaxial structure includes a substrate 110 and components stacked on the substrate 110. Core layer 120, channel layer 130, intermediate layer 140, barrier layer 150, 2EDG recovery layer 210 and protective layer 220. The gate region of the epitaxial structure has a gate trench structure, and the bottom of the gate trench structure is located on the barrier layer. 150 faces away from the surface of the channel layer 130, and the notch is flush with the surface of the protective layer 220 facing away from the 2EDG recovery layer 210. The source electrode 410 and the drain electrode 420 are arranged on the 2EDG recovery layer 210, and the protective layer 220 is arranged on the gate trench structure. A gate dielectric layer 310 is also provided between the source electrode 410 and the drain electrode 420, as well as on the groove walls of the gate trench structure and the protective layer 220. The gate electrode 430 is disposed in the gate trench structure and located on the gate dielectric layer 310.

In this embodiment, the substrate 110 may be a SiC substrate, a sapphire substrate or a Si substrate, etc., the nucleation layer 120 may be a GaN nucleation layer, the channel layer 130 may be a GaN channel layer, and the intermediate layer 140 may be is an AlN intermediate layer, and the barrier layer 150 may be an AlGaN barrier layer.

In this embodiment, the thickness and aluminum component of the A1GaN barrier layer are calculated according to the critical thickness for forming 2DEG. As shown in Table 1, the thickness of the barrier layer 150 is set lower than the critical thickness according to the content of the A1 component, using The relationship between the thickness of the barrier layer 150 and the 2DEG concentration makes the thickness of the barrier layer 150 lower than the critical thickness for forming 2DEG, so that the channel of the device is initially in a depletion state. By changing the Al group of the barrier layer 150 To change the initial 2DEG concentration by dividing and thickness, the threshold voltage can be adjusted.

Table 1 Content of Al component of A1GaN barrier layer and corresponding critical thickness

In this embodiment, the 2DEG recovery layer 210 is a Si layer, and the thickness of the 2DEG recovery layer 210 is 1 nm to 10 nm. The 2DEG recovery layer 210 is used to recover the concentration of the two-dimensional electron gas in the channel to form an enhanced HEMT device. It should be noted that the 2DEG recovery layer 210 under the source and drain electrodes is retained. Based on the current experimental results, the retained 2DEG recovery layer 210 will not only not reduce the ohmic contact performance of the source and drain electrodes, but will have a certain optimization effect.

In this embodiment, the protective layer 220 is mainly used to protect the 2DEG recovery layer 210 from being oxidized. Specifically, the material of the protective layer 220 includes SiNx or AlN, and the thickness of the protective layer 220 is 20 nm to 30 nm.

In this embodiment, the material of the gate dielectric layer 310 is a compound that does not contain Si. Specifically, the material of the gate dielectric layer 310 is hafnium oxide, aluminum nitride, aluminum oxide, etc., and the thickness of the gate dielectric layer 310 is 10 nm. ~30nm.

Please refer to Figure 2, a method for fabricating an enhanced HEMT device structure, including the following steps:

1) Growth of the epitaxial layer: First, the nucleation layer 120, the GaN channel layer 130, the AlN intermediate layer 140, the AlGaN barrier layer 150, and the AlGaN barrier layer 150 are sequentially epitaxially laminated on the sapphire/SiC/Si substrate 110. Refer to Table 1 for the Al composition and thickness. The thickness of the AlGaN barrier layer 150 should be lower than the critical thickness. For example, when the Al component content of the AlGaN barrier layer 150 is 18at.%, the thickness of the AlGaN barrier layer 150 is 5nm. .

2) Device isolation: Glue photolithography, using etching process or ion implantation process to perform mesa isolation on the epitaxial layer.

3) Grow the 2DEG recovery layer 210 and the protective layer 220: Use the PECVD process to continuously grow a 5nm-thick Si layer as the 2DEG recovery layer 210 and a 20nm-thick SiNx layer as the protective layer 220 on the AlGaN barrier layer 150. Please explain. What is unique is that Si in the Si layer acts as a shallow donor in AlGaN and can be ionized at room temperature. Due to its surface doping effect, a 2DEG conductive channel can be formed in the channel.

4) Selective etching of the 2DEG recovery layer: apply glue on the protective layer 220 and photoetch the gate window, and use wet etching to remove the 2DEG recovery layer 210 and the protective layer 220 located in the gate window to form the gate trench structure 201.

5) Ohmic electrode production: Apply glue on the protective layer 220 and photoetch to expose the source and drain windows of the 2DEG recovery layer 210, and make the source electrode 410 and the drain electrode on the 2DEG recovery layer 210 exposed at the source and drain windows. 420.

First, a wet etching process is used to remove the protective layer 220 in the source and drain regions, and then an electron beam evaporation process is used to sequentially form a 22nm Ti layer, a 140nm Al layer, a 55nm Ni layer, and a 45nm layer on the exposed 2DEG recovery layer 210. Au layer; use a stripping process to remove the metal in the mask area, and quickly anneal it at 880°C for 30 seconds to form an ohmic contact.

6) Gate dielectric growth: Using the PEALD process at 300°C, aluminum oxide with a thickness of 20 nm is thermally grown on the protective layer 220 and the source electrode 410 and the drain electrode 420 as the gate dielectric layer 310.

7) Selective gate dielectric etching: Apply glue on the gate dielectric layer 310 and photoetch the source and drain windows, and use dry etching to remove the gate dielectric layer 310 exposed in the source and drain windows to expose the source electrodes 410 and Drain 420.

8) Make the gate electrode: Make the gate electrode 430 on the gate dielectric layer 310 in the gate trench structure.

An electron beam evaporation process is used to sequentially form a Ni layer with a thickness of 20 nm and an Au layer with a thickness of 100 nm on the gate dielectric layer 310, and a stripping process is used to remove metal in the mask area.

The thickness of the barrier layer used in the present invention is lower than the critical thickness for forming 2DEG, so that the device channel is initially in a depleted state. A thin Si layer is deposited on the surface of the barrier layer as a 2DEG recovery layer to restore the 2DEG concentration in the channel to form an enhanced device. .

The present invention is improved on the basis of the thin barrier structure, inherits the existing advantages of the thin barrier structure, and at the same time optimizes the shortcomings of the existing thin barrier structure. First, the relationship between the thickness of the barrier layer and the concentration of 2DEG is used. The thickness of the barrier layer is lower than the critical thickness for forming 2DEG, so that the device channel is initially in a depleted state. By changing the Al composition and The thickness changes the initial 2DEG concentration, which can realize threshold voltage regulation; and, the present invention grows a thin Si layer on the surface of the barrier layer as a 2DEG recovery layer. Compared with the SiNx layer, the Si layer has higher Si doping efficiency and can be more The 2DEG concentration is increased to a large extent, thereby increasing the saturation current density. Secondly, the present invention uses wet etching to remove the Si layer in the lower gate area to avoid the impact of etching damage.

It should be understood that the above embodiments are only to illustrate the technical concepts and characteristics of the present invention. Their purpose is to enable those familiar with the technology to understand the content of the present invention and implement it accordingly, and cannot limit the scope of protection of the present invention. All equivalent changes or modifications made based on the spirit and essence of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. The utility model provides an enhancement mode HEMT device structure, includes heterojunction and with heterojunction matched source electrode, drain electrode and grid, the heterojunction includes channel layer and barrier layer that stacks the setting, its characterized in that:

the barrier layer is formed of a semiconductor material containing Al, and the thickness of the barrier layer is smaller than a critical thickness capable of forming a two-dimensional electron gas with the channel layer by itself;

and the enhanced HEMT device structure further comprises a two-dimensional electron gas recovery layer, the two-dimensional electron gas recovery layer is arranged on the barrier layer, the source electrode and the drain electrode are arranged on the two-dimensional electron gas recovery layer, the two-dimensional electron gas recovery layer is used for recovering the concentration of channel two-dimensional electron gas, a grid electrode area of the two-dimensional electron gas recovery layer is provided with a grid groove structure, the bottom of the grid groove structure is located on the barrier layer, a notch is located on the two-dimensional electron gas recovery layer, and the grid electrode is arranged in the grid groove structure.

2. The enhancement HEMT device structure of claim 1, wherein: the thickness of the barrier layer is not less than 2nm;

and/or, the Al component content of the barrier layer is 3at.% to 30at.%;

and/or the thickness of the barrier layer is 2 nm-52 nm.

3. The enhancement-mode HEMT device structure of claim 1 or 2, wherein: the barrier layer is made of AlGaN, and the channel layer is made of GaN.

4. The enhancement-mode HEMT device structure of claim 1 or 2, wherein: the two-dimensional electron gas recovery layer is made of Si; and/or the thickness of the two-dimensional electron gas recovery layer is 1 nm-10 nm.

5. The enhancement HEMT device structure of claim 1, wherein: the enhanced HEMT device structure further comprises a protective layer, wherein the protective layer is arranged on the two-dimensional electron gas recovery layer in a lamination mode, and the protective layer is at least used for protecting the two-dimensional electron gas recovery layer from being oxidized;

preferably, the protective layer is arranged between the grid electrode and the source electrode and between the grid electrode and the drain electrode, and the notch of the grid groove structure is positioned on the protective layer;

preferably, the material of the protective layer comprises SiNx or AlN;

preferably, the thickness of the protective layer is 20 nm-30 nm;

and/or, the enhanced HEMT device structure further comprises a gate dielectric layer, wherein the gate dielectric layer is at least arranged in the gate groove structure, and the gate is arranged on the gate dielectric layer;

preferably, the material of the gate dielectric layer comprises a compound which does not contain Si;

preferably, the gate dielectric layer is made of hafnium oxide, aluminum nitride or aluminum oxide.

6. The manufacturing method of the enhanced HEMT device structure is characterized by comprising the following steps:

manufacturing a heterojunction, wherein the heterojunction comprises a channel layer and a barrier layer which are stacked, the barrier layer is formed by a semiconductor material containing Al, and the thickness of the barrier layer is smaller than the critical thickness capable of forming two-dimensional electron gas with the channel layer;

forming a two-dimensional electron gas recovery layer in a non-grid region of the barrier layer, wherein the two-dimensional electron gas recovery layer is used for recovering the concentration of channel two-dimensional electron gas, and the two-dimensional electron gas recovery layer and the barrier layer are also enclosed to form a grid groove structure, and the bottom of the grid groove structure is positioned on the barrier layer;

and forming a source electrode and a drain electrode on the two-dimensional electron gas recovery layer, wherein the source electrode and the drain electrode are electrically connected through the two-dimensional electron gas, a gate dielectric layer is formed on the two-dimensional electron gas recovery layer and in the gate groove structure, and a gate electrode is formed on the gate dielectric layer.

7. The method of manufacturing according to claim 6, wherein: the Al component content of the barrier layer is 3at.% to 30at.%; and/or the thickness of the barrier layer is 2 nm-52 nm;

and/or the material of the barrier layer comprises AlGaN, and the material of the channel layer comprises GaN.

8. The method according to claim 6, characterized in that it comprises: forming a two-dimensional electron gas recovery layer on the barrier layer, and removing the two-dimensional electron gas recovery layer in the grid region to form the grid groove structure;

preferably, the manufacturing method specifically comprises the following steps: removing the two-dimensional electron gas recovery layer in the grid electrode area by adopting a wet etching mode;

and/or the material of the two-dimensional electron gas recovery layer comprises Si; and/or the thickness of the two-dimensional electron gas recovery layer is 1 nm-10 nm.

9. The method of manufacturing of claim 6, further comprising: forming a protective layer on the two-dimensional electron gas recovery layer, wherein the protective layer is arranged between a grid electrode region and source electrode region as well as between the grid electrode region and drain electrode region, the protective layer is at least used for protecting the two-dimensional electron gas recovery layer from oxidization, the protective layer, the two-dimensional electron gas recovery layer and the barrier layer are jointly enclosed to form the grid groove structure, and a notch of the grid groove structure is positioned in the protective layer;

preferably, the manufacturing method specifically comprises the following steps: sequentially forming a laminated two-dimensional electron gas recovery layer and a protective layer on the barrier layer, and removing the protective layer and the two-dimensional electron gas recovery layer which are positioned in a grid electrode area, thereby forming the grid groove structure;

removing the protective layer in a source region and a drain region, forming a source on the two-dimensional electron gas recovery layer in the source region, and forming a drain on the two-dimensional electron gas recovery layer in the drain region;

preferably, the manufacturing method specifically comprises the following steps: removing the protective layer and the two-dimensional electron gas recovery layer which are positioned in the grid electrode area by adopting a wet etching mode;

preferably, the material of the protective layer comprises SiNx or AlN;

preferably, the thickness of the protective layer is 20 nm-30 nm.

10. The method of manufacturing of claim 6, further comprising: forming a gate dielectric layer in the gate groove structure, wherein the gate is arranged on the gate dielectric layer;

preferably, the material of the gate dielectric layer comprises a compound which does not contain Si;

preferably, the gate dielectric layer is made of hafnium oxide, aluminum nitride or aluminum oxide.