CN117613086A - A kind of LDMOS based on hemispherical insulating layer to improve HCI and its preparation method - Google Patents

Abstract

The invention discloses an LDMOS based on a hemispherical insulating layer to improve HCI and a preparation method. The LDMOS includes: a trench opened on the upper layer of the N-drift layer; the distance between the bottom of the trench and the bottom surface of the polysilicon field plate is h2; The bottom of the trench is located directly below the sidewall surface of the polysilicon field plate; an insulating material is deposited in the trench. By setting the shape of the STI under the polycrystalline silicon field plate into a hemispherical shape, the present invention makes the thickness of the STI at the bottom of the edge of the polycrystalline silicon field plate where the electric field is strongest thicker than elsewhere. The hemispherical design structure also avoids the risk of strong electric fields at sharp corners. It improves the device damage caused by the hot carrier injection effect of LDMOS and improves the reliability of LDMOS.

Description

A kind of LDMOS based on hemispherical insulating layer to improve HCI and its preparation method

Technical field

The invention relates to the field of semiconductor technology, and in particular to an LDMOS based on a hemispherical insulating layer that improves HCI and a preparation method.

Background technique

When carriers obtain a large amount of energy from the outside world, they can become hot carriers. For example, under the action of a strong electric field, carriers continue to drift along the direction of the electric field, continue to accelerate, and obtain a large kinetic energy, thus becoming hot carriers. For MOS devices, when the characteristic size of the MOS device is small, a strong electric field can be generated even at a not high voltage, resulting in the easy occurrence of hot carriers. Therefore, hot carriers are prone to appear in small-size MOS devices and large-scale integrated circuits.

Hot carriers are carriers with high energy, and their kinetic energy is higher than the average thermal motion energy, that is, the motion speed of hot carriers is also very high. Hot carriers will induce the degradation of MOS devices. This phenomenon is caused by the injection of high-energy electrons and holes into the gate oxide layer. During the injection process, interface states and oxide layer trap charges will be generated, causing damage to the oxide layer. As the degree of damage increases, the current and voltage characteristics of MOS devices will change. When the MOS device parameters change beyond a certain limit, the MOS device will fail.

HCI, the hot carrier injection effect, refers to the electrical performance degradation caused by the injection of high-energy electrons or holes in semiconductor devices. It is a key issue affecting the reliability of LDMOS and will also affect the service life of LDMOS. . The hot carrier injection effect is due to the increased probability of ionization collision caused by the location of the strong electric field in the LDMOS device, which causes the hot carriers to overcome the interface potential between silicon and silicon dioxide and tunnel into the oxide layer, causing damage to the oxide layer of the LDMOS device. This damage will cause the charge density of the oxide layer to change, thereby affecting the electrical performance of the device, causing the electrical parameters of the device to drift or degrade.

Contents of the invention

In order to solve at least one of the technical problems raised above, the purpose of the present invention is to provide an LDMOS and a preparation method based on a hemispherical insulating layer to improve HCI. By setting the shape of the STI under the polysilicon field plate into a hemispherical shape, the polysilicon field plate The STI thickness at the bottom where the edge electric field is strongest is thicker than elsewhere. The hemispherical design structure also avoids the generation of strong electric fields at sharp corners, improves device damage caused by the hot carrier injection effect of LDMOS, and improves the performance of LDMOS. Reliability.

The object of the present invention is achieved by the following technical means:

In a first aspect, the present invention provides an LDMOS with improved HCI based on a hemispherical insulating layer, including: a trench opened on the upper layer of the N-drift layer;

The distance between the bottom of the trench and the bottom surface of the polysilicon field plate is h2;

The bottom of the trench is located directly below the sidewall surface of the polysilicon field plate;

The trenches have insulating material deposited therein.

Preferably, it also includes: polysilicon field plate;

The polysilicon field plate is located above the P-body layer, the N-drift layer and the trench, and is adjacent to the P-body layer and the N-drift layer.

Preferably, the groove is composed of multiple arc sections.

Preferably, the width of the groove ranges from 0.5 to 10um.

Preferably, the insulating material includes: SiO2.

Preferably, the cross section of the groove is semicircular.

Preferably, the distance h2 between the bottom of the trench and the bottom surface of the polysilicon field plate ranges from 0.25 to 5um.

In a second aspect, the present invention provides an LDMOS preparation method based on a hemispherical insulating layer to improve HCI, including:

Etch the upper layer of the N-drift layer to form a hemispherical trench;

Deposit silicon dioxide in the trench to form a hemispherical insulating layer;

Depositing polysilicon field plates;

Etched polysilicon field plates;

The upper layer of N-drift layer is ion implanted to form P-body layer, N+ layer and P+ layer.

Preferably, etching the upper layer of the N-drift layer to form a hemispherical trench specifically includes: using photolithography to define the etching area of the hemispherical trench, and then using an isotropic etching method to etch the upper layer of the N-drift layer to form a hemispherical trench. .

Preferably, the etching of the polysilicon field plate specifically includes: using photolithography to define the area to be etched, and etching the polysilicon field plate using a polysilicon etching method.

Compared with the existing technology, the beneficial effects of the present invention are:

By setting the shape of the STI under the polycrystalline silicon field plate into a hemispherical shape, the present invention makes the thickness of the STI at the bottom of the edge of the polycrystalline silicon field plate where the electric field is strongest thicker than elsewhere. The hemispherical design structure also avoids the risk of strong electric fields at sharp corners. It improves the device damage caused by the hot carrier injection effect of LDMOS and improves the reliability of LDMOS.

It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not restrictive of the disclosure.

Description of drawings

In order to more clearly explain the technical solutions in the embodiments of the present application or the background technology, the drawings required to be used in the embodiments or the background technology of the present application will be described below.

The accompanying drawings herein are incorporated into and constitute a part of this specification. They illustrate embodiments consistent with the disclosure and, together with the description, serve to explain the technical solutions of the disclosure.

Figure 1 is a schematic structural diagram of an LDMOS based on a hemispherical insulating layer improved HCI provided by an embodiment of the present invention;

FIG. 2 is a schematic flow chart of an LDMOS preparation method based on a hemispherical insulating layer modified HCI provided by an embodiment of the present invention.

Implementation

In order to enable those in the technical field to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only These are part of the embodiments of this application, but not all of them. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

The terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish different objects, rather than describing a specific sequence. Furthermore, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes Other steps or units inherent to such processes, methods, products or devices.

The term "and/or" in this article is just an association relationship that describes related objects, indicating that three relationships can exist. For example, A and/or B can mean: A exists alone, A and B exist simultaneously, and they exist alone. B these three situations. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, and C, which can mean including from A, Any one or more elements selected from the set composed of B and C.

Reference herein to "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.

In addition, in order to better explain the present invention, numerous specific details are given in the following detailed description. It will be understood by those skilled in the art that the present invention may be practiced without certain specific details. In some instances, methods, means, components and circuits that are well known to those skilled in the art are not described in detail in order to emphasize the gist of the present invention.

When carriers obtain a large amount of energy from the outside world, they can become hot carriers. For example, under the action of a strong electric field, carriers continue to drift along the direction of the electric field, continue to accelerate, and obtain a large kinetic energy, thus becoming hot carriers. For MOS devices, when the characteristic size of the MOS device is small, a strong electric field can be generated even at a not high voltage, resulting in the easy occurrence of hot carriers. Therefore, hot carriers are prone to appear in small-size MOS devices and large-scale integrated circuits. Hot carriers are carriers with high energy, and their kinetic energy is higher than the average thermal motion energy, that is, the motion speed of hot carriers is also very high. Hot carriers will induce the degradation of MOS devices. This phenomenon is caused by the injection of high-energy electrons and holes into the gate oxide layer. During the injection process, interface states and oxide layer trap charges will be generated, causing damage to the oxide layer. As the degree of damage increases, the current and voltage characteristics of MOS devices will change. When the MOS device parameters change beyond a certain limit, the MOS device will fail. HCI, the hot carrier injection effect, refers to the electrical performance degradation caused by the injection of high-energy electrons or holes in semiconductor devices. It is a key issue affecting the reliability of LDMOS and will also affect the service life of LDMOS. . The hot carrier injection effect is due to the increased probability of ionization collision caused by the location of the strong electric field in the LDMOS device, which causes the hot carriers to overcome the interface potential between silicon and silicon dioxide and tunnel into the oxide layer, causing damage to the oxide layer of the LDMOS device. This damage will cause the charge density of the oxide layer to change, thereby affecting the electrical performance of the device, causing the electrical parameters of the device to drift or degrade.

By setting the shape of the STI under the polycrystalline silicon field plate into a hemispherical shape, the present invention makes the thickness of the STI at the bottom of the edge of the polycrystalline silicon field plate where the electric field is strongest thicker than elsewhere. The hemispherical design structure also avoids the risk of strong electric fields at sharp corners. It improves the device damage caused by the hot carrier injection effect of LDMOS and improves the reliability of LDMOS.

Example 1

An LDMOS with improved HCI based on a hemispherical insulating layer is provided, including: a trench opened on the upper layer of the N-drift layer;

The distance between the bottom of the trench and the bottom of the polysilicon field plate is h2;

The bottom of the trench is located directly below the sidewall surface of the polysilicon field plate;

The trenches are deposited with insulating material.

LDMOS is used in the field of high-voltage power. Its reliability is an important indicator to measure the performance of LDMOS devices. Due to the existence of high drain voltage and the reduction of the size of LDMOS devices, the strong field effect of LDMOS has to be seriously considered, and the strong field directly causes It is the hot carrier injection effect of LDMOS devices.

Hot carriers: When channel electrons pass through a strong field region, the electrons gain additional energy from the electric field, breaking the energy balance between the electrons and the crystal lattice, that is, this additional energy cannot be transferred to the crystal lattice. These high-energy carriers are called hot carriers. Regarding the structure of LDMOS, the PN junction near the drift region generates hot carriers in the LDMOS device and can affect the gate current.

In the strong field area, because there are more high-energy electrons than in other areas, another main phenomenon is caused, namely impact ionization. High-energy electrons strike the lattice, creating additional electron-hole pairs. The newly added electrons become part of the drain current, and the holes generated have various places to go. Most of it flows to the substrate and becomes the substrate current, and a small part flows to the gate and source. Hot carriers entering the gate will generate oxide charges and interface traps, leading to the degradation of LDMOS device performance, especially threshold voltage drift, transconductance degradation, etc., which affect the life of the LDMOS device.

The number of hot carriers can be reflected by the substrate current. The size of the substrate current is determined by the drain current, field strength, and collision coefficient. It can be seen that collision ionization occurs preferentially in areas with high field strength and current concentration. The beak area and drain area under the LDMOS field plate are places where current is concentrated. The beak area under the field plate is a place where current is dense. When the field strength is large enough, the number of secondary electron-hole pairs generated by high-speed carriers hitting the crystal lattice will increase significantly, that is, the impact ionization intensity of this area will be enhanced.

In this embodiment, a trench is opened in the upper layer of the N-drift layer. The bottom of the trench is located directly below the side wall surface of the polysilicon field plate, and the distance from the bottom surface of the polysilicon field plate is h2. The maximum electric field is at the edge of the polysilicon field plate. The thickness h2 of the strong bottom is the thickest, thereby reducing the hot carrier injection effect at the bottom of the edge of the polysilicon field plate.

By setting the shape of the STI under the polycrystalline silicon field plate into a hemispherical shape, the present invention makes the thickness of the STI at the bottom of the edge of the polycrystalline silicon field plate where the electric field is strongest thicker than elsewhere. The hemispherical design structure also avoids the risk of strong electric fields at sharp corners. It improves the device damage caused by the hot carrier injection effect of LDMOS and improves the reliability of LDMOS.

Preferably, it also includes: polysilicon field plate;

The polysilicon field plate is located above the P-body layer, N-drift layer and trench, and is adjacent to the P-body layer and N-drift layer.

Field plate is an electric field optimization technology widely used in lateral power devices. This technology increases the field plate and improves the withstand voltage performance of the LDMOS device without changing the on-resistance of the LDMOS device. The surface charge of the LDMOS device will affect the breakdown electric field of the device. When there are power lines on the surface of the drift zone, these power lines will terminate on the surface charge of the LDMOS device and will be affected by the electric field on the surface of the LDMOS device, the shape of the drift zone surface and the electric field. The distribution will change as a result, thereby changing the breakdown voltage of the LDMOS device. Field plate technology covers the surface of the LDMOS device with a field plate and changes the breakdown voltage of the LDMOS device by changing the field plate voltage.

By introducing two centrally symmetrical vertical field plates in the oxide trench, the goals of increasing the breakdown voltage of the device and reducing the on-resistance of the device can be achieved. One of the two vertical field plates in the device is connected to the gate and the other is connected to the drain. In the off state, the vertical field plate introduces a high electric field into the oxidation trench, forming two new electric field peaks near the trench surface, optimizing the overall electric field of the device. The auxiliary depletion effect caused by the gate field plate helps the drift region reach higher doping concentrations. In the on state, due to the high concentration of the doped region, the specific on-resistance of the device is smaller, which alleviates the contradictory relationship between the breakdown voltage and the specific on-resistance of the device to a certain extent, and improves the performance of the device. In addition to being embedded in trenches and connected to electrodes, field plate technology can also be used directly on electrodes to optimize and adjust the surface electric field of LDMOS devices and improve the performance of LDMOS devices. Field plate technology is connected to different electrodes to form different field plates, such as source field plates, gate field plates and drain field plates.

Preferably, the groove is composed of multiple arc segments.

In LDMOS devices, the strong field region is usually located at the edge or tip of the region. In some embodiments, the shape of the cross-section of the STI trench is a trapezoid. The surface curvature increases at one end of the trapezoidal sidewall surface, and the electric field intensity increases sharply. This results in the existence of a strong electric field on the trapezoidal sidewall surface, where Hot carrier injection damage is more likely to occur. In this embodiment, the trench located just below the side wall of the polysilicon field plate is composed of a multi-ended arc surface, which avoids the generation of strong electric fields at sharp corners and improves the hot carrier injection effect of the LDMOS device.

Preferably, the width of the groove ranges from 0.5-10um.

Preferably, the insulating material includes: SiO2.

In some embodiments, the insulating material of the trench may be silicon dioxide, other oxides deposited by high-density plasma deposition, or other insulating materials such as undoped silicon glass. Silicon dioxide has advantages as an insulating material for trenches. Silicon dioxide has good high-temperature resistance and can be manufactured at high temperatures during the production process. Secondly, the cost of silicon dioxide is lower than other insulating materials. Using silicon dioxide as an insulating material is beneficial to cost savings.

Preferably, the cross-section of the groove is semicircular.

In some embodiments, the cross-sectional shape of the groove may be semi-elliptical or semi-circular. The shape of the cross-section of the trench is set to a semicircle, which has a better effect on improving the strong electric field of the LDMOS device. At the same time, the etching of the trench can be more convenient and precise, saving trench production and labor costs.

Preferably, the distance h2 between the bottom of the trench and the bottom surface of the polysilicon field plate ranges from 0.25 to 5um.

The shape and size of the trench will affect the current in the drift region, thereby affecting the performance of the LDMOS device. For example, improper design of the trench will block the current path from source to drain, resulting in the generation of impact ionization and hot carriers. Impact ionization generates The interface states and hot carriers will affect the performance of LDMOS devices. Appropriate trench size and shape can make the drift region depleted more completely and also improve the breakdown voltage of the LDMOS device. In this embodiment, the width of the trench is in the range of 0.5-10um, and the distance h2 between the bottom of the trench and the bottom surface of the polysilicon field plate is in the range of 0.25-5um.

Example 2

An LDMOS preparation method based on hemispherical insulating layer-improved HCI is provided, including:

S100, etching the upper layer of the N-drift layer to form a hemispherical trench;

S200, deposit silicon dioxide in the trench to form a hemispherical insulating layer;

The STI process overcomes the limitations of the LOCOS process, and its excellent performance is obtained by integrating a series of complex processes, mainly including trench etching, filling and chemical mechanical polishing planarization. In the formation of trenches, the STI process generally uses Si3N4 as an isolation mask. In order to prevent the stress of Si3N4 from causing defects in the silicon substrate, a thin layer of Si02 is used as a buffer layer to release the stress between Si3N4 and the silicon substrate. . SiN4 serves as a polishing barrier during the subsequent chemical mechanical polishing planarization process. Its thickness determines the step height of the active area and field area, and its optimal selection should be to ensure that the step height after chemical mechanical polishing planarization is sufficient to allow cleaning and etching before growing gate oxide. In some embodiments, 20 nm of SiO2 is grown as a buffer layer at 1000°C in an O2 and HCI atmosphere, and then 200 nm of Si3N4 is deposited using a LPCVD process, and then annealed at 800°C in a N2 atmosphere for 30 minutes. After Si3N4 is annealed, photoresist is used as an etching mask for photolithography. The trenches are formed by reactive ion etching of the silicon substrate. The factors that affect etching mainly include temperature, pressure, RF power, etching gas and its components, etc. The most critical thing in the etching process is to control the shape of the trench. The shape of the trench affects trench filling.

The main step in trench filling is to deposit SiO2. The corrosion rate of deposited SiO2 is generally higher than that of grown SiO2. A high corrosion rate will lead to the loss of field SiO2 during the surface cleaning process before generating gate SiO2. The corrosion rate of deposited SiO2 can be reduced by a densification process, such as annealing at 800-1050°C, so that the corrosion rate of the filling medium is reduced to close to the corrosion rate of thermally grown SiO2. In some embodiments, PECVD TEOS SiO2 is used as the trench filling medium. Before filling the trench with SiO2, 15nm SiO2 and 15nm Si3N4 are deposited using the LPCVD process to protect the corners of the trench during chemical mechanical polishing planarization. It is not damaged during the process. After the trench is filled, it is annealed in an N2 atmosphere at 900°C to reduce the corrosion rate of SiO2.

CMP planarization is considered to be the core of the STI process. It uses the combined action of chemistry and machinery to achieve planarization of the silicon wafer surface. The difficulty with the CMP process is that its planarization effect is related to the pattern size on the silicon wafer surface. After CMP, after SiN4 is exposed on the wide active area, over-polishing often occurs in the wide isolation area and the narrow active area, resulting in dishing phenomenon, which will cause the step height between the active area and the field area after Si3N4 removal The non-uniformity can even damage the silicon substrate in the narrow active area. In some embodiments, after CMP, hot phosphoric acid is used to remove the exposed Si3N4, and finally a sacrificial oxide layer is grown on the surface of the silicon wafer and floated away to further remove defects and damage on the surface of the silicon wafer, providing a basis for gate oxidation and Prepare for polysilicon gate formation.

S300, deposited polysilicon field plate;

S400, etched polysilicon field plate;

Deposition processes are divided into chemical vapor deposition (CVD) and physical vapor deposition (PVD). CVD refers to the method of chemically depositing coatings on the surface of wafers, generally by applying energy to a mixed gas. Assuming that substance (A) is deposited on the wafer surface, two gases (B and C) that can generate substance (A) are first input to the deposition equipment, and then energy is applied to the gas to promote a chemical reaction between gases B and C.

PVD (physical vapor deposition) coating technology is mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion plating. The main methods of physical vapor deposition include: vacuum evaporation, sputtering coating, arc plasma coating, ion coating and molecular beam epitaxy, etc. Corresponding vacuum coating equipment includes vacuum evaporation coating machines, vacuum sputtering coating machines and vacuum ion coating machines.

Etching is the process of selectively removing unwanted materials from the surface of silicon wafers using chemical or physical methods. It is a general term for stripping and removing materials through solutions, reactive ions or other mechanical means. Etching technology is mainly divided into dry etching and wet etching. Dry etching mainly uses reactive gases and plasma for etching; wet etching mainly uses chemical reagents to react with the etched material for etching.

Ion beam etching is a physical dry etching process. Thereby, argon ions are radiated onto the surface in an ion beam of about 1 to 3 keV. Due to the energy of the ions, they hit the material on the surface. With the wafer vertical or tilted into the ion beam, the etching process is absolutely anisotropic. Selectivity is low as there is no difference between layers. The gases and ground material are removed by a vacuum pump, but since the reaction products are not gaseous, particles can deposit on the wafer or chamber walls. All materials can be etched using this method, with very low wear on vertical walls due to vertical radiation.

Plasma etching is an absolute chemical etching process. The advantage is that the wafer surface will not be damaged by accelerated ions. Due to the mobile particles of the etching gas, the etching profile is isotropic, so this method is used to remove the entire film layer (e.g. backside cleaning after thermal oxidation). One type of reactor used for plasma etching is the downstream reactor. Thus, plasma is ignited at a high frequency of 2.45GHz through impact ionization, and the location of impact ionization is separated from the wafer.

The etch rate depends on the pressure, power of the high frequency generator, process gas, actual gas flow and wafer temperature. Anisotropy increases with increasing high-frequency power, decreasing pressure, and decreasing temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes, and the material of the electrodes. If the distance is too small, the plasma cannot be dispersed unevenly, resulting in inhomogeneity. If the distance between the electrodes is increased, the etch rate decreases because the plasma is distributed in an enlarged volume. For electrodes, carbon has proven to be the material of choice. Because fluorine and chlorine gases also attack carbon, the electrodes create a uniformly strained plasma so the edges of the wafer are affected in the same way as the center of the wafer. Selectivity and etch rate are highly dependent on the process gas. For silicon and silicon compounds, fluorine gas and chlorine gas are mainly used.

S500, ion implantation is performed on the upper layer of the N-drift layer to form a P-body layer, an N+ layer and a P+ layer.

+ is heavily doped (high doping concentration), - is lightly doped (low doping concentration), P-type doped IIIA group elements, such as boron, aluminum, gallium, indium, and thallium. N-type doping with Group VA elements such as nitrogen, phosphorus, arsenic, antimony, bismuth and enrium. Heavily doped semiconductors can be used to manufacture high-performance electronic devices. The doping concentration of heavy doping is above 10 ¹⁹ cm ^-3 . The methods for preparing P+ doping include diffusion and ion implantation. The diffusion method mixes impurity ions with the semiconductor material, and then heats the mixture to a high temperature to diffuse the impurity ions into the semiconductor material. Ion implantation accelerates the impurity ions to high speed and then injects them into the semiconductor material. Lightly doped semiconductor refers to a type of semiconductor material in which a low concentration of impurity atoms is added during the preparation of semiconductor materials. Doped impurity atoms can change the electrical properties of semiconductor materials, thereby improving their performance and functionality. In lightly doped semiconductors, the concentration of doped impurity atoms is usually lower than the intrinsic concentration of the semiconductor material (the intrinsic concentration refers to the concentration of impurity atoms in a pure semiconductor). The doped impurity atoms must also have a similar lattice size and electronic structure to the semiconductor material atoms to ensure that they can successfully combine with the semiconductor material and move in the semiconductor material. After doping impurity atoms, the electrical properties of lightly doped semiconductors will change accordingly. The most important change is the increase in electrical conductivity. This is because the added impurity atoms can form additional free electrons or holes in the semiconductor, thereby enhancing the conductive properties of the semiconductor material. In addition, lightly doped semiconductors can also change the bandgap width, carrier mobility, optical absorption spectrum and other properties of semiconductor materials, thereby expanding their applications in electronics, optoelectronics, chemistry and other fields. The preparation of lightly doped semiconductors usually uses techniques such as ion implantation and melt diffusion. Ion implantation is to accelerate doping elements to high speed through a high-voltage electric field, and then bombard the semiconductor surface to inject them into the semiconductor lattice. Melting diffusion places the semiconductor chip on a doped material block and then heats it to a high temperature. The doped atoms are melted and diffused into the semiconductor material. In practical applications, lightly doped semiconductors are widely used in circuits, solar cells, nanomaterials and other fields. For example, after silicon is doped with aluminum, n-type silicon can be formed, whose conductivity is significantly improved and can be used to manufacture pn junction solar cells. In addition, lightly doped semiconductors can also be used to prepare microelectronic devices such as metal oxide semiconductor field effect transistors (MOSFETs) and low-noise power amplifiers. In the field of nanotechnology, lightly doped semiconductors can be used to prepare various optoelectronic and biochemical sensors and have broad application prospects.

Preferably, etching the upper layer of the N-drift layer to form a hemispherical trench specifically includes: using photolithography to define the etching area of the hemispherical trench, and then using an isotropic etching method to etch the upper layer of the N-drift layer to form a hemispherical trench.

Preferably, etching the polysilicon field plate specifically includes: using photolithography to define the area to be etched, and etching the polysilicon field plate using a polysilicon etching method.

Photolithography is a method of making patterns using photoresist. This step uses exposure and development to carve a geometric structure on the photoresist layer, and then transfers the pattern on the photomask to the substrate through an etching process. Through a metallization process, a metal layer only a few nanometers thick is arranged on the silicon substrate. This layer of metal is then covered with a layer of photoresist. This layer of photoresist can be dissolved by a specific solution after exposure. By irradiating specific light waves through the photomask onto the photoresist, the photoresist can be selectively exposed. A developer is then used to dissolve the illuminated area so that the pattern on the photomask appears on the photoresist. Usually, some properties of the remaining photoresist will be improved through drying measures. After the above steps are completed, the substrate can be selectively etched or ion implanted. The undissolved photoresist will protect the substrate from being changed during these processes. After etching or ion implantation is completed, the final step of photolithography will be carried out, that is, the photoresist is removed to facilitate other steps of semiconductor device manufacturing.

Photoresist: The photosensitive material used in photolithography is called photoresist, which is mainly divided into two types: positive photoresist and negative photoresist. The unilluminated portions of positive photoresist are retained after development, while the exposed portions of negative photoresist are retained after development. Photoresist not only needs to be sensitive to specified light, but also needs to remain stable during subsequent metal etching and other processes. Different photoresists generally have different photosensitive properties. Some are sensitive to all ultraviolet spectrums, some are only sensitive to specific spectrums, and some are sensitive to X-rays or electron beams. Photoresist needs to be stored in special light-shielding containers.

According to different exposure methods, photolithography can be divided into projection exposure, proximity exposure and contact exposure. Projection exposure is an exposure method that uses lenses or mirrors to project the pattern on the mask onto the substrate. In this exposure method, due to the long distance between the mask and the silicon wafer, damage to the mask can be completely avoided. In order to improve the resolution, in projection exposure, only a small part of the silicon wafer is exposed at a time, and then the entire silicon wafer is exposed using scanning and step-by-step repetition. Proximity exposure leaves a small gap between the silicon wafer and the mask during exposure. This gap is generally between 10-25um. This gap can greatly reduce damage to the mask. The resolution of proximity exposure is lower, generally between 2-4um. The main advantage of proximity exposure compared to projection exposure is higher production efficiency. In contact exposure technology, the silicon wafer coated with photoresist is in direct contact with the mask. Due to the close contact between the photoresist and the mask, relatively high resolution can be obtained. However, contact exposure also has disadvantages. The main problem is that it is easy to damage the mask and photoresist.

By adding the developer after the exposure process, the photosensitive areas of the positive photoresist and the non-photosensitive areas of the negative photoresist will be dissolved in the developer. After this step is completed, the pattern in the photoresist layer can be revealed. In order to improve the resolution, almost every kind of photoresist has a special developer to ensure high-quality development results. Photoresist removal methods include wet removal and dry removal. Wet removal is divided into using organic solvents to remove photoresist and using inorganic solvents to oxidize the carbon element of the photoresist into carbon dioxide. Dry removal is divided into The photoresist is stripped off using plasma.

By setting the shape of the STI under the polycrystalline silicon field plate into a hemispherical shape, the present invention makes the thickness of the STI at the bottom of the edge of the polycrystalline silicon field plate where the electric field is strongest thicker than elsewhere. The hemispherical design structure also avoids the risk of strong electric fields at sharp corners. It improves the device damage caused by the hot carrier injection effect of the LDMOS device and improves the reliability of the LDMOS.

In some embodiments, the functions or modules provided by the device provided by the embodiments of the present disclosure can be used to execute the methods described in the above method embodiments. For specific implementation, refer to the description of the above method embodiments. For the sake of brevity, here No longer. In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in or transmitted over a computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server or data center to another through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means. A website site, computer, server or data center for transmission. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more available media integrated. The available media may be magnetic media (eg, floppy disk, hard disk, tape), optical media (eg, digital versatile disc (DVD)), or semiconductor media (eg, solid state disk (SSD)) wait.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments are implemented. This process can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, , may include the processes of the above method embodiments. The aforementioned storage media include: read-only memory (ROM) or random access memory (RAM), magnetic disks, optical disks and other media that can store program codes.

The above descriptions are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be practiced in other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims (10)

1. An LDMOS based on a hemispherical insulating layer to improve HCI, which is characterized by including: a trench opened on the upper layer of the N-drift layer; The distance between the bottom of the trench and the bottom surface of the polysilicon field plate is h2; The bottom of the trench is located directly below the sidewall surface of the polysilicon field plate; The trenches have insulating material deposited therein. 2. A kind of LDMOS based on hemispherical insulating layer improved HCI according to claim 1, characterized in that it also includes: a polysilicon field plate; The polysilicon field plate is located above the P-body layer, the N-drift layer and the trench, and is adjacent to the P-body layer and the N-drift layer. 3. An LDMOS improved HCI based on a hemispherical insulating layer according to claim 1, characterized in that the trench is composed of multiple arc surfaces. 4. An LDMOS based on a hemispherical insulating layer to improve HCI according to claim 1, characterized in that the width of the trench ranges from 0.5 to 10um. 5. A LDMOS based on a hemispherical insulating layer to improve HCI according to claim 1, characterized in that the insulating material includes: SiO2. 6. An LDMOS improved HCI based on a hemispherical insulating layer according to claim 1, characterized in that the cross section of the trench is semicircular. 7. An LDMOS improved HCI based on a hemispherical insulating layer according to claim 1, characterized in that the distance h2 between the bottom of the trench and the bottom surface of the polysilicon field plate ranges from 0.25 to 5um. 8. A LDMOS preparation method based on hemispherical insulating layer improved HCI, which is characterized by including: Etch the upper layer of the N-drift layer to form a hemispherical trench; Deposit silicon dioxide in the trench to form a hemispherical insulating layer; Depositing polysilicon field plates; Etched polysilicon field plates; The upper layer of N-drift layer is ion implanted to form P-body layer, N+ layer and P+ layer. 9. A kind of LDMOS based on hemispherical insulating layer improved HCI according to claim 8, characterized in that the etching of the upper layer of the N-drift layer to form a hemispherical trench is specifically: defining a hemispherical trench using photolithography. The etched area is then used to etch the upper layer of the N-drift layer using an isotropic etching method to form a hemispherical trench. 10. A kind of LDMOS based on hemispherical insulating layer improved HCI according to claim 8, characterized in that the etching of the polysilicon field plate specifically includes: defining the area to be etched using photolithography, and etching using polysilicon etching. Polysilicon field plates.