CN117253925A - STI type LDMOS with groove field plate and preparation method - Google Patents
STI type LDMOS with groove field plate and preparation method Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/65—Lateral DMOS [LDMOS] FETs
- H10D30/655—Lateral DMOS [LDMOS] FETs having edge termination structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
- H10D64/112—Field plates comprising multiple field plate segments
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
- H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses an STI type LDMOS with a groove field plate and a preparation method thereof, wherein the LDMOS comprises a polysilicon field plate; the polysilicon field plate is provided with a groove; the recess is located directly above the STI top side edge. The invention reduces the hot carrier injection effect and time-dependent dielectric breakdown caused by the pit formed at the top side edge of the STI while maintaining the breakdown voltage of the LDMOS device by forming the groove at the position of the polysilicon field plate right above the top side edge of the STI.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an STI type LDMOS with a groove field plate and a preparation method thereof.
Background
DMOS is a double diffused metal oxide semiconductor field effect transistor, and is mainly of two types, VDMOS and LDMOS, respectively. The LDMOS is a lateral diffusion metal oxide semiconductor, is used as a high-voltage power device, and is widely applied to a radio frequency power integrated circuit due to the advantages of high voltage resistance, high transconductance, high gain and the like. The LDMOS device is composed of hundreds to thousands of LDMOS cells of a single structure.
When the carriers acquire a large amount of energy from the outside, they can become hot carriers. For example, under the action of a strong electric field, carriers drift continuously along the direction of the electric field and accelerate continuously, so that great kinetic energy can be obtained, and the carriers become hot carriers. The hot carriers are carriers with high energy, which kinetic energy is higher than the average thermal movement energy, i.e. the movement speed of the hot carriers is also high. The hot carrier can induce the degradation of the MOSFET device, which is caused by the injection of high-energy electrons and holes into the gate oxide layer, and interfacial states and oxide layer trapping charges can be generated in the injection process, so that the oxide layer is damaged. As the degree of damage increases, the current-voltage characteristics of the MOSFET device change. When the MOSFET device parameters change beyond a certain limit, the MOSFET device will fail.
Time-dependent dielectric breakdown, also known as time-dependent breakdown, refers to the gradual increase in leakage current when the gate oxide is operated under bias conditions, which eventually results in breakdown, thereby rendering the gate oxide non-insulating. With the development of semiconductor technology, STI structures are developed, and STI has been widely used in semiconductor structures due to its superior isolation characteristics. In the fabrication process of the STI-type LDMOS, a pit is easily formed at the top side edge of the STI when the STI is formed. Then in the subsequent process, the size of the pit is further enlarged after a few processes, so that when the gate structure of the LDMOS is formed later, the gate structure is easy to form downward bulges at the pit, the LDMOS is caused to have dielectric breakdown related to time, and the problem of lower reliability of the LDMOS is caused.
Disclosure of Invention
In order to solve at least one technical problem, the present invention is directed to providing an STI-type LDMOS with a trench field plate and a method for manufacturing the same, so as to solve the problem of LDMOS reliability caused by a pit formed at the top edge of the STI.
The aim of the invention is realized by adopting the following technical modes:
in a first aspect, the present invention provides an STI-type LDMOS having a recessed field plate, comprising a polysilicon field plate;
the polysilicon field plate is provided with a groove;
the recess is located directly above the STI top side edge.
Preferably, the length of the polysilicon field plate is 1-15um.
Preferably, the width of the polysilicon field plate is 1-1000um.
Preferably, the height of the polysilicon field plate is 60-300nm.
Preferably, the length of the groove is 0.5-5um.
Preferably, the width of the groove is 0.5-1000um.
Preferably, the semiconductor device further comprises a P-drift layer, an N-body layer, an N+ layer, a source region, a drain region, a source, a drain, a gate and an STI;
the N-body layer is positioned below the polycrystalline silicon field plate and is adjacent to the polycrystalline silicon field plate;
the STI is located to the left of the drain region and is adjacent to the polysilicon field plate and the drain region.
Preferably, the cross-sectional shape of the STI includes a trapezoid and a semicircle.
In a second aspect, the present invention provides a method for manufacturing an STI type LDMOS having a trench field plate, including:
etching the upper layer of the P-drift layer to form a groove;
depositing silicon dioxide in the trench to form an STI;
depositing a polysilicon field plate;
etching the polysilicon field plate;
and forming an N-body layer, a P+ layer and an N+ layer on the P-drift layer by ion implantation.
Preferably, the etching the polysilicon field plate includes:
a groove is formed in the polycrystalline silicon field plate;
the recess is located directly above the STI top side edge.
Compared with the prior art, the invention has the beneficial effects that:
the invention reduces the hot carrier injection effect and time-dependent dielectric breakdown caused by the pit formed at the top side edge of the STI while maintaining the breakdown voltage of the LDMOS device by forming the groove at the position of the polysilicon field plate right above the top side edge of the STI.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
In order to more clearly describe the technical solutions in the embodiments or the background of the present application, the following description will describe the drawings that are required to be used in the embodiments or the background of the present application.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the technical aspects of the disclosure.
Fig. 1 is a schematic structural diagram of an STI-type LDMOS with a trench field plate according to an embodiment of the present invention;
FIG. 2 is a schematic top view of an STI LDMOS with a trench field plate according to an embodiment of the present invention;
FIG. 3 is a schematic flow chart of a method for manufacturing an STI type LDMOS with a trench field plate according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a method for manufacturing an STI-type LDMOS with a trench field plate according to an embodiment of the present invention.
Detailed Description
In order to make the present application solution better understood by those skilled in the art, the following description will clearly and completely describe the technical solution in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better illustration of the invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present invention.
HCI, hot carrier injection, is a phenomenon of degradation of electrical properties in semiconductor devices due to injection of high-energy electrons or holes, and is a major key problem affecting the reliability of MOSFET devices, and also affecting the lifetime of MOSFET devices. The hot carrier injection effect is that the probability of ionization collision is increased due to the position of the strong electric field of the MOSFET device, so that the hot carrier overcomes the tunneling of the interface potential of silicon and silicon dioxide into the oxide layer, and the oxide layer of the MOSFET device is damaged. Such damage can cause a change in the charge density of the oxide layer, which in turn affects the electrical performance of the MOSFET device, causing a drift or degradation in the electrical parameters of the MOSFET device.
TDDB, time dependent dielectric breakdown, refers to the application of a constant voltage to the gate electrode to bring the MOSFET device into an accumulated state, after a period of time, during which the oxide film breaks down, the lifetime of which is the time that elapses under that condition. As the chip size decreases, the supply voltage and the operating voltage of the chip are not reduced much, so the corresponding electric field strength increases, resulting in an increase in the movement rate of electrons. When the energy of the electrons is high enough, they leave the silicon substrate and tunnel into the oxide layer, thereby changing the threshold voltage. This effect can also affect other parameters, creating long-term reliability problems.
In the preparation process of the STI type LDMOS, a pit is easily formed at the top side edge of the STI when the STI is formed, and the size of the pit after a plurality of processes is further enlarged in the subsequent process, so that when the gate structure of the LDMOS is formed subsequently, the gate structure is easily formed to be downwards convex at the pit, and the LDMOS is caused to have dielectric breakdown related to time, so that the problem of lower reliability of the LDMOS is caused.
The invention reduces the hot carrier injection effect and time-dependent dielectric breakdown caused by the pit formed at the top side edge of the STI while maintaining the breakdown voltage of the LDMOS device by forming the groove at the position of the polysilicon field plate right above the top side edge of the STI.
Example 1
An STI-type LDMOS having a recessed field plate is provided, see fig. 1 and 2, comprising a polysilicon field plate;
the polysilicon field plate is provided with a groove;
the recess is located directly above the STI top side edge.
In modern semiconductor processes, one common method for preparing junctions is to use silicon dioxide or the like as a mask on the surface of the silicon, and then dope the impurities into the silicon at the window by liquid phase diffusion or low energy ion implantation. It is desirable that the window of the reticle be able to control the extent of doping precisely during the fabrication process, but in fact, due to the uncontrollable direction of movement of the impurity, it will also move laterally down the mask as it goes deeper in the longitudinal direction. Therefore, the PN junction formed in the actual process has a curved junction. Generally, curved junctions can be divided into two types, a cylindrical junction formed at the edge of a mask window and a spherical junction formed at the window corner, and these curved junctions have a high electric field. In order to increase the breakdown voltage of MOSFET devices, it is necessary to change the weak link of the high electric field into a planar junction. For PN junctions, the dominant force to withstand voltage is the space charge region, i.e., the depletion region. Since the edge formed by diffusion is curved, the corresponding depletion region is also curved. The voltage is applied to the PN junction edge, so that the PN junction edge is regulated and controlled, the curved surface radius of the depletion region at the PN junction edge is prolonged, and therefore the distribution of the electric field intensity is balanced to improve the breakdown voltage of the MOSFET device, and the field plate technology is adopted.
The field plate is an electric field optimization technology widely applied to a transverse power device, and the technology improves the voltage resistance of the LDMOS device by adding the field plate under the condition of not changing the on-resistance of the LDMOS device. When electric lines exist on the surface of the depletion region, the electric lines terminate on the surface charge of the LDMOS device and are influenced by the electric field on the surface of the LDMOS device, and the shape of the surface of the depletion region and the distribution of the electric field are changed, so that the breakdown voltage of the LDMOS device is changed. The field plate technology is used for covering a field plate on the surface of the LDMOS device, and changing the breakdown voltage of the LDMOS device by changing the voltage of the field plate.
The reliability of the gate oxide layer is an important issue in the early stages of the integrated circuit industry, and the gate dielectric layer is thinned as the size of the MOSFET device is reduced. In the past few years, oxide film thickness has approached a few nanometers, so any defects, impurities, or interface states in the oxide film have a significant impact on the gate oxide layer. In addition, the failure process of the gate oxide layer is an accumulation process, and defects in the oxide film easily capture electrons, so that a passage is formed when the electrons accumulate to a certain degree along with the time, the oxide film breaks down, and the MOSFET device fails.
HCI causes degradation of MOSFET device performance over time to be an important reliability problem. The hot carriers, i.e. high energy carriers, are accelerated by the channel transverse electric field near the drain and collide with the lattice to generate electron-hole pairs. One part of electrons with lower energy flow out through the drain electrode, and the other part of electrons with higher energy cross the interface barrier between silicon and silicon dioxide and enter the silicon dioxide dielectric layer, so that a small gate current is formed; and holes are led out from the substrate electrode to form a substrate current. The magnitude of the substrate current is a sign of the magnitude of the HCI effect. Lattice collisions of the channel hot carriers with the silicon and silicon dioxide interface create interface states, while electrons injected into the silicon dioxide dielectric layer become trapped therein forming trapped charges. The trapped charges and interface states affect channel carrier mobility and effective channel potential, causing drift in threshold voltage, drive current and transconductance, and degradation in MOSFET device performance.
During the formation of the STI, undesirable pits, i.e., divots, may form on the top edge of the STI. The pit problem is directly related to electric leakage of the edge of the STI, the pit can cause parasitic edge transistors and the electric field is concentrated at the edge of the STI, so that a larger electric field exists at the edge of the top side of the STI, and further, the leakage current of the edge of the grid electrode is generated and increased, and a hot carrier injection effect occurs in the LDMOS device; in forming the gate structure of the LDMOS, the gate structure tends to form a downward bump at the pit and cause the LDMOS to exhibit a time-dependent dielectric breakdown. These phenomena eventually cause problems in gate control, which affects the reliability of the LDMOS device.
In this embodiment, the polysilicon field plate is provided with a groove just above the top side edge of the STI, so that the breakdown voltage of the LDMOS device is maintained, and the hot carrier injection effect and the time-dependent dielectric breakdown caused by the pit formed at the top side edge of the STI are reduced, thereby improving the reliability problem of the LDMOS device.
Preferably, the polysilicon field plate has a length of 1-15um.
Preferably, the width of the polysilicon field plate is 1-1000nm.
Preferably, the height of the polysilicon field plate is 60-300nm.
There are three electric field peaks at the interface of the LDMOS. The first peak exists at the P-N junction formed by the channel and the drift region, and the second peak exists at the pit formed by the top side edge of the STI; the third peak exists directly below the field plate edge of the drift region. The electric field intensity at the second peak position of the LDMOS is high, hot carriers are easy to generate, and the impact of pits is added, so that the carriers bombard a gate oxide layer, the leakage current of a gate is increased, and the stability and the reliability of the LDMOS device are affected. The hot carrier injection effect is generated in part because of the hot carrier injection near the source end, so that the hot carrier injection effect is reduced, the reliability of the LDMOS device is improved, two electric field peaks between the source electrode and the STI need to be reduced, and the field plates are arranged at corresponding positions. In this embodiment, the length of the polysilicon field plate is set to 1-15um, the width of the polysilicon field plate is set to 1-1000um, and the height of the polysilicon field plate is set to 60-300nm. As a preferred embodiment, the length of the polysilicon field plate is set to be 5um, the height of the polysilicon field plate is set to be 200nm, and the width of the polysilicon field plate is matched with the size of the LDMOS device, which has the advantages that the polysilicon field plate has the best effect of balancing the local electric field intensity, and the breakdown voltage which the LDMOS device can bear is large.
Preferably, the length of the grooves is 0.5-5um.
Preferably, the width of the grooves is 0.5-1000um.
In this embodiment, the length of the groove is set to 0.5-5um, and the width of the groove is set to 0.5-1000um. It should be noted that the width of the groove is set according to the widths of the polysilicon field plate and the active region, and the width of the groove is larger than the width of the active region and smaller than the width of the polysilicon field plate. The grooves are formed from the top of the polysilicon field plate to the bottom of the polysilicon field plate, namely, the heights of the grooves are set according to the heights of the polysilicon field plate, namely, the heights of the grooves. As a preferred embodiment, the width of the polysilicon field plate is set to 10um, the length of the groove is set to 1um, and the width of the groove is set to 8um, which has the advantages of reducing the gate oxide TDDB caused by HCI at the STI pit and maintaining the breakdown voltage of the polysilicon field plate. In some embodiments, the shape of the groove may also be an oval racetrack shape with a circular arc on the top surface and a circular arc on the bottom surface.
Preferably, further comprising a P-drift layer (P-drift region), an N-body layer (N-body region), an n+ layer, a source region, a drain region, a source, a drain, a gate and STI;
the N-body layer is positioned below the polycrystalline silicon field plate and is adjacent to the polycrystalline silicon field plate;
the STI is located to the left of the drain region and adjoins the polysilicon field plate and the drain region.
In this embodiment, the LDMOS is of the P-type, including a P-drift layer, an N-body layer, an n+ layer, a source region, a drain region, a source, a drain, a gate, and an STI; the N-body layer is positioned below the polycrystalline silicon field plate and is adjacent to the polycrystalline silicon field plate; the STI is located to the left of the drain region and adjoins the polysilicon field plate and the drain region. The source region is in contact with the source, the drain region is in contact with the drain, and the gate is in contact with the polysilicon field plate. The P-type LDMOS is particularly serious for the gate oxide TDDB caused by HCI due to its physical characteristics, a recess is formed in the polysilicon field plate just above the top side edge of the STI, and the effect of reducing the hot carrier injection effect and the time-dependent dielectric breakdown caused by the pit formed at the top side edge of the STI while maintaining the breakdown voltage of the LDMOS device is more pronounced and effective in the P-type LDMOS. It should be noted that the embodiment only illustrates the structure of the P-type LDMOS, and the technical scheme is not limited to be applied to the P-type LDMOS, and the technical scheme can be applied to the N-type LDMOS as well and achieve good effects.
Preferably, the cross-sectional shape of the STI includes a trapezoid and a semicircle.
In LDMOS devices, the high electric field region is typically located at the region edge or tip region. In this embodiment, the cross-section of the STI may be trapezoidal in shape, and the curvature of the surface increases at one end of the sidewall surface of the trapezoid, which causes a strong electric field to exist on the sidewall surface of the trapezoid, where hot carrier injection damage is more likely to occur. Thus, the polysilicon field plate is notched at the top edge of the STI, reducing hot carrier injection effects and time dependent dielectric breakdown. The cross section of the STI can be semicircular, so that the strong electric field of the LDMOS device is improved, the generation of sharp-angle strong electric field is avoided, the hot carrier injection effect at the bottom of the edge of the polycrystalline silicon field plate can be reduced by the semicircular bottom, and the reliability of the LDMOS device is improved.
Example 2
The method for preparing the STI type LDMOS with the groove field plate is provided, referring to fig. 3 and 4, and comprises the following steps:
s100, etching the upper layer of the P-drift layer to form a groove;
the STI technology etches silicon in the doped region to form a shallow trench, and then the trench is filled with insulating material to achieve isolation. Compared with the traditional intrinsic oxidation isolation technology, the insulating layer can be deeper, leakage current between electrodes can be reduced, and larger breakdown voltage is born.
S200, depositing silicon dioxide in the groove to form STI;
the STI process overcomes the limitations of the LOCOS process, and its superior performance is achieved by integrating a complex series of processes, mainly including etching, filling and chemical mechanical polishing planarization of trenches. In the formation of trenches, the STI process typically employs Si 3 N 4 As an isolation mask to prevent Si 3 N 4 Is used as a buffer layer to release Si 3 N 4 And stress between the silicon substrates. Si (Si) 3 N 4 As a polish stop during a subsequent chemical mechanical polish planarization process. Its thickness determines the step height of the active region and field region and its optimization should be chosen to ensure that the step height after cmp planarization is sufficient to allow cleaning and etching prior to gate oxide growth. In some embodiments, at 1000 ℃, O 2 And growing 20nm silicon dioxide as buffer layer under HCl atmosphere, then using LPCVD process deposition of 200nm Si 3 N 4 Thereafter at 800 ℃, N 2 Is annealed for 30min in the atmosphere. In Si 3 N 4 And (4) photoetching by taking the photoresist as an etching mask after annealing. The trench is formed by reactive ion etching the silicon substrate. Factors that affect etching are mainly temperature, pressure, RF power, etching gas, and components thereof. The most critical of the etching process is controlling the shape of the trench, which affects the trench filling.
The main step in the filling of the trench is to deposit silicon dioxide, which is typically higher in etch rate than the grown silicon dioxide, which can lead to loss of field silicon dioxide during the surface cleaning process prior to gate silicon dioxide formation. The etch rate of the deposited silicon dioxide may be reduced by a densification process, such as annealing at 800-1050 c, to reduce the etch rate of the fill medium to a level close to that of thermally grown silicon dioxide. In some embodiments, the process of plasma enhanced chemical vapor deposition is employed with tetraethoxysilane as a precursor and silicon dioxide as the trench filling medium, and the LPCVD process is used to deposit 15nm silicon dioxide and 15nm Si prior to filling the trench with silicon dioxide 3 N 4 To protect the corners of the trench from damage during chemical mechanical polishing planarization, and after filling the trench, at 900 ℃ and N 2 To reduce the corrosion rate of the silicon dioxide.
CMP planarization is considered to be the most central part of the STI process, which utilizes a combination of chemistry and machinery to planarize the surface of the silicon wafer. The difficulty with the CMP process is that its planarization effect is related to the pattern size of the wafer surface. After CMP, si is exposed on the wide active region 3 N 4 Thereafter, overpolishing tends to occur in the wide isolation region and the narrow active region, resulting in a dishing phenomenon, which causes Si 3 N 4 The non-uniformity of the step height between the active region and the field region after removal may even damage the silicon substrate at the narrow active region. In some embodiments, after CMP, the exposed Si is removed using hot phosphoric acid 3 N 4 Finally, a layer of sacrificial oxide layer is grown on the surface of the silicon wafer and is rinsed off, so as to further processAnd removing defects and damages on the surface of the silicon wafer, and preparing for gate oxidation and formation of a polysilicon gate.
S300, depositing a polysilicon field plate;
deposition processes are classified into Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD). CVD refers to a process of chemically depositing a coating on the surface of a wafer, typically by applying energy to a gas mixture. Assuming that the substance (a) is deposited on the wafer surface, two gases (B and C) that can generate the substance (a) are first input to the deposition apparatus, and then energy is applied to the gases to cause the gases B and C to chemically react.
PVD (physical vapor deposition) coating techniques are mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like. The corresponding vacuum coating equipment comprises a vacuum evaporation coating machine, a vacuum sputtering coating machine and a vacuum ion coating machine.
In some embodiments, the goals of increasing the breakdown voltage of the LDMOS device and reducing the on-resistance of the LDMOS device can be achieved by introducing two centrally symmetric vertical field plates in the oxide trench. Two vertical field plates in the LDMOS device are connected one to the gate and one to the drain. In the off state, the vertical field plate introduces a high electric field into the oxidation trench, two new electric field peaks are formed near the surface of the trench, and the whole electric field of the device is optimized. The auxiliary depletion effect caused by the gate field plate helps the drift region to reach a higher doping concentration. In the on state, the concentration of the doped region is higher, so that the specific on resistance of the device is smaller, the contradiction relation between the breakdown voltage and the specific on resistance of the LDMOS device is relieved to a certain extent, and the performance of the device is improved. Besides being connected with the electrode through being embedded in the groove, the field plate technology can be directly used on the electrode to optimize and adjust the surface electric field of the LDMOS device, and the performance of the LDMOS device is improved. The field plate technology is connected with different electrodes to form different field plates, such as a source field plate, a gate field plate and a drain field plate.
S400, etching the polysilicon field plate;
etching is a process of selectively removing unwanted material from the surface of a silicon wafer by chemical or physical means, and is a generic term for stripping and removing material by solution, reactive ions or other mechanical means. The etching technology is mainly divided into dry etching and wet etching. The dry etching mainly uses the reaction gas and the plasma for etching; the wet etching mainly uses chemical reagents to chemically react with the etched material for etching.
Ion beam etching is a physical dry etching process. Thereby, argon ions are irradiated onto the surface with an ion beam of about 1 to 3 keV. Due to the energy of the ions, they strike the material of the surface. The wafer is vertically or obliquely directed into the ion beam and the etching process is absolutely anisotropic. The selectivity is low because it is not different for each layer. The gas and abraded material are evacuated by the vacuum pump, but since the reaction products are not gaseous, particles can deposit on the wafer or chamber walls. All materials can be etched in this way and the wear on the vertical walls is low due to the vertical radiation.
Plasma etching is an absolute chemical etching process and has the advantage that the wafer surface is not damaged by accelerated ions. The method is used to remove the entire film (e.g., backside cleaning after thermal oxidation) because the etch profile is isotropic due to the movable particles of the etch gas. One type of reactor used for plasma etching is a downstream reactor. So that the plasma is ignited at a high frequency of 2.45GHz by impact ionization, the location of which is separated from the wafer.
The etch rate depends on the pressure, the power of the high frequency generator, the process gas, the actual gas flow and the wafer temperature. Anisotropy increases with an increase in high-frequency power, a decrease in pressure, and a decrease in temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes and the material of the electrodes. If the distance is too small, the plasma cannot be unevenly dispersed, resulting in non-uniformity. If the distance of the electrodes is increased, the etch rate is reduced because the plasma is distributed in the enlarged volume. Carbon has proven to be the material of choice for electrodes. Since fluorine and chlorine also attack carbon, the electrodes produce a uniformly strained plasma and the wafer edge is affected by the same effect as the wafer center. The selectivity and etch rate are largely dependent on the process gas. For silicon and silicon compounds, fluorine gas and chlorine gas are mainly used.
S500, forming an N-body layer, a P+ layer and an N+ layer on the P-drift layer by ion implantation.
The substrate of the PN junction is divided into P type and N type, and +is heavily doped (high doping concentration), is lightly doped (low doping concentration), and P type doped with IIIA group elements, such as: boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl). N-type doping with group VA elements such As nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi) and permangana (Mc). In this embodiment, the p+ layer and the n+ layer are highly doped, the P-body layer is lightly doped, and the method for preparing the doping includes a thermal diffusion technique and an ion implantation technique; the impurities incorporated are of two types, acceptor impurities or donor magazines providing carriers, respectively; and heavy metal impurities that create recombination centers. Thermal diffusion technology: for the incorporation of donor or acceptor impurities, a higher temperature thermal diffusion is required. Because the radius of donor or acceptor impurity atoms is generally relatively large, it is difficult to get them directly into the interstices of the semiconductor lattice; only after crystal lattice vacancies are present in the crystal is it possible for impurity atoms to enter to occupy these vacancies and thus enter the crystal. In order to create a large number of crystal lattice vacancies in the crystal, the crystal must be heated to intensify the thermal motion of the crystal atoms so that some of the atoms acquire a sufficiently high energy to leave the lattice sites, leaving vacancies (while also creating an equal amount of interstitial atoms, collectively referred to as thermal defects), and therefore the diffusion coefficient of the atoms increases exponentially with increasing temperature. For silicon crystals, a temperature of around 1000 degrees celsius is required, i.e. the temperature at which heat diffuses, in order to form a large number of vacancies therein. Ion implantation technology: in order to enable the donor or acceptor impurity atoms to enter the crystal, the impurity atoms are ionized into ions, the ions are accelerated by a strong electric field, high kinetic energy is obtained, and then the ions are directly bombarded into the crystal and injected into the crystal. Of course, when doping is performed by ion implantation, many lattice defects must be generated, and some atoms are located in the gaps. Therefore, the semiconductor must also be subjected to a so-called annealing process after ion implantation to eliminate these defects and activate the impurities.
Lightly doped semiconductors refer to semiconductor materials that are made by adding a low concentration of impurity atoms in the preparation of the semiconductor material. The doped impurity atoms can alter the electrical properties of the semiconductor material, thereby improving its performance and functionality. In lightly doped semiconductors, the concentration of impurity atoms incorporated is typically lower than the intrinsic concentration of the semiconductor material (intrinsic concentration refers to the concentration of impurity atoms in a pure semiconductor). The impurity atoms to be incorporated must also have a lattice size and an electronic structure similar to those of the semiconductor material atoms to ensure that they can be smoothly bonded to and move in the semiconductor material. After doping impurity atoms, the electrical properties of the lightly doped semiconductor will change accordingly. The most important of these is the improvement in conductivity. This is because the added impurity atoms may form additional free electrons or holes in the semiconductor, resulting in enhanced conductivity properties of the semiconductor material. In addition, the lightly doped semiconductor can also change the properties of the semiconductor material such as forbidden bandwidth, carrier mobility, optical absorption spectrum and the like, so that the application of the lightly doped semiconductor in the fields of electronics, optoelectronics, chemistry and the like is expanded. The lightly doped semiconductor is prepared by ion implantation, fusion diffusion and other technologies. The ion implantation is to accelerate the doping element to a high speed by a high voltage electric field, then bombard the semiconductor surface, and implant it into the semiconductor lattice. The fusion diffusion is to place the semiconductor chip on the doped material block, then heat to high temperature, and the doped atoms are fused and diffused into the semiconductor material. In practical application, lightly doped semiconductors are widely applied to the fields of circuits, solar cells, nano materials and the like. For example, after silicon is doped with aluminum element, N-type silicon can be formed, the conductivity of the N-type silicon is obviously improved, and the N-type silicon can be used for manufacturing a P-N junction solar cell. In addition, lightly doped semiconductors can also produce Metal Oxide Semiconductor Field Effect Transistors (MOSFETs),Low noise power amplifiers and the like. In the field of nanotechnology, the lightly doped semiconductor can be used for preparing various photoelectron and biochemical sensors, and has wide application prospect. The doping concentration of the heavy doping is 10 19 cm -3 The above methods of preparing the heavily doped semiconductor include a diffusion method and an ion implantation method. The diffusion method mixes impurity ions with a semiconductor material, and then heats the mixture to a high temperature to diffuse the impurity ions into the semiconductor material, and the ion implantation accelerates the impurity ions to a high speed and then injects the impurity ions into the semiconductor material, so that the heavily doped semiconductor can be used to manufacture high-performance electronic devices.
Preferably, etching the polysilicon field plate comprises:
a groove is formed in the polycrystalline silicon field plate;
the recess is located directly above the STI top side edge.
In this embodiment, by providing a recess at the top side edge of the polysilicon field plate directly above the STI, the hot carrier injection effect and time-dependent dielectric breakdown caused by the pit formed at the top side edge of the STI are reduced while maintaining the breakdown voltage of the LDMOS device, improving the reliability problem of the LDMOS device.
In some embodiments, functions or modules included in an apparatus provided by the embodiments of the present disclosure may be used to perform a method described in the foregoing method embodiments, and specific implementations thereof may refer to descriptions of the foregoing method embodiments, which are not repeated herein for brevity. In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
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