CN117478548B - Fault tolerance capability test system and method for I2C slave equipment - Google Patents

Abstract

The invention provides a system and method for testing the fault tolerance of I2C slave equipment, which belongs to the field of I2C bus communication technology and fills the gap in the existing technology for testing the fault tolerance of the slave; including I2C bus, slave equipment, unstable waveform circuit flat simulation module and waveform slope change simulation module; the slave device is connected to the unstable waveform level simulation module through the I2C bus. The unstable waveform level simulation module is used to replace the host device in the I2C communication process and provide feedback to the slave device. Output unstable waveform level; the I2C bus is connected to the external power supply through the waveform slope change simulation module. The waveform slope change simulation module is used to change the level signal slope in the I2C bus; the slave device detects unstable waveform levels and signal edges. It responds to the slope change, and its fault tolerance can be evaluated based on the response results; the invention can uniformly and efficiently test the fault tolerance of the slave equipment and ensure the application quality of the slave equipment.

Description

A fault-tolerance testing system and method for I2C slave devices

Technical field

The invention belongs to the technical field of I2C bus communication and is used in the testing process of slave equipment. Specifically, it is a fault-tolerance testing system and method for I2C slave equipment.

Background technique

The integrated circuit bus (Inter-Integrated Circuit, IIC) is a simple, reliable, half-duplex and synchronous serial control bus, often called the I2C bus. I2C testing is a testing method used to evaluate and verify the function and performance of I2C slave devices; it includes testing content such as sending and receiving data, detecting communication errors, and verifying timing and level requirements. Through I2C testing, it can be ensured that the slave device correctly identifies and processes the data sent by the host device under different signal environments, and ensures accurate data transmission and reliable communication.

In I2C bus technology, the clock line (Serial Clock, SCL) and the data line (Serial Data, SDA) are the two basic signal lines. The clock line SCL is used to synchronize the data transmission between the host device and the slave device. The host device controls the clock pulse on SCL to indicate the timing of data transmission; the data line SDA is used to transmit data between the host device and the slave device. Data is represented by the level on SDA. By controlling the level on SDA, data can be sent and received between the host device and the slave device.

In the existing technology, when performing I2C communication, you may face the following problems:

1. The levels of the clock line SCL and data line SDA are unstable: This problem will cause the start signal or stop signal to be mistakenly triggered, causing the communication to fail to proceed normally or to exit, resulting in data transmission errors or communication in a deadlock state. .

2. Clock frequency mismatch: This problem will cause errors in the communication timing between the host device and the slave device. If the clock frequencies are different, the data cannot be transmitted correctly, and the communication process will fail.

In addition, in I2C communication, data transmission is performed between the rising edge and falling edge of the clock line SCL; during data transmission, SCL is high level, and the data represented by SDA is valid at this time; when SCL is low power Normally, SDA data is invalid. When the master device sends data, the slave device needs to read the data on the data line SDA when the clock line SCL generates a rising edge.

The length of the rising edge affects the correct timing for the slave device to read data. If the rising edge time is too short, the slave device may not be able to read the data on the data line in time, resulting in data transmission errors or loss; if the rising edge time is too long, the slave device may read data at the wrong time. Cause data parsing errors.

In summary, in order to ensure the correct progress of the I2C communication process, the slave device needs to have a certain fault tolerance for the levels of the clock line SCL and data line SDA sent by the host device. Even if the clock line SCL level sent by the master device is unstable, the slave device should still correctly identify the rising and falling edges of the clock signal to ensure data synchronization. Even if the data line SDA level sent by the host device is unstable, the slave device should still correctly identify the signal status to ensure accurate reading and writing of data.

By identifying the state changes of the I2C bus data signal, the slave device should accurately determine whether the data sent by the host device is 0 or 1, and perform corresponding operations; otherwise, the signal may be accidentally triggered due to level instability in the early stage of communication. The communication process cannot be exited, and the I2C bus is always busy. There is currently a lack of systematic testing technology for the fault tolerance of slave equipment. Therefore, it is necessary to fill this gap in time, test the fault tolerance of slave equipment uniformly and efficiently, and ensure the actual application quality of slave equipment.

Contents of the invention

In view of the current situation in the background technology, the present invention introduces FPGA and DAC devices during the test process of I2C slave equipment to simulate the effect of unstable waveform level and waveform slope change, resulting in a scene in which the I2C communication level signal is unstable, thereby observing and Test the fault tolerance of the slave device to unstable levels of the clock line SCL and data line SDA. The invention can efficiently and comprehensively test the data transmission stability and I2C communication reliability of the slave device, and control the communication quality of the slave device.

The present invention adopts the following technical solutions to achieve the purpose:

A fault-tolerant test system for I2C slave equipment. The test system includes an I2C bus, a slave equipment, an unstable waveform level simulation module and a waveform slope change simulation module; the slave equipment communicates with all the I2C slave equipment through the I2C bus. The unstable waveform level simulation module is connected to the unstable waveform level simulation module, which is used to replace the host device in the conventional I2C communication process and output the unstable waveform level to the slave device; the I2C bus The waveform slope change simulation module is connected to an external power supply. The external power supply is used to provide power supply for the test system. The waveform slope change simulation module is used to change the slope of the level signal in the I2C bus.

Further, the unstable waveform level simulation module is composed of a first FPGA unit, a first DAC unit and a second DAC unit; the first FPGA unit is loaded with a preset unstable waveform level simulation program, and the The unstable waveform level simulation program is used to drive the first DAC unit and the second DAC unit, respectively generate unstable waveform levels corresponding to the clock line SCL and the data line SDA, and send them to In the slave device, the slave device is used to receive unstable waveform levels and respond; testers evaluate the fault tolerance of the slave device based on the response results.

Further, the waveform slope change simulation module includes a pull-up resistor, a digital potentiometer and a second FPGA unit; the second FPGA unit is loaded with a preset waveform slope change simulation program, and the resistance of the pull-up resistor is The digital potentiometer presents a variable resistance state; the waveform slope change simulation program is used to change the resistance of the pull-up resistor by controlling the digital potentiometer, thereby changing the value of the clock. The preset waveform level signal edge slope transmitted on the line SCL or the data line SDA; the slave device is used to receive the preset waveform level of different signal edge slopes and make a response; the tester based on the response result, Evaluate the fault tolerance of the slave device.

The present invention also provides a fault-tolerance testing method for I2C slave equipment. The hardware basis of the testing method is the aforementioned testing system. The testing method includes an unstable waveform level testing process and a waveform slope change testing process; based on The specifications of the slave device and the I2C communication protocol enable the slave device to receive unstable waveform levels and preset waveform levels with different signal edge slopes successively, and obtain the response result of the slave device and the actual received data content; and then based on the response Results and data content accuracy evaluate the fault tolerance of the slave device.

To sum up, due to the adoption of this technical solution, the beneficial effects of the present invention are as follows:

Based on the combination of FPGA and DAC devices, the present invention can simulate the unstable level sent by the host device and reproduce the level jitter or noise scenario that may exist in the real I2C communication process. This test solution can more realistically simulate the level changes of the host device, thereby evaluating the slave device's fault tolerance and recognition ability for unstable levels. Slave devices that have passed the unstable level test can better ensure the stability of their data transmission and the reliability of I2C communication, and have better benefits in practical applications.

Based on the combination of FPGA and digital potentiometer, the present invention can dynamically simulate the size of the pull-up resistor during the I2C bus communication process, thereby adjusting the rising and falling edge slopes of the clock line SCL and the data line SDA. This test solution can evaluate the slave device's ability to identify signal edges with different slopes, and then test the stability and reliability of the slave device in different signal environments; the adjustment of the slope can directly simulate different signal transmission environmental conditions and comprehensively test The adaptability of the slave machine to different signal environments.

Description of the drawings

Figure 1 is a schematic diagram of the structural connection frame of the test system of the present invention;

Figure 2 is a schematic diagram of the architecture of the unstable waveform level simulation module of the present invention;

Figure 3 is a schematic structural diagram of the waveform slope change simulation module of the present invention;

Figure 4 is a schematic diagram of the overall flow of the testing method of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, rather than all embodiments. The components of the embodiments of the invention generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations.

Therefore, the following detailed description of the embodiments of the invention provided in the appended drawings is not intended to limit the scope of the claimed invention, but rather to represent selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present invention.

Example 1

A fault-tolerance test system for I2C slave devices. Figure 1 shows the structural connection relationship of the system, including I2C bus, slave device, unstable waveform level simulation module and waveform slope change simulation module; the slave device passes The I2C bus is connected to the unstable waveform level simulation module. The unstable waveform level simulation module is used to replace the host device in the conventional I2C communication process and output unstable waveform levels to the slave devices; the I2C bus changes through the waveform slope The analog module is connected to an external power supply. The external power supply is used to provide power supply for the test system. The waveform slope change simulation module is used to change the slope of the level signal in the I2C bus.

In this embodiment, as shown in Figure 2, the unstable waveform level simulation module is composed of a first FPGA unit, a first DAC unit and a second DAC unit. The first FPGA unit is connected to the first DAC unit and the second DAC unit at the same time. ; The first DAC unit is connected to the clock line SCL, and the second DAC unit is connected to the data line SDA.

The first FPGA unit is loaded with a preset unstable waveform level simulation program. The unstable waveform level simulation program uses FPGA programming to make the unstable waveform level have customized waveform shape, frequency and amplitude parameters, thereby simulating Unstable clock and data line levels.

The unstable waveform level simulation program is used to drive the first DAC unit and the second DAC unit to generate unstable waveform levels corresponding to the clock line SCL and data line SDA respectively, and send them to the slave device; the slave device uses To receive unstable waveform levels and respond; based on the response results, testers observe the communication behavior of the slave device and determine whether its data information is read correctly, thereby evaluating the fault tolerance of the slave device.

Example 2

Based on Embodiment 1, this embodiment specifically introduces the relevant content of the waveform slope change simulation module. Please refer to Figure 1 and Figure 3.

As shown in Figure 3, there are two waveform slope change simulation modules, which are respectively connected to the clock line SCL and data line SDA of the I2C bus; each waveform slope change simulation module includes a pull-up resistor, a digital potentiometer and a second FPGA unit. Among them, the combination of digital potentiometer and pull-up resistor can be implemented by using an external programmable resistor.

The clock line SCL or the data line SDA is connected to the external power supply through a pull-up resistor, and the pull-up resistor is connected to the second FPGA unit through a digital potentiometer.

The second FPGA unit is loaded with a preset waveform slope change simulation program. The waveform slope change simulation program changes the duration and length of the rising edge and/or falling edge of the level waveform through FPGA programming. Here, it is tested whether the slave device can correctly identify the rising edge and falling edge of the corresponding level to ensure the accurate transmission of data and the reliability of I2C communication.

The resistance of the pull-up resistor becomes a variable resistance state under the action of the digital potentiometer; the waveform slope change simulation program is used to change the resistance of the pull-up resistor by controlling the digital potentiometer, thereby changing the value of the clock line SCL or The preset waveform level signal edge slope transmitted on the data line SDA; the slave device is used to receive the preset waveform level with different signal edge slopes and respond; the tester determines the actual condition of the slave device based on the response results. During use, whether it can maintain synchronization with the host device, correctly parse data, and meet protocol timing requirements can evaluate the fault tolerance of the slave device.

Example 3

On the basis of Embodiment 1 or 2, this embodiment provides a method for testing the fault tolerance of an I2C slave device. The hardware basis of the test method is the test system in Embodiment 1 or 2. The test method includes unstable waveform circuits. The flat test process and the waveform slope change test process; according to the specifications of the slave device and the I2C communication protocol, the slave device successively receives unstable waveform levels and preset waveform levels with different signal edge slopes, and obtains the response results of the slave device. and the actual received data content; and then evaluate the fault tolerance of the slave device based on the response results and the accuracy of the data content.

In this embodiment, the overall flow of the unstable waveform level testing process can be seen in Figure 4, which specifically includes the following steps:

S11. Hardware connection: Connect the first FPGA unit to the clock line SCL and data line SDA of the I2C bus through the first DAC unit and the second DAC unit respectively;

S12. FPGA programming: Use FPGA development tools (such as Vivado tools) to write an unstable waveform level simulation program to control the output of the first DAC unit and/or the second DAC unit to generate unstable waveform levels; in the program, you can pass To implement the simulation process of calling counters, state machines or other logic circuits, those skilled in the art can set it according to actual needs;

S13. Configure the slave device: Connect the slave device to the I2C bus, and configure related configuration parameters such as the address and clock frequency of the slave device according to the specifications of the slave device;

S14. Test data transmission: Send the generated unstable waveform level to the slave device through the clock line SCL and/or data line SDA; different data modes and data values can be sent according to the specific test item category to simulate actual communication. different situations that may arise;

S15. Slave device response monitoring: Use monitoring tools to monitor the response of the slave device to unstable waveform levels and present the data content received by the slave device; the monitoring tool can use an oscilloscope, logic analyzer or other tools to observe I2C Level changes on the bus and data received by the slave device;

S16. Evaluate fault tolerance: Based on the response of the slave device and the accuracy of the data content, determine whether the slave device correctly recognizes the unstable waveform level, and obtain the fault tolerance evaluation result of the slave device.

Example 4

On the basis of Embodiments 2 and 3, this embodiment introduces the waveform slope change test process. The overall process is also as shown in Figure 4, and specifically includes the following steps:

S21. Hardware connection: Connect the second FPGA unit in each waveform slope change simulation module to the corresponding pull-up resistor through a digital potentiometer, and set the clock line SCL and data line SDA respectively;

S22. FPGA programming: Use FPGA development tools to write a waveform slope change simulation program and control the digital potentiometer to change the slope of the preset waveform level signal transmitted on the clock line SCL and/or data line SDA;

S23. Configure the slave device: Connect the slave device to the I2C bus, and configure the address and clock frequency of the slave device according to the specifications of the slave device;

S24. Test data transmission: Fix the unstable waveform level generated by the unstable waveform level simulation program to the preset waveform level. Through the waveform slope change simulation program, the preset waveform level with changed signal edge slope is passed through the clock. Line SCL and/or data line SDA is sent to the slave device;

S25. Slave device response monitoring: Use monitoring tools to monitor the response of the slave device to the preset waveform levels of different signal edge slopes, and present the data content received by the slave device; the monitoring tool can use an oscilloscope, logic analyzer or Other tools to observe the level changes on the I2C bus and the data received by the slave device;

S26. Evaluate fault tolerance: Based on the response of the slave device and the accuracy of the data content, determine whether the slave device correctly recognizes the preset waveform levels of different signal edge slopes, and obtain the fault tolerance evaluation result of the slave device.

Example 5

This embodiment introduces a specific test scenario based on the unstable waveform level test process of Embodiment 3. The scenario steps are as follows:

Step1: Select the Xilinx Spartan-6 FPGA development board; the slave device is an EEPROM chip; the DAC chip is AD5621; the clock frequency is set to 100kHz; the slave device address is 0x50; the FPGA clock frequency is 50MHz;

Step2: Connect the FPGA development board and DAC chip combination, and then connect it to the clock line SCL and data line SDA of the slave device to simulate the host device sending unstable levels;

Step3: Use Xilinx ISE software to write VHDL code to control the output voltage of the DAC chip; as needed, simulate the host device to send unstable levels by modifying the input data of the DAC chip;

Step4: The FPGA development board controls the DAC chip to output unstable levels, such as generating noise, interference, etc.; the FPGA development board sends data information to the slave device, such as writing a set of data to the EEPROM chip;

Step5: Monitor the level changes on the I2C bus and the response of the slave device. You can use tools such as an oscilloscope or a logic analyzer; check whether the slave device can accurately identify the data information sent by the host device and compare it with the expected results;

Step6: Result evaluation: Based on the response of the slave device, judge its ability to identify unstable levels; if the slave device can accurately identify the data information sent by the host device, even when the level is unstable, it means that the slave device The machine equipment has good data transmission and communication reliability.

Example 6

This embodiment introduces a specific test scenario based on the waveform slope change test process of Embodiment 4. The scenario steps are as follows:

Step1: Select the Xilinx Spartan-6 FPGA development board; the slave device is a temperature sensor; the initial setting of the pull-up resistor is 10 kiloohms; the clock frequency is 100kHz; the slave device address is 0x48; the FPGA clock frequency is 50MHz;

Step2: Connect the FPGA development board, digital potentiometer and pull-up resistor. Add pull-up resistors on the clock line SCL and data line SDA, initially set to 10 kiloohms; write Verilog code to control I2C host communication; modify the code parameters as needed to control the size of the pull-up resistor;

Step3: Change the size of the pull-up resistor, for example, change it to 20 kΩ or 5 kΩ, and record the value of each change; monitor the level changes on the I2C bus and the response of the slave device, you can use an oscilloscope or logic Tools such as analyzers; check whether the slave device can correctly identify the data information sent by the host device and compare it with the expected results;

Step4: Based on the response of the slave device, determine its ability to recognize changes in the rising and falling edge times; if the slave device can accurately identify the data information sent by the host device, even if the rising edge and falling edge times change, In this case, it shows that the slave device has better data transmission and communication reliability.

Claims (6)

1. A fault-tolerant test system for I2C slave devices, characterized in that: the test system includes an I2C bus, a slave device, an unstable waveform level simulation module and a waveform slope change simulation module; the slave device passes The I2C bus is connected to the unstable waveform level simulation module. The unstable waveform level simulation module is used to replace the host device in the conventional I2C communication process and output unstable waveform voltage to the slave device. flat; the I2C bus is connected to an external power supply through the waveform slope change simulation module, the external power supply is used to provide power supply for the test system, and the waveform slope change simulation module is used to change the I2C bus The level signal slope; There are two waveform slope change simulation modules, which are respectively connected to the clock line SCL and data line SDA of the I2C bus; each of the waveform slope change simulation modules includes a pull-up resistor, a digital potentiometer and a second FPGA Unit; wherein, the clock line SCL or the data line SDA is connected to the external power supply through the pull-up resistor, and the pull-up resistor is connected to the second FPGA unit through the digital potentiometer. ; The second FPGA unit is loaded with a preset waveform slope change simulation program, and the resistance of the pull-up resistor becomes a variable resistance state under the action of the digital potentiometer; the waveform slope change simulation program is By controlling the digital potentiometer, the resistance of the pull-up resistor is changed, thereby changing the edge slope of the preset waveform level signal transmitted on the clock line SCL or the data line SDA; the slave The device is used to receive preset waveform levels with different signal edge slopes and respond; the tester evaluates the fault tolerance of the slave device based on the response results; The waveform slope change simulation program changes the duration and length of the rising edge and falling edge of the level waveform through FPGA programming. 2. A fault-tolerant testing system for I2C slave devices according to claim 1, characterized in that: the unstable waveform level simulation module is composed of a first FPGA unit, a first DAC unit and a second DAC unit. , the first FPGA unit is connected to the first DAC unit and the second DAC unit at the same time; the first DAC unit is connected to the clock line SCL, and the second DAC unit is connected to the data line SDA. 3. A fault-tolerant testing system for an I2C slave device according to claim 2, characterized in that: the first FPGA unit is loaded with a preset unstable waveform level simulation program, and the unstable waveform level simulation program The flat simulation program is used to drive the first DAC unit and the second DAC unit, respectively generate unstable waveform levels corresponding to the clock line SCL and the data line SDA, and send them to the slave device In; the slave device is used to receive unstable waveform levels and respond; testers evaluate the fault tolerance of the slave device based on the response results. 4. A fault-tolerant testing system for I2C slave equipment according to claim 3, characterized in that: the unstable waveform level simulation program makes the unstable waveform level have a customized value through FPGA programming. Waveform shape, frequency and amplitude parameters. 5. A fault-tolerant testing method for I2C slave equipment, characterized in that: the hardware basis of the testing method is the testing system as described in any one of claims 1 to 4, and the testing method includes unstable waveform electrical The flat test process and the waveform slope change test process; according to the specifications of the slave device and the I2C communication protocol, the slave device successively receives unstable waveform levels and preset waveform levels with different signal edge slopes, and obtains the response results of the slave device. and the actual received data content; then evaluate the fault tolerance of the slave device based on the response results and the accuracy of the data content; The waveform slope change testing process specifically includes the following steps: S21. Hardware connection: Connect the second FPGA unit in each waveform slope change simulation module to the corresponding pull-up resistor through a digital potentiometer, and set the clock line SCL and data line SDA respectively; S22. FPGA programming: Use FPGA development tools to write a waveform slope change simulation program and control the digital potentiometer to change the slope of the preset waveform level signal transmitted on the clock line SCL and/or data line SDA; S23. Configure the slave device: Connect the slave device to the I2C bus, and configure the address and clock frequency of the slave device according to the specifications of the slave device; S24. Test data transmission: Fix the unstable waveform level generated by the unstable waveform level simulation program to the preset waveform level. Through the waveform slope change simulation program, the preset waveform level with changed signal edge slope is passed through the clock. Line SCL and/or data line SDA is sent to the slave device; S25. Slave device response monitoring: Use monitoring tools to monitor the response of the slave device to the preset waveform levels of different signal edge slopes, and present the data content received by the slave device; S26. Evaluate fault tolerance: Based on the response of the slave device and the accuracy of the data content, determine whether the slave device correctly recognizes the preset waveform levels of different signal edge slopes, and obtain the fault tolerance evaluation result of the slave device. 6. A fault-tolerance testing method for an I2C slave device according to claim 5, characterized in that: the unstable waveform level testing process specifically includes the following steps: S11. Hardware connection: Connect the first FPGA unit to the clock line SCL and data line SDA of the I2C bus through the first DAC unit and the second DAC unit respectively; S12. FPGA programming: Use FPGA development tools to write an unstable waveform level simulation program to control the output end of the first DAC unit and/or the second DAC unit to generate unstable waveform levels; S13. Configure the slave device: Connect the slave device to the I2C bus, and configure the address and clock frequency of the slave device according to the specifications of the slave device; S14. Test data transmission: Send the generated unstable waveform level to the slave device through the clock line SCL and/or the data line SDA; S15. Slave device response monitoring: Use monitoring tools to monitor the response of the slave device to unstable waveform levels and present the data content received by the slave device; S16. Evaluate fault tolerance: Based on the response of the slave device and the accuracy of the data content, determine whether the slave device correctly recognizes the unstable waveform level, and obtain the fault tolerance evaluation result of the slave device.