CN117476763A - E-HEMT with low leakage current and preparation method - Google Patents

Abstract

The invention provides an E-HEMT with low electric leakage and a preparation method thereof, wherein the E-HEMT comprises the following components: a heterojunction substrate; the heterojunction substrate comprises a base and a silicon-based N+ buffer layer; the substrate is positioned below the silicon-based N+ buffer layer and is adjacent to the silicon-based N+ buffer layer; the silicon-based N+ buffer layer is positioned between the GaN buffer layer and the substrate and is adjacent to the GaN buffer layer. The invention replaces the traditional silicon substrate with the material with higher forbidden bandwidth and better heat conduction performance, such as silicon carbide material, because the silicon carbide has the characteristics of wide band gap, high breakdown field intensity, high heat conductivity, high saturated electron migration rate and the like, and is suitable for high-temperature, high-power and extreme environments.

Description

An E-HEMT with low leakage and preparation method

Technical field

The invention relates to the field of semiconductor technology, and in particular to an E-HEMT with low leakage and a preparation method.

Background technique

GaN material has unique advantages in preparing high-voltage, high-temperature, high-power and high-density integrated electronic devices due to its large bandgap, high critical breakdown electric field, and high thermal conductivity. GaN materials can form heterojunction structures with materials such as AlGaN. Due to the spontaneous polarization and piezoelectric polarization effects of barrier layer materials such as AlGaN, a high concentration and high mobility two-dimensional electron gas (2DEG) will be formed at the heterojunction interface. This characteristic can not only improve the carrier mobility and operating frequency of GaN-based devices, but also reduce the on-resistance and switching delay of the device. GaN-based HEMT devices have broad application prospects in power electronics fields such as power management, wind power generation, solar cells, and electric vehicles due to their high breakdown characteristics, fast switching speed, and small on-resistance. Compared with traditional MOS devices, GaN-based HEMT devices have faster switching speeds and withstand higher reverse voltages. They can also improve efficiency, reduce losses, and save energy. They have huge market applications in the 600V-1200V device range. prospect.

For power devices, achieving enhanced mode and high-voltage operation is crucial. From the perspective of safety and energy consumption, it is necessary not to generate additional leakage in the event of a power outage. Therefore, the preparation of enhancement-mode devices with superior performance is a research direction of great research value. If the conventional E-HEMT (Enhanced Modle HEMT) device continues to pressurize the source and drain when it is turned off, a large area of GaN HEMT will leak. The leakage channel layer is mainly located in the GaN buffer layer. within, and will further cause leakage of current flowing from the GaN buffer layer to the substrate. This leakage will further cause heating inside the device, leading to GaN HEMT device failure and circuit damage. The choice of substrate material for semiconductor power devices has a direct impact. In order to improve the performance and reliability of power devices, silicon, quartz, sapphire, etc. are often used as substrate materials in the existing technology. However, traditional substrate materials can no longer meet the insulation requirements under high-voltage operating conditions of power devices, severely limiting GaN HEMTs. application fields.

Contents of the invention

The purpose of the present invention is to provide an E-HEMT with low leakage and a preparation method. The E-HEMT replaces the traditional silicon substrate with a material with a higher bandgap and better thermal conductivity, such as silicon carbide material, because The third generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field strength, high thermal conductivity, high saturation electron migration rate, stable physical and chemical properties, etc. It can be applied to high temperature, high frequency, high power and extreme environments. Compared with silicon material, silicon carbide has a larger bandgap width and higher critical breakdown field strength, and the present invention introduces an N-type heavily doped layer above the silicon carbide layer as a buffer layer, and the silicon base is N+ doped. The layer can form an electron trap, thereby further weakening the leakage phenomenon at the substrate end and reducing the overall thermal effect of the device.

An E-HEMT with low leakage, including: a heterojunction substrate;

The heterojunction substrate includes a base and a silicon-based N+ buffer layer;

The substrate is located below the silicon-based N+ buffer layer and adjacent to the silicon-based N+ buffer layer;

The silicon-based N+ buffer layer is located between the GaN buffer layer and the substrate and adjacent to the GaN buffer layer.

Preferably, the band gap of the filling material of the substrate is greater than the band gap of silicon.

Preferably, the filling material of the base includes: silicon carbide.

Preferably, the doping concentration of the N+ buffer layer is 10 ¹⁹ cm ^-3 .

Preferably, the thickness of the N+ buffer layer is 3um.

Preferably, the thickness of the substrate is 25um.

Preferably, the thermal conductivity of the filling material of the base is greater than or equal to the thermal conductivity of silicon carbide.

Preferably, it also includes: GaN buffer layer, AlGaN barrier layer, GaN layer, source electrode, drain electrode and gate electrode,

The GaN buffer layer is located above the heterojunction substrate;

The GaN layer is located above the GaN buffer layer;

The AlGaN barrier layer is located above the GaN layer;

The source electrode is located above the AlGaN barrier layer;

The gate electrode is located above the AlGaN barrier layer;

The drain electrode is located above the AlGaN barrier layer.

A method for preparing E-HEMT with low leakage, including:

Epitaxially extend an N-type heavily doped silicon layer over the substrate to form a silicon-based N+ buffer layer;

Epitaxially forming a GaN buffer layer, a GaN layer and an AlGaN barrier layer above the silicon-based N+ buffer layer;

Deposit gate, drain and source electrodes.

Preferably, the epitaxial layer of N-type heavily doped silicon layer above the substrate to form a silicon-based N+ buffer layer includes:

A silicon layer with a thickness of 3um is epitaxially grown on the substrate;

Ions are implanted into the silicon layer to form a silicon-based N+ buffer layer with a doping concentration of 10 ¹⁹ cm ^-3 .

This invention replaces the silicon substrate of the traditional E-HEMT with a material with a higher bandgap than the silicon substrate, because the material with a higher bandgap can form a higher potential barrier difference with the GaN buffer layer, making it difficult for electrons to pass through the potential barrier. The barrier reduces the current leakage from the GaN buffer layer to the substrate direction, and the replaced substrate material also has high heat dissipation performance, which can effectively dissipate the heat inside the E-HEMT and improve the heating situation inside the E-HEMT. To avoid E-HEMT failure caused by overheating inside the E-HEMT, the present invention also adds an N-type heavily doped N+ buffer layer under the GaN buffer layer. The silicon-based N+ doped layer can create an electron well, thereby further weakening the The leakage phenomenon at the substrate end reduces the overall thermal effect of the E-HEMT device.

Description of the drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those of ordinary skill in the art, It is said that other drawings can be obtained based on these drawings without exerting creative labor.

Figure 1 is a schematic structural diagram of the E-HEMT of the present invention;

Figure 2 is a schematic diagram of the E-HEMT preparation process method of the present invention;

Figure 3 is a schematic structural diagram of the E-HEMT preparation process of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiment of the present invention are only used to explain the relationship between components in a specific posture (as shown in the drawings). Relative positional relationship, movement conditions, etc., if the specific posture changes, the directional indication will also change accordingly.

In addition, descriptions involving "first", "second", etc. in the present invention are for descriptive purposes only and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In addition, the technical solutions in various embodiments can be combined with each other, but it must be based on the realization by those of ordinary skill in the art. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that such a combination of technical solutions does not exist. , nor within the protection scope required by the present invention.

For power devices, achieving enhanced mode and high-voltage operation is crucial. From the perspective of safety and energy consumption, it is necessary not to generate additional leakage in the event of a power outage. Therefore, the preparation of enhancement-mode devices with superior performance is a research direction of great research value. If the source and drain of the conventional E-HEMT (Enhanced Modle HEMT) device are turned off and the pressure is continuously applied, a large area of GaN HEMT will leak. The leakage channel layer is mainly located in the GaN buffer layer. within, and will further cause leakage of current flowing from the GaN buffer layer to the substrate. This leakage will further cause heating inside the device, leading to GaN HEMT device failure and circuit damage. The choice of substrate material for semiconductor power devices has a direct impact. In order to improve the performance and reliability of power devices, silicon, quartz, sapphire, etc. are often used as substrate materials in the existing technology. However, traditional substrate materials can no longer meet the insulation requirements under high-voltage operating conditions of power devices, severely limiting GaN HEMTs. application fields.

In the prior art, in order to prevent substrate leakage, methods usually include: strengthening the surface treatment of the substrate. Commonly used surface treatment methods include cleaning, oxidation, film deposition, etc. Cleaning can remove impurities and pollutants on the surface and improve the purity of the surface; oxidation can form an oxide film to enhance the insulation performance; thin film deposition can form an insulating layer on the surface to further improve the insulation capability. Through these surface treatment methods, leakage problems can be effectively prevented. Design a reasonable structure. The structural design of semiconductor devices is also an important part of preventing leakage. For example, in transistor design, reasonably setting the distance between the gate, source, and drain and using appropriate insulating materials to fill the gaps can effectively prevent current leakage. In addition, the insulation performance of the device can be improved by adding protective layers, isolation layers and other structures to further reduce leakage. Reinforce electrical insulation Electrical insulation is an important means to prevent leakage. In the manufacturing process of semiconductor devices, electrical insulation can be achieved by using materials such as insulating layers, insulating substrates, and insulating glue. These insulating materials have good electrical insulation properties and can effectively isolate current and prevent leakage problems. Strict quality control Quality control is the key to preventing leakage problems. In the production process of semiconductor devices, a complete quality control system needs to be established to ensure that every link meets standard requirements. For example, during the material procurement process, materials that meet standards must be selected; during the manufacturing process, process parameters must be strictly controlled; during the testing process, rigorous electrical performance testing must be performed. However, the production cost of the above method is relatively high and is not suitable for large-scale production.

This invention replaces the silicon substrate of the traditional E-HEMT with a material with a higher bandgap than the silicon substrate, because the material with a higher bandgap can form a higher potential barrier difference with the GaN buffer layer, making it difficult for electrons to pass through the potential barrier. The barrier reduces the current leakage from the GaN buffer layer to the substrate direction, and the replaced substrate material also has high heat dissipation performance, which can effectively dissipate the heat inside the E-HEMT and improve the heating situation inside the E-HEMT. To avoid E-HEMT failure caused by overheating inside the E-HEMT, the present invention also adds an N-type heavily doped N+ buffer layer under the GaN buffer layer. The silicon-based N+ doped layer can create an electron well, thereby further weakening the The leakage phenomenon at the substrate end reduces the overall thermal effect of the E-HEMT device.

Example 1

An E-HEMT with low leakage, referring to Figure 1, includes: a heterojunction substrate;

The substrate is a material used to support crystal growth, and the substrate plays the role of mechanical support. In the present invention, the substrate is made of silicon carbide material, whose mechanical strength and stability can effectively support various stresses and distortions during crystal growth. This is crucial to ensure uniformity and integrity of crystal growth. In addition, the substrate protects against impurities and defects during crystal growth. Secondly, the substrate plays an important role in the electrical properties of GaN HEMTs. When preparing GaN HEMTs, the electrical properties of the substrate determine the performance and stability of the device. For example, the conductivity of the substrate directly affects the efficiency and speed of current transfer. In addition, the electron affinity and bandgap width of the substrate are also crucial for adjusting the threshold voltage and electron mobility of GaN HEMT. In addition, the substrate also plays an important role in isolating the insulation layer of GaN HEMT. In the GaN HEMT preparation process, the insulating layer of the substrate is usually composed of silicon dioxide. The quality and characteristics of the insulating layer directly affect the insulation properties of GaN HEMT, such as electrical insulation and capacitance characteristics. A good insulating layer can effectively isolate different electrodes in the GaN HEMT structure and reduce leakage current and capacitive coupling effects.

The heterojunction substrate includes a base and a silicon-based N+ buffer layer;

The heterojunction of semiconductors is a special PN junction, which is formed by depositing more than two layers of different semiconductor material films on the same base. These materials have different energy band gaps. They can be compounds such as gallium arsenide. , or it can be a semiconductor alloy such as silicon-germanium. A heterojunction is an interface region formed by the contact of two different semiconductors. According to the different conductivity types of the two materials, heterojunctions can be divided into homojunctions (P-p junction or N-n junction) and heterogeneous heterojunctions (P-n or p-N). Multi-layer heterojunctions are called heterostructures. Usually the conditions for forming a heterojunction are that the two semiconductors have similar crystal structures, similar atomic spacing and thermal expansion coefficients. Heterojunctions can be manufactured using technologies such as interface alloys, epitaxial growth, and vacuum deposition. Heterojunction often has excellent optoelectronic properties that cannot be achieved by the respective PN junctions of two semiconductors, making it suitable for making ultra-high-speed switching devices, solar cells, and semiconductor lasers.

Because the heterojunction is formed by the contact of two semiconductor single crystal materials of different materials, and the lattice constants of the two different materials are often different, a lattice mismatch will occur and the two will Dangling bonds are generated at the interface of a kind of semiconductor material. Dangling bonds are some unsaturated bonds that appear in semiconductor materials with small lattice constants at the interface. These dangling bonds will seriously affect the movement of carriers, making the heterojunction have Some homojunctions do not have characteristics, such as: two-dimensional electron gas exists at the interface between the AlGaN barrier layer and the GaN layer heterojunction. Generally, the N-type GaN buffer layer is epitaxially grown first, and then the P-type AlGaN barrier layer is epitaxially grown. An AlGaN/GaN heterojunction is formed. Since AlGaN material has a wider band gap than GaN material, when reaching equilibrium, the energy band at the junction of the heterojunction interface bends, causing discontinuity in the conduction band and valence band, forming a triangular potential well at the heterojunction interface. . On the GaN side, the bottom of the conduction band is already lower than the Fermi level, so a large number of electrons will accumulate in the triangular potential well. At the same time, the high potential barrier on one side of the wide bandgap AlGaN makes it difficult for electrons to cross outside the potential well, and the electrons are restricted to move laterally in a thin layer at the interface. This thin layer is called two-dimensional electron gas (2DEG). The heterojunction energy band may have a sudden change in the energy band, or there may be an electron barrier (upward spike) at the interface, or there may be an electron potential well (downward spike) at the interface. Using the heterojunction interface will produce To overcome the characteristic of energy band bending, the present invention uses a semiconductor material with a bandgap width much larger than that of silicon as the base in the heterojunction substrate. An electron barrier will be formed at the interface of the heterojunction. The bandgap width of the base is the same as that of silicon. The greater the difference in the bandgap widths of silicon, the harder it is for electrons to cross the heterojunction, significantly improving the ability to prevent current leakage from the substrate.

In the embodiment of the present invention, the heterojunction substrate is composed of an N-type semiconductor N+ buffer layer made of silicon material and a P-type semiconductor made of a semiconductor material with a higher bandgap than silicon material and strong thermal conductivity.

The base is located under the silicon-based N+ buffer layer and adjacent to the silicon-based N+ buffer layer;

The silicon-based N+ buffer layer is located between the GaN buffer layer and the substrate and is adjacent to the GaN buffer layer.

The substrate and the silicon-based N+ buffer layer together form a heterojunction substrate. In Figure 1, from bottom to top in the vertical direction are the substrate, the silicon-based N+ buffer layer and the GaN buffer layer, and the substrate and the silicon-based N+ buffer layer The layers are closely connected, and the silicon-based N+ buffer layer is closely connected to the GaN buffer layer. In HEMT, GaN material is the key material for GaN HEMT devices and has the advantages of wide bandgap, high electron mobility and high saturation drift speed. However, due to the lattice mismatch between GaN and standard substrate materials, crystal defects and high-density lattice dislocations will occur, affecting device performance. To solve this problem, a buffer layer needs to be introduced between the substrate and the GaN material. The main function of the buffer layer is to relieve stress caused by lattice mismatch, reduce defect density, and improve film quality. Commonly used buffer layer materials include AlN, GaN, AlGaN, etc. AlGaN buffer layer or GaN buffer layer or AlN buffer layer can effectively improve the electrical properties of GaN HEMT devices and increase mobility. During the growth process of the buffer layer, the crystal quality can be optimized and defects reduced by controlling parameters such as growth temperature, thickness, and flow rate.

Preferably, the bandgap of the filling material of the substrate is greater than the bandgap of silicon.

The bandgap width refers to the width of a band gap (unit is electron volt (ev)). The energy of electrons in solids cannot take continuous values, but some discontinuous energy bands. To conduct electricity, there must be free electrons or holes. The energy band in which free electrons exist is called the conduction band, and the energy band in which free holes exist is called the valence band. In order for a bound electron to become a free electron or hole, it must obtain enough energy to jump from the valence band to the conduction band. The minimum value of this energy is the bandgap width.

The bandgap width is an important characteristic parameter of semiconductors. Its size is mainly determined by the energy band structure of the semiconductor, that is, it is related to the crystal structure and the bonding properties of atoms. A large number of electrons in the valence band of semiconductors are electrons on valence bonds (called valence electrons) and cannot conduct electricity, that is, they are not carriers. Only when the valence electrons transition to the conduction band (i.e. intrinsic excitation) and generate free electrons and free holes can conduct electricity. The hole is actually the valence bond vacancy left after the valence electron jumps to the conduction band (the movement of a hole is equivalent to the movement of a large group of valence electrons). Therefore, the size of the forbidden band width reflects a physical quantity of the degree to which valence electrons are bound, that is, the minimum energy required to generate intrinsic excitation. The energy between the lowest energy level of the conduction band and the highest energy level of the valence band. Since the valence band energy level is lower, the electrons mostly stay in the valence band. So generally the valence band is mainly holes and does not conduct electricity, while the conduction band electrons can move and conduct electricity. The bandgap width is the interval between the conduction band and the valence band, and this interval is the interval for electronic transitions. In order for the bound electrons in the valence band to become free electrons, they must gain enough energy to jump to the conduction band.

Because the bandgap width of the filling material of the base is larger than the bandgap width of silicon, it can prevent the current from flowing from the buffer layer to the substrate. The formation of the heterojunction causes the electrons to have an energy band shift between the silicon and the filling material of the base. , thereby forming an electron barrier, which can control the movement of electrons between the two materials, thereby achieving the purpose of blocking electrons outside the substrate.

Materials whose bandgap width is larger than that of silicon mainly include silicon carbide (SiC), cubic boron nitride (C-BN), gallium nitride (GaN), aluminum nitride (AlN), zinc selenide (ZnSe) and diamond wait. The bandgap width of the above materials is greater than 2eV, and the bandgap width of silicon is 1.12eV. The wide bandgap semiconductor material has the characteristics of wide bandgap, high critical breakdown electric field, high thermal conductivity, high carrier saturation drift velocity, etc., and can be used in many applications. In terms of high temperature, high frequency, high power, optoelectronics and radiation resistance.

Preferably, the filling material of the base includes: silicon carbide.

Because the band gap of silicon carbide is much larger than that of silicon, and other properties of silicon carbide are also better than silicon. For example, the breakdown field strength of silicon carbide is 3MV/cm, while the breakdown field strength of silicon is only 0.3MV/cm. Carbonization The bandgap width of silicon is much larger than that of silicon, and the corresponding intrinsic carrier concentration is smaller than that of silicon. The maximum operating temperature of wide bandgap semiconductors is higher than that of silicon materials. The breakdown field strength is much greater than that of silicon. As a preferred embodiment, the present invention selects silicon carbide as the filling material of the base.

Preferably, the doping concentration of the N+ buffer layer is 10 ¹⁹ cm ^-3 .

The doping concentration of the N+ buffer layer will affect the energy band difference between the GaN buffer layer and the substrate. The higher the doping concentration of the N+ buffer layer, the more difficult it is for electrons to reach the N+ buffer layer from the GaN buffer layer. The energy band difference between the N+ buffer layer and the substrate The greater the difference, the better the anti-leakage performance of E-HEMT. Therefore, the doping concentration of the N+ buffer layer should be set to be greater than the doping concentration of the GaN buffer layer, making the electron barrier larger and improving the anti-leakage performance of the substrate. Even better, as a preferred embodiment, the present invention sets the doping concentration of the N+ buffer layer to 10 ¹⁹ cm ^-3 .

Preferably, the thickness of the N+ buffer layer is 3um.

The greater the thickness of the N+ buffer layer, the more difficult it is for electrons to pass through the N+ buffer layer and reach the substrate, and the better the anti-leakage performance of the E-HEMT. If the thickness of the N+ buffer layer is increased, the doping concentration of the N+ buffer layer can be reduced. , Correspondingly, if the thickness of the N+ buffer layer is relatively small, in order to prevent electrons from passing through the N+ buffer layer, the doping thickness of the N+ buffer layer needs to be increased. If the thickness of the N+ buffer layer is too large, the chip area will increase. Large defects, so the thickness of the N+ buffer layer should not be too large. As a preferred embodiment, the present invention sets the doping concentration of the N+ buffer layer to 10 ¹⁹ cm ^-3 , which significantly improves the anti-leakage performance of the substrate.

Preferably, the thickness of the substrate is 25um.

The substrate provides mechanical support for the entire E-HEMT, and can conduct heat conduction with the external environment, and can discharge the heat generated by the E-HEMT during normal operation to the outside world. Because the substrate needs to provide mechanical support for the E-HEMT, the thickness of the substrate cannot Less than 20um, if the substrate is too thick, the chip area will increase. As a preferred embodiment, the present invention sets the thickness of the substrate to 25um.

Preferably, the thermal conductivity of the filling material of the base is greater than or equal to the thermal conductivity of silicon carbide.

Thermal conductivity is the thermal conductivity of a semiconductor material, which reflects the thermal conductivity of the semiconductor material. Thermal conductivity is defined as the heat transferred by the unit temperature gradient (the temperature decreases by 1K within a length of 1m) through the unit thermal conductive surface in the unit time. Thermal conductivity Objects with a large thermal conductivity are excellent thermal conductors; objects with a small thermal conductivity are poor conductors of heat or are thermal insulators. The value of thermal conductivity is also affected by temperature. The density of a substance is large, and its thermal conductivity is usually also large. The thermal conductivity of metals decreases when they contain impurities. The thermal conductivity of alloys is lower than that of pure metals. The thermal conductivities of various substances range from 50 to 415 W/(m×K) for metals and 12 to 120 W/ for alloys. (m×K), insulation materials are 0.03～0.17 W/(m×K), liquids are 0.17～0.7 W/(m×K), gases are 0.007～0.17 W/(m×K), carbon nanotubes are up to 1000 W/(m×K) or more. The thermal conductivity of traditional semiconductor material silicon is 150 W/(m×K), and the thermal conductivity of silicon carbide is 490 W/(m×K), which is much larger than silicon. Therefore, in the selection of base filling materials, thermal conductivity Materials with a conductivity greater than or equal to silicon carbide and a band gap greater than silicon can be used as filling materials for the substrate.

Preferably, it also includes: GaN buffer layer, AlGaN barrier layer, GaN layer, source electrode, drain electrode and gate electrode,

The GaN buffer layer is located above the heterojunction substrate;

The main function of the buffer layer is to relieve stress caused by lattice mismatch, reduce defect density, and improve film quality. Commonly used buffer layer materials include AlN, GaN, AlGaN, etc. The GaN buffer layer can effectively improve the electrical properties of GaN HEMT devices and increase mobility. During the growth process of the GaN buffer layer, the crystal quality can be optimized and defects reduced by controlling parameters such as growth temperature, thickness, and flow rate.

The GaN layer is located above the GaN buffer layer;

The AlGaN barrier layer is located above the GaN layer;

The source is located above the AlGaN barrier layer;

The gate is located above the AlGaN barrier layer;

By adjusting the external gate voltage (relative to the source), the two-dimensional electron gas (2DEG) density in the channel can be adjusted, thereby achieving control of the gate voltage and drain voltage on the drain current (output current).

The drain is located above the AlGaN barrier layer.

GaN-based heterojunction field-effect transistors (GaN HEMTs) operate using high concentration and high electron mobility 2DEG formed in the AlGaN/GaN heterojunction channel. The current common GaN HEMT is a lateral device. Its structure mainly includes a substrate, a GaN buffer layer, a gallium nitride channel layer (GaN layer), an AlGaN barrier layer, and an AlGaN barrier layer that are grown sequentially from bottom to top. The source, gate, and drain on the upper surface all form ohmic contact with the AlGaN barrier layer; the gate forms Schottky contact with the AlGaN barrier layer; the AlGaN potential between the source and the drain A passivation layer grows on the surface of the barrier layer.

Example 2

A method for preparing E-HEMT with low leakage, refer to Figure 2 and Figure 3, including:

S100, epitaxially layer an N-type heavily doped silicon layer above the substrate to form a silicon-based N+ buffer layer;

The epitaxial process refers to the process of growing a completely ordered single crystal layer on a substrate. The epitaxial process is the growth of a crystal layer with the same lattice orientation as the original substrate on a single crystal substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. According to the different phase states of the growth source, epitaxial growth methods are divided into solid phase epitaxy, liquid phase epitaxy, and vapor phase epitaxy. In integrated circuit manufacturing, the commonly used epitaxy methods are solid-phase epitaxy and vapor-phase epitaxy.

Solid-phase epitaxy refers to the growth of a single crystal layer on a substrate by a solid source. For example, thermal annealing after ion implantation is actually a solid-phase epitaxy process. During ion implantation processing, the silicon atoms of the silicon wafer are bombarded by high-energy implanted ions, leaving the original crystal lattice position and becoming amorphous, forming a surface amorphous silicon layer. After high-temperature thermal annealing, the amorphous atoms return to the original lattice position. The lattice position is consistent with the atomic orientation within the substrate.

The growth methods of vapor phase epitaxy include chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), atomic layer epitaxy (ALE), etc. In the embodiment of the present invention, chemical vapor epitaxy (CVE) is used to form the N-drift layer. The principles of chemical vapor epitaxy and chemical vapor deposition (CVD) are basically the same. They are both processes that use gas mixing to react chemically on the surface of the wafer to deposit thin films. The difference is that because chemical vapor epitaxy grows a single crystal layer, it is The impurity content in the equipment and the cleanliness requirements on the silicon wafer surface are both higher. In integrated circuit manufacturing, CVE can also be used in epitaxial silicon wafer processes and MOS transistor embedded source-drain epitaxial processes. The epitaxial silicon wafer process is to epitaxially extend a layer of single crystal silicon on the surface of the silicon wafer. Compared with the original silicon substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, thus improving the yield of semiconductor manufacturing. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to device design. For example, it can be used to reduce substrate resistance, enhance substrate isolation, etc. The embedded source-drain epitaxy process refers to the process of epitaxially growing doped silicon germanium or silicon in the source and drain regions of the transistor. The main advantages of introducing the embedded source-drain epitaxial process include: it can grow a pseudocrystalline layer that contains stress due to lattice adaptation, improving channel carrier mobility; it can dope the source and drain in situ, reducing the parasitic resistance of the source-drain junction , Reduce the defects of high-energy ion implantation.

S200, epitaxially forming a GaN buffer layer, a GaN layer and an AlGaN barrier layer on top of the silicon-based N+ buffer layer;

S300, deposit gate, drain and source electrodes.

Metal electrode deposition processes are divided into chemical vapor deposition (CVD) and physical vapor deposition (PVD). CVD refers to the method of chemically depositing coatings on the surface of wafers, generally by applying energy to a mixed gas. Assuming that substance (A) is deposited on the wafer surface, two gases (B and C) that can generate substance (A) are first input to the deposition equipment, and then energy is applied to the gas to promote a chemical reaction between gases B and C.

PVD (physical vapor deposition) coating technology is mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion plating. The main methods of physical vapor deposition include: vacuum evaporation, sputtering coating, arc plasma coating, ion coating and molecular beam epitaxy, etc. Corresponding vacuum coating equipment includes vacuum evaporation coating machines, vacuum sputtering coating machines and vacuum ion coating machines.

Both chemical vapor deposition (CVD) and physical vapor deposition (PVD) can be used as technical means to deposit metal electrodes. In embodiments of the present invention, a chemical vapor deposition method is used to deposit metal electrodes. The chemical vapor deposition process is divided into three stages: diffusion of reaction gas to the surface of the substrate, adsorption of the reaction gas on the surface of the substrate, and chemical reaction on the surface of the substrate to form a solid deposition. The substances and the gas phase by-products produced are separated from the surface of the matrix. The most common chemical vapor deposition reactions are: thermal decomposition reactions, chemical synthesis reactions and chemical transport reactions.

Preferably, S100 epitaxially adds an N-type heavily doped silicon layer over the substrate to form a silicon-based N+ buffer layer, including:

S101, a silicon layer with a thickness of 3um is epitaxially grown on the substrate;

S102, perform ion implantation in the silicon layer to form a silicon-based N+ buffer layer with a doping concentration of 10 ¹⁹ cm ^-3 .

The present invention uses ion implantation to implant ions into the silicon layer to form an N+ buffer layer with a doping concentration of 10 ¹⁹ cm ^-3 . The doping concentration and thickness of the silicon-based N+ buffer layer are controlled by controlling the number, dose, and energy of ion implantation. Ion implantation is to emit an ion beam in a vacuum towards a solid material. After the ion beam hits the solid material, its speed slowly slows down due to the resistance of the solid material, and finally stays in the solid material. The ions of an element are accelerated into a solid target, thereby changing the physical, chemical or electrical properties of the target. Ion implantation is often used in the manufacturing of semiconductor devices, metal surface treatment, and materials science research. If the ions are stopped and retained in the target, the ions will change the elemental composition of the target (if the ions are of a different composition than the target). Ion implantation beamline designs all contain a common set of functional components. The main part of an ion beamline consists of a device called an ion source, which is used to generate ion species. The source is tightly coupled to a bias electrode to extract ions into the beamline, and most commonly to some means of selecting specific ion species for transport into the main accelerator section. Mass selection accompanies the extracted ion beam through the magnetic field region, with its exit path restricted by blocking holes or slits that only allow ions with mass and velocity/charge to continue along the beamline. If the target surface is larger than the ion beam diameter, and the implant dose is evenly distributed over the target surface, some combination of beam scanning and wafer motion can be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implant process stopped at the desired dose level.

Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When injected into a semiconductor, each dopant atom can generate charge carriers in the semiconductor after annealing. A hole can be created for P-type dopants and an electron for N-type dopants. Changes the conductivity of the semiconductor near the doped region.

This invention replaces the silicon substrate of the traditional E-HEMT with a material with a higher bandgap than the silicon substrate, because the material with a higher bandgap can form a higher potential barrier difference with the GaN buffer layer, making it difficult for electrons to pass through the potential barrier. The barrier reduces the current leakage from the GaN buffer layer to the substrate direction, and the replaced substrate material also has high heat dissipation performance, which can effectively dissipate the heat inside the E-HEMT and improve the heating situation inside the E-HEMT. To avoid E-HEMT failure caused by overheating inside the E-HEMT, the present invention also adds an N-type heavily doped N+ buffer layer under the GaN buffer layer. The silicon-based N+ doped layer can create an electron well, thereby further weakening the The leakage phenomenon at the substrate end reduces the overall thermal effect of the E-HEMT device.

The above descriptions are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be practiced in other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims (10)

1. An E-HEMT with low leakage, characterized in that it includes: a heterojunction substrate; The heterojunction substrate includes a base and a silicon-based N+ buffer layer; The substrate is located below the silicon-based N+ buffer layer and adjacent to the silicon-based N+ buffer layer; The silicon-based N+ buffer layer is located between the GaN buffer layer and the substrate and adjacent to the GaN buffer layer. 2. An E-HEMT with low leakage according to claim 1, characterized in that the bandgap width of the filling material of the base is greater than the bandgap width of silicon. 3. The E-HEMT with low leakage according to claim 1, wherein the filling material of the base includes: silicon carbide. 4. An E-HEMT with low leakage according to claim 1, characterized in that the doping concentration of the N+ buffer layer is 10 ¹⁹ cm ^-3 . 5. An E-HEMT with low leakage according to claim 1, characterized in that the thickness of the N+ buffer layer is 3um. 6. An E-HEMT with low leakage according to claim 1, characterized in that the thickness of the substrate is 25um. 7. An E-HEMT with low leakage according to claim 2, characterized in that the thermal conductivity of the filling material of the base is greater than or equal to the thermal conductivity of silicon carbide. 8. An E-HEMT with low leakage according to claim 1, further comprising: a GaN buffer layer, an AlGaN barrier layer, a GaN layer, a source electrode, a drain electrode and a gate electrode, The GaN buffer layer is located above the heterojunction substrate; The GaN layer is located above the GaN buffer layer; The AlGaN barrier layer is located above the GaN layer; The source electrode is located above the AlGaN barrier layer; The gate electrode is located above the AlGaN barrier layer; The drain electrode is located above the AlGaN barrier layer. 9. A method for preparing E-HEMT with low leakage, characterized by comprising: Epitaxially extend an N-type heavily doped silicon layer over the substrate to form a silicon-based N+ buffer layer; Epitaxially forming a GaN buffer layer, a GaN layer and an AlGaN barrier layer above the silicon-based N+ buffer layer; Deposit gate, drain and source electrodes. 10. A method for preparing an E-HEMT with low leakage according to claim 9, characterized in that, epitaxially extending an N-type heavily doped silicon layer over the substrate to form a silicon-based N+ buffer layer includes: A silicon layer with a thickness of 3um is epitaxially grown on the substrate; Ions are implanted into the silicon layer to form a silicon-based N+ buffer layer with a doping concentration of 10 ¹⁹ cm ^-3 .