CN117374125A - Trench MOSFET device and preparation process thereof - Google Patents

Abstract

A trench MOSFET device and a preparation process thereof are provided, relating to the technical field of semiconductors. The device includes: an epitaxial layer formed on one side of the substrate, a shielding trench arranged side by side in the epitaxial layer, and a MOS trench arranged between adjacent shielding trenches; a shielding trench field insulation is formed inside the shielding trench. layer, a shield electrode is deposited on the inside of the shielding trench field insulating layer; a MOS trench thick oxide layer is formed in the MOS trench, and a gate oxide layer is formed on the top of the MOS trench thick oxide layer. Between the MOS trench thick oxide layer and the gate A MOS gate is deposited inside the oxygen layer; the thickness of the gate oxide layer is smaller than the thickness of the MOS trench thick oxide layer; a part of the top dielectric layer is formed on top of the MOS gate. The device provides good charge balance by setting the MOS trench, resulting in a good trade-off between on-resistance and breakdown voltage, thereby reducing the device channel length and the thickness of the epitaxial layer, improving the device's withstand voltage effect, and also helping to reduce parasitics capacitance.

Description

A trench MOSFET device and its preparation process

Technical field

The present disclosure relates to the technical field of semiconductors. Specifically, the present disclosure relates to a trench MOSFET device and a manufacturing process thereof.

Background technique

The trench MOSFET device is a new type of vertical structure MOSFET device. Because this trench MOSFET device has the trench deep into the silicon body, more cells can be connected in parallel in the design, thereby reducing the on-resistance and achieving greater current conduction. pass and wider switching speeds.

However, trench MOSFET devices in the existing technology are limited in reducing the channel length, making the trench MOSFET device prone to breakdown; or, in order to ensure that the device is not broken down, when the breakdown voltage is increased, the current flowing through If it is too small, the on-resistance will be too large and the device will not conduct easily.

Contents of the invention

In order to solve the problems in the prior art, a first aspect of the present disclosure provides a trench MOSFET device. This trench MOSFET device includes:

An epitaxial layer formed on one side of the substrate, shielding trenches arranged in parallel in the epitaxial layer, and MOS trenches arranged between adjacent shielding trenches; wherein,

A thick oxide layer of the shielding trench is formed inside the shielding trench, and a shielding electrode is deposited inside the thick oxide layer of the shielding trench;

A MOS trench thick oxide layer is formed inside the MOS trench, a gate oxide layer is formed on the top of the MOS trench thick oxide layer, and a MOS gate is deposited inside the MOS trench thick oxide layer and the gate oxide layer; where, the gate The thickness of the oxygen layer is smaller than the thickness of the thick oxygen layer of the MOS trench;

A portion of the top dielectric layer is formed on top of the MOS gate.

Optionally, a well region is also formed on the epitaxial layer between the MOS trench and the shielding trench.

Optionally, an active electrode is also formed on the top of the side of the well region close to the MOS trench, and the source electrode is located on the side of the gate oxide layer away from the MOS gate.

Optionally, the thickness d of the gate oxide layer satisfies:

d>Vgs/E;

Among them, Vgs is the driving voltage applied to the MOS gate, and E is the critical breakdown electric field at which the gate oxide layer breaks down.

Optionally, a top dielectric layer is formed on the top surfaces of the gate oxide layer and the source electrode, and a top dielectric layer is also formed on the top of the well region close to the shielding trench side.

Optionally, the shielding trench and MOS trench also meet:

h ₁ > h ₂ ;

Among them, h ₁ is the thickness of the shielding trench in the direction perpendicular to the substrate; h ₂ is the thickness of the MOS trench in the direction perpendicular to the substrate.

Optionally, the trench MOSFET device further includes a drain electrode, and the drain electrode is formed on a side of the substrate away from the epitaxial layer.

Optionally, the doping type of the substrate, the epitaxial layer and the source electrode is the first conductive type; wherein the doping concentration of the substrate and the source electrode is higher than the doping concentration of the epitaxial layer.

Optionally, the doping type of the well region is the second conductivity type.

Optionally, the material of the epitaxial layer includes: silicon, silicon carbide, gallium nitride, gallium oxide and diamond.

Optionally, the applicable voltage range of the trench MOSFET device provided in this application is above 30V.

Optionally, the well region is connected to the source electrode and the shield electrode through metal lines and is grounded.

The second aspect of the present disclosure provides a manufacturing process for a trench MOSFET device, which is suitable for any of the trench MOSFET devices provided by the first aspect of the present disclosure. The manufacturing process includes:

An epitaxial layer is grown on one side of the substrate;

Multiple parallel shielding trenches are formed into the epitaxial layer from the side surface of the epitaxial layer away from the substrate, and MOS trenches are formed between each two adjacent shielding trenches;

Grow or deposit a thick oxide layer of the shielding trench on the inner wall of the shielding trench and engrav it back;

Grow or deposit a thick oxide layer of the MOS trench on the inner wall of the MOS trench and etch back;

Grow or deposit a gate oxide layer on the inner wall of the MOS trench on top of the thick oxide layer of the MOS trench;

Grow or deposit electrodes inside the thick oxide layer of the shielding trench and the thick oxide layer of the MOS trench and etch back to form the shielding electrode inside the shielding trench and the MOS gate inside the MOS trench respectively;

Grow or deposit a top dielectric layer on the top surface of the MOS gate and etch back;

Perform ion implantation into the epitaxial layer between the MOS trench and the shielding trench with impurities of different conductivity types from those of the substrate to form a well region that is inverse to the substrate;

The well region is doped with impurities near the top of the MOS trench to form the source electrode;

The epitaxial layer between the MOS trench and the shielding trench is etched and impurities of the same conductivity type as the well region are ion-implanted to form ohmic contact with the metal;

A metal layer is deposited on the lower surface of the substrate to form a drain electrode.

The technical solution in the present disclosure can play the role of a field plate through a thick shielding trench and thick oxide layer, so as to provide a good charge balance between the source electrode and the epitaxial layer in the device, thereby leading to on-resistance and breakdown A good voltage trade-off is to reduce the on-resistance as much as possible while the device can withstand a larger breakdown voltage. At the same time, while keeping the overall breakdown voltage unchanged, since the thick oxide layer of the shielding trench can bear part of the breakdown voltage, the channel length can be greatly reduced compared with single trench MOSFET devices, thus The channel resistance is reduced; since this application deposits a thick MOS trench thick oxide layer, the insulating layer can also withstand part of the breakdown voltage, making the device's voltage withstand effect more obvious. Due to the existence of the thick oxide layer in the MOS trench, the length of the shielding trench and the thickness of the epitaxial layer can be significantly reduced while maintaining the overall breakdown voltage, achieving device miniaturization and reducing on-resistance. The parasitic capacitance between the MOS gate and drain electrode is reduced, greatly improving the conduction capability of the device.

Description of the drawings

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the following description, serve to explain the principles of the disclosure.

Figure 1 shows an optional cross-sectional schematic diagram of a trench MOSFET device provided by an embodiment of the present disclosure;

FIG. 2 shows an optional process flow diagram of a trench MOSFET device provided by an embodiment of the present disclosure.

The reference symbols in the figure respectively indicate:

1: Epitaxial layer; 2: MOS trench; 3: Shielding trench; 4: MOS trench thick oxide layer; 5: MOS gate; 51: MOS gate first part; 52: MOS gate second part 6: Top dielectric layer; 7: Shielding trench thick oxide layer; 8: Shield electrode; 9: Gate oxide layer; 10: Well area; 11: Metal line; 12: Source electrode; 13: Substrate; 14: Drain electrode.

Detailed ways

The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. This disclosure may, however, be embodied in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. The same reference numbers refer to the same parts throughout. Furthermore, in the drawings, the thicknesses, ratios, and dimensions of components are exaggerated for clarity of illustration.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless the context clearly dictates otherwise, "a," "an," "the," and "at least one" as used herein do not imply a limitation on quantity but are intended to include both the singular and the plural. For example, "a component" has the same meaning as "at least one component" unless the context clearly dictates otherwise. "At least one" should not be construed as being limited to the number "one". "Or" means "and/or". The term "and/or" includes any and all combinations of one or more of the associated listed items.

Unless otherwise defined, all terms, including technical and scientific terms, used herein have the same meaning as commonly understood by one of ordinary skill in the art. Terms as defined in commonly used dictionaries shall be construed to have the same meaning as in the relevant technical context and shall not be construed in an idealized or overly formal sense unless expressly defined in the specification. Has a formal meaning.

The meaning of "includes" or "includes" specifies a property, number, step, operation, component, component, or combination thereof, but does not exclude other properties, quantities, steps, operations, component, component, or combination thereof.

Embodiments are described herein with reference to cross-sectional illustrations that are idealized embodiments. Thus, variations in shape from those shown in the illustrations are contemplated, for example as a result of manufacturing techniques and/or tolerances. Thus, embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, regions shown or described as flat may typically have rough and/or non-linear characteristics. Furthermore, the acute angles shown can be rounded. Therefore, the regions shown in the figures are schematic in nature and their shapes are not intended to show the precise shapes of the regions and are not intended to limit the scope of the claims.

As mentioned earlier, trench MOSFET devices have a good effect on reducing on-resistance (Rdson) and increasing switching speed. A better way to reduce on-resistance is to reduce on-resistance by reducing the channel length, thus making The device is more voltage resistant. However, for single-trench MOSFET devices, there is only one MOS gate with a wide top and a narrow bottom that penetrates deep into the epitaxial layer through the trench, which places great limitations on reducing the channel length.

Based on this, the inventor provides a trench MOSFET device structure, as shown in Figure 1, etching multiple shielding trenches inside the epitaxial layer, forming MOS trenches between each two shielding trenches, and A MOS trench thick oxide layer and a MOS gate that is wide at the top and narrow at the bottom are deposited inside the MOS trench, and a thick oxide layer for the shielding trench and the source electrode are deposited inside the shielding trench. This structure can withstand more breakdown voltage (BV) by using two shielding trench thick oxide layers as field plates, making the on-resistance of this structure smaller, improving conductivity while achieving conduction Good trade-off between resistance and breakdown voltage.

Hereinafter, exemplary embodiments according to the present disclosure will be described with reference to the accompanying drawings.

FIG. 1 shows an optional cross-sectional schematic diagram of a trench MOSFET device provided by an embodiment of the present disclosure. As shown in Figure 1, the trench MOSFET device includes:

The epitaxial layer 1 formed on one side of the substrate 13 is juxtaposed with the shielding trenches 3 in the epitaxial layer 1, and the MOS trenches 2 arranged between adjacent shielding trenches 3; wherein, inside the shielding trench 3 A shielding trench thick oxide layer 7 is formed, and a shielding electrode 8 is deposited inside the shielding trench thick oxide layer 7;

A MOS trench thick oxide layer 4 is formed inside the MOS trench 2 , a gate oxide layer 9 is formed on the top of the MOS trench thick oxide layer 4 , and MOS is deposited inside the MOS trench thick oxide layer 4 and the gate oxide layer 9 Gate 5; wherein, the thickness of the gate oxide layer 9 is smaller than the thickness of the MOS trench thick oxide layer 4;

A part of the top dielectric layer 6 is formed on the top of the MOS gate 5 .

According to the above-described embodiment, the substrate 13 may be composed of a heavily doped semiconductor material. In the embodiment of the present application, the substrate 13 may be a heavily doped region doped with N-type impurities of the first conductive type, with a doping concentration of 10 ¹⁹ ~10 ²⁰ cm ^-3 .

According to the above embodiment, the epitaxial layer 1 may also be called a "drift region", and the epitaxial layer 1 may be an epitaxial layer of the first conductivity type, that is, N-type, disposed on the substrate 13 through, for example, an epitaxial process. In the embodiment of the present application, the epitaxial layer 1 may be an N-lightly doped region, with a doping concentration of 10 ¹⁴ ~10 ¹⁸ cm ^-3 . In the embodiment of the present application, the doping concentration of the substrate 13 is higher than the doping concentration of the epitaxial layer 1 . The material of the epitaxial layer 1 may include but is not limited to silicon, silicon carbide, gallium nitride, gallium oxide and diamond.

Those skilled in the art should realize that although the embodiments of the present application are described herein by taking the first conductivity type as N-type and the second conductivity type as P-type as an example, the present application is not limited thereto. In other embodiments of the present application, the first conductivity type may also be P-type and the second conductivity type may be N-type.

In addition, those skilled in the art will recognize that the term "heavily doped region" herein generally refers to a region with a doping concentration greater than or equal to 10 ¹⁸ cm ^-3 and is represented by the symbol "+". Furthermore, the term "lightly doped region" herein refers to a region with a doping concentration less than 10 ¹⁸ cm ^-3 and is represented by a symbol "-". For example, "N+" represents an N-type heavily doped region with a doping concentration greater than or equal to 10 ¹⁸ cm ^-3 , and "N-" represents an N-type lightly doped region with a doping concentration less than 10 ¹⁸ cm ^-3 .

In the embodiment of the present application, the MOS trench thick oxide layer 4 can be grown or deposited on the inner wall of the MOS trench 2 through, for example, a thermal oxidation process or a deposition process. The MOS trench thick oxide layer 4 is formed at the bottom of the MOS trench 2. And the gate oxide layer 9 is grown or deposited on the top of the MOS trench thick oxide layer 4 through a thermal oxidation process or a deposition process. The MOS gate electrode 5 is grown or deposited in the groove surrounded by the MOS trench thick oxide layer 4 and the gate oxide layer 9 . The MOS gate 5 is a T-shaped gate, and the lateral width of the first part 51 of the MOS gate is greater than the lateral width of the second part 52 of the MOS gate. That is, the thickness of the MOS trench thick oxide layer 4 is greater than the thickness of the gate oxide layer 9 . Increasing the thickness of the MOS trench thick oxide layer 4 can reduce the possibility of breakdown of the MOS trench thick oxide layer 4 when the breakdown point is near the MOS trench 2. It can not only reduce the length and length of the shielding trench 3 The thickness of the epitaxial layer 1 can also improve the voltage resistance of the device, making the MOS gate 5 more stable. At the same time, thickening the MOS trench thick oxide layer 4 can also help reduce the parasitic capacitance (C _gd ) between the MOS gate 5 and the drain electrode 14 and increase the operating frequency of the circuit.

According to the above embodiment, the shielding trench thick oxide layer 7 can be grown or deposited on the inner wall of the shielding trench 3 through a thermal oxidation process or a deposition process, and the shielding electrode 8 can be deposited inside the shielding trench thick oxide layer 7 . In some optional embodiments, the gate oxide layer 9 and the shielding trench thick oxide layer 7 may be made of the same material. In some optional embodiments, the materials of the gate oxide layer 9 and the shielding trench thick oxide layer 7 may also be different. It is not difficult to understand that the materials of the shielding trench thick oxide layer 7 and the MOS trench thick oxide layer 4 can be the same or different. Among them, the thickness of the shielding trench thick oxide layer 7 is greater than the thickness of the MOS trench thick oxide layer 4, so that the shielding trench thick oxide layer 7 has the function of a field plate. The trench MOSFET device added with the field plate can enhance the resistance of the device itself. Therefore, the on-resistance can be reduced to a certain extent, that is, a good charge balance is provided between the shield electrode 8 and the epitaxial layer 1 in the thick oxide layer 7 of the shielding trench, thereby achieving on-resistance and breakdown. A good trade-off for voltage.

In addition, since the gate oxide layer and the thick oxide layer need to withstand a certain degree of high voltage during the operation of the trench MOSFET device, they need to be denser films, such as through a high-temperature thermal oxidation process or chemical vapor deposition (CVD). , Chemical Vapor Deposition) insulating film of silicon oxide or silicon nitride, or a composite insulating film of silicon oxide and silicon nitride. Due to the withstand voltage problem, the reduction of the trench thickness in the device is limited. The shorter the trench thickness, the smaller the on-resistance. The lower the voltage withstand level of the device, the easier it will be to be broken down. In the embodiment of the present application, the thick oxide layers 7 on both sides of the shielding trench act as field plates, enhancing the voltage resistance of the device itself. Therefore, the thickness of the MOS trench 2 can be reduced, and the channel resistance and drift can be reduced. resistance, thus reducing the thickness of the epitaxial layer 1, thereby improving the conductivity of the device while miniaturizing the device.

According to the above embodiment, as shown in FIG. 1 , the bottom of the trench is provided with a rounded structure to reduce physical damage and defects on the trench surface. In other words, the trench bottom may be U-shaped.

In the embodiment of the present application, a well region 10 is formed between each of the plurality of shielding trenches 3 and the MOS trench 2. Optionally, this region may be formed by, for example, an ion implantation process or a high-temperature annealing process. P-type lightly doped region of epitaxial layer 1. In the embodiment of the present application, the doping type of the well region 10 is different from the doping type of the substrate 13 . For example, the well region 10 in this application is an N-type lightly doped region formed on the epitaxial layer 1 through an ion implantation process or a high-temperature annealing process.

According to the above embodiment, the source electrode 12 is formed between the gate oxide layer 9 and the side of the well region 10 close to the MOS trench 2 through, for example, an ion implantation process and a high-temperature annealing process. In the embodiment of the present application, the doping type of the source electrode 12 is the same as the doping type of the substrate 13 .

According to the above embodiment, the well region 10 is located above the side close to the MOS trench 2 , and the source electrode 12 is located on the side of the gate oxide layer 9 away from the MOS gate 5 . Further, in this application, the well region 10 and the source electrode 12 are connected through the metal wire 11 . In this way, the potential of the well regions 10 on both sides can be kept the same, thereby reducing the well bias effect and the well proximity effect. Among them, the metal wire 11 may be a metal wiring or a bonding wire.

According to the above embodiment, the present application also deposits a top dielectric layer 6 on the top surfaces of the MOS gate 5 and the source electrode 12 through a high-temperature thermal oxidation process or a chemical vapor deposition process.

In the embodiment of the present application, the trench MOSFET device also includes a metal layer formed on the lower surface of the substrate 13 through a sputtering process. According to embodiments of the present application, a metal pattern electrically connected to the substrate 13 may be provided in the metal layer to serve as the drain electrode 14 . The drain electrode 14 is located on the side of the substrate 13 away from the epitaxial layer 1 .

According to the embodiment of the present application, the thickness of the shielding trench 3 and the thickness of the MOS trench 2 also satisfy:

h ₁ > h ₂ ; (1)

Among them, h ₁ is the thickness of the shielding trench 3 along the direction perpendicular to the substrate 13 ; h ₂ is the thickness of the MOS trench 2 along the direction perpendicular to the substrate 13 .

According to the above embodiment, the thickness of the shielding trench 3 is greater than the thickness of the MOS trench 2 such that: Rdson ∝ BV ⁿ . The above formula enables the trench MOSFET device to achieve a good balance between reducing conduction losses and ensuring sufficient withstand voltage value. Optionally, along the direction perpendicular to the substrate 13, the thickness of the shielding trench 3 is 1~20 μm. Optionally, along the direction perpendicular to the substrate 13, the thickness of the MOS trench 2 is 0.5~10 μm.

According to the above embodiment, the thickness of the gate oxide layer 9 can satisfy:

d>Vgs/E; (2)

Wherein, Vgs is the driving voltage applied to the MOS gate 5, and E is the critical breakdown electric field at which the gate oxide layer 9 breaks down. This formula can solve the reliability problem during the operation of the trench MOSFET device.

Those skilled in the art will appreciate that although the semiconductor manufacturing processes used to form various components of trench MOSFET devices are illustrated above, such as photolithography, epitaxy, deposition, implantation, sputtering, etc., the present application is not limited thereto. Based on the teachings of this application, those skilled in the art can use other semiconductor processes to obtain the same structure as the trench MOSFET device described herein, and all these modifications should be covered by the scope of this application.

FIG. 2 shows an optional process flow diagram of a trench MOSFET device provided by an embodiment of the present disclosure. As shown in FIG. 2 , an embodiment of the present application also provides a manufacturing process suitable for the trench MOSFET device provided in any of the above embodiments. The preparation process includes:

In the embodiment of the present application, an epitaxial layer 1 is grown on one side surface of the substrate 13 , and multiple parallel shields are formed through an etching process from the side surface of the epitaxial layer 1 away from the substrate 13 toward the inside of the epitaxial layer 1 . Trench 3, and MOS trench 2 is formed through an etching process between every two adjacent shielding trenches 3. For example, the MOS trench 2 can be a U-shaped trench, and the multiple shielding trenches 3 can be U-shaped groove.

Further, the shielding trench thick oxide layer 7 is grown or deposited on the inner wall of the shielding trench 3 through a thermal oxidation process or a deposition process; the MOS trench is grown or deposited on the inner wall of the MOS trench 2 through a thermal oxidation process or a deposition process. Thick Oxygen Layer 4. In the embodiment of the present application, the thickness of the shielding trench thick oxide layer 7 is greater than the thickness of the MOS trench thick oxide layer 4 .

Further, a gate oxide layer 9 is grown or deposited on the inner wall of the MOS trench 2 on top of the MOS trench thick oxide layer 4 through a thermal oxidation process or a deposition process.

Further, electrodes are grown or deposited inside the shielding trench thick oxide layer 7 and the MOS trench thick oxide layer 4 and etched back to form the shielding electrode 8 inside the shielding trench 3 and the MOS inside the MOS trench 2 respectively. Gate 5. In the embodiment of the present application, a T-shaped gate is grown or deposited inside the MOS trench thick oxide layer 4. The bottom of the T-shaped gate is U-shaped, and the lower half of the T-shaped gate is at the height of the MOS trench thick oxide layer 4. consistent. The part where the bottom of the T-shaped gate contacts the top of the MOS trench thick oxide layer 4 has a certain tilt angle, and a top dielectric layer 6 is grown or deposited on the top of the T-shaped gate and etched back.

Further, the epitaxial layer 1 between the MOS trench 2 and the shielding trench 3 is etched, and impurities with different conductivity types from the substrate 13 are injected through an ion implantation process and a high-temperature annealing process to form two substrates. The bottom 13 is an inverted and symmetrical well region 10 .

Further, impurities are doped above the well region 10 close to the MOS trench 2 to form a source electrode 12 .

Further, the epitaxial layer 1 between the MOS trench 2 and the shielding trench 3 is etched and impurities of the same conductivity type as the well region are ion-implanted to form ohmic contact with the metal.

Further, a metal line 11 is formed through a physical deposition process and a metal etching process to electrically connect the well region 10, the source electrode 12, and the shield electrode 8 on both sides of the MOS trench 2 and ground them.

Further, on the lower surface of the substrate 13, a metal layer is deposited through a physical deposition process to form the drain electrode 14.

In summary, the trench MOSFET device provided by the embodiments of the present disclosure can play the role of a field plate through a relatively thick shielding trench thick oxide layer, so that a good gap between the shielding electrode and the epitaxial layer in the device is maintained. charge balance, thereby maintaining a good trade-off between on-resistance and breakdown voltage, that is, reducing on-resistance as much as possible when the device can withstand a larger breakdown voltage. At the same time, while keeping the overall breakdown voltage unchanged, since the thick oxide layer of the shielding trench can bear most of the breakdown voltage, the trench length of trench MOSFET devices can be longer than that of single trench MOSFET devices. The reduction in amplitude, that is, while keeping the overall breakdown voltage unchanged, can significantly reduce the length of the MOS trench and reduce the on-resistance. Since this application deposits a thick oxide layer in the MOS trench, the parasitic capacitance between the MOS gate and the drain electrode is reduced, and the operating frequency of the device is greatly increased.

The above are only specific implementation modes of the embodiments of the present disclosure, but the protection scope of the embodiments of the present disclosure is not limited thereto. Any person familiar with the technical field can easily implement the method within the technical scope disclosed in the embodiments of the present disclosure. Any changes or substitutions that come to mind should be included within the protection scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure should be subject to the protection scope of the claims.

Claims (12)

1. A trench MOSFET device, comprising:

an epitaxial layer (1) formed on one side of a substrate (13), shielding trenches (3) provided in parallel in the epitaxial layer (1), and MOS trenches (2) provided between adjacent shielding trenches (3); wherein,

a shielding groove thick oxygen layer (7) is formed in the shielding groove (3), and a shielding electrode (8) is deposited on the inner side of the shielding groove thick oxygen layer (7);

a MOS groove thick oxygen layer (4) is formed in the MOS groove (2), a gate oxygen layer (9) is formed at the top of the MOS groove thick oxygen layer (4), and a MOS grid (5) is deposited on the inner sides of the MOS groove thick oxygen layer (4) and the gate oxygen layer (9); wherein the thickness of the gate oxide layer (9) is smaller than the thickness of the MOS groove thick oxide layer (4);

a part of a top dielectric layer (6) is formed on the top of the MOS gate (5);

and a drain electrode (14) formed on the substrate (13) side away from the epitaxial layer.

2. Trench MOSFET device according to claim 1, characterized in that a well region (10) is also formed on the epitaxial layer (1) between the MOS trench (2) and the shield trench (3).

3. Trench MOSFET device according to claim 2, characterized in that the well region (10) is further formed with an active electrode (12) on top of the side of the MOS trench (2) and that the source electrode (12) is located on the side of the gate oxide layer (9) facing away from the MOS gate (5).

4. Trench MOSFET device according to claim 1, characterized in that the thickness d of the gate oxide layer (9) satisfies:

d>Vgs/E；

wherein Vgs is a driving voltage applied to the MOS gate electrode (5), and E is a critical breakdown electric field at which breakdown occurs in the gate oxide layer (9).

5. A trench MOSFET device according to claim 3, characterized in that a top dielectric layer (6) is formed on top surfaces of the gate oxide layer (9) and the source electrode (12), and that the top dielectric layer (6) is also formed on top of the well region (10) on the side close to the shielding trench (3).

6. The trench MOSFET device according to claim 1, characterized in that the shielding trench (3) and the MOS trench (2) further satisfy:

h ₁ >h ₂ ；

wherein h is ₁ Is the thickness of the shielding trench (3) in a direction perpendicular to the substrate (13); h is a ₂ Is the thickness of the MOS trench (2) in a direction perpendicular to the substrate (13).

7. A trench MOSFET device according to claim 3, characterized in that the doping type of the substrate (13), the epitaxial layer (1) and the source electrode (12) is of a first conductivity type; wherein the doping concentration of the substrate (13) and the source electrode (12) is higher than the doping concentration of the epitaxial layer (1).

8. A trench MOSFET device according to claim 2, characterized in that the doping type of the well region (10) is of the second conductivity type.

9. The trench MOSFET device according to claim 1, wherein the epitaxial layer (1) material comprises: silicon, silicon carbide, gallium nitride, gallium oxide, and diamond.

10. The trench MOSFET device of claim 1, comprising a medium-low voltage trench MOSFET device having a suitable voltage in the range of 30V or more.

11. A trench MOSFET device according to claim 3, characterized in that the well region (10) is connected to the source electrode (12) and to ground via a metal line (11).

12. A process for fabricating a trench MOSFET device, suitable for use in a trench MOSFET device according to any one of claims 1 to 11, the process comprising:

growing an epitaxial layer (1) on one side surface of a substrate (13);

etching a plurality of parallel shielding trenches (3) from a side surface of the epitaxial layer (1) away from the substrate (13) into the epitaxial layer (1), and etching a MOS trench (2) between every two adjacent shielding trenches (3);

growing or depositing a thick oxygen layer (7) of the shielding groove on the inner wall of the shielding groove (3) and etching back;

growing or depositing a MOS groove thick oxygen layer (4) on the inner wall of the MOS groove (2) and back etching;

growing or depositing a gate oxide layer (9) on the inner wall of the MOS groove (2) at the top of the MOS groove thick oxide layer (4);

growing or depositing electrodes in the shielding groove thick oxygen layer (7) and the MOS groove thick oxygen layer (4) and back etching to respectively form a shielding electrode (8) in the shielding groove (3) and a MOS grid (5) in the MOS groove (2);

growing or depositing a top dielectric layer (6) on the top surface of the MOS gate (5) and etching back;

ion implanting impurities of a conductivity type different from that of the substrate (13) into the epitaxial layer (1) between the MOS trench (2) and the shielding trench (3) to form a well region (10) inverted to the substrate (13);

doping impurities above the well region (10) close to the MOS groove (2) to form a source electrode (12);

etching the epitaxial layer (1) between the MOS trench (2) and the shielding trench (3) and ion implanting impurities of the same conductivity type as the well region (10) so as to form ohmic contact with metal;

connecting the well region (10), the source electrode (12) and the shielding electrode (8) by using a metal wire (11);

a metal layer is deposited on the lower surface of the substrate (13) to form a drain electrode (14).