CN110459598A - A kind of superjunction MOS type power semiconductor device and preparation method thereof - Google Patents
A kind of superjunction MOS type power semiconductor device and preparation method thereof Download PDFInfo
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Abstract
一种超结MOS型功率半导体器件及其制备方法，属于功率半导体技术领域。本发明提供一种包括多层第一导电类型半导体柱区以及通过异质结作为非平衡载流子势垒的功率半导体器件，实现了电荷平衡效应以及降低了源极一侧的高注入效率，解决了由实际工艺带来的电荷不平衡造成击穿电压降低以及体二极管反向恢复特性恶化的问题，提高了器件的击穿电压以及改善了体二极管的反向恢复特性。此外，本发明还提供了一种超结MOS型功率半导体器件的制备方法，制作工艺简单可控，与现有工艺兼容性强。
A superjunction MOS type power semiconductor device and a preparation method thereof belong to the technical field of power semiconductors. The present invention provides a power semiconductor device including a multi-layer first conductive type semiconductor column region and a heterojunction as an unbalanced carrier potential barrier, which realizes the charge balance effect and reduces the high injection efficiency on the source side, The problems of lower breakdown voltage and deterioration of the reverse recovery characteristic of the body diode caused by the charge imbalance caused by the actual process are solved, the breakdown voltage of the device is increased and the reverse recovery characteristic of the body diode is improved. In addition, the present invention also provides a preparation method of a super-junction MOS type power semiconductor device, the preparation process is simple and controllable, and the compatibility with the existing technology is strong.
Description
技术领域technical field
本发明属于功率半导体技术领域，具体涉及一种超结MOS型功率半导体器件及其制备方法。The invention belongs to the technical field of power semiconductors, and in particular relates to a superjunction MOS type power semiconductor device and a preparation method thereof.
背景技术Background technique
图1示出了一种传统超结金属氧化物半导体场效应晶体管(Super JunctionMetal Oxide Semiconductor Field Effect Transistor，简称SJ-MOSFET)的半元胞结构，SJ-MOSFET作为绝缘栅控制的多子型器件，由于漂移区内具有掺杂类型相反的P型柱区与N型柱区，其带来的电荷平衡效应可以提高器件的击穿电压，但是在实际的工艺过程中，刻蚀P型柱区的过程会呈现出一定的角度，使得刻蚀出的P型柱区沟槽呈梯形，此梯形沟槽会造成P型柱区与N型柱区两边的电荷不平衡，从而减小了器件的击穿电压。此外，由于超结MOSFET的结构特性以及源极一侧的高注入效率，在反向导通过程中会造成漂移区内存储有大量的非平衡载流子，大量的非平衡载流子会增加体二极管反向恢复时间，进而增加关断损耗，使得MOSFET中体二极管反向恢复特性恶化。因此亟需一种新的超结MOS型功率半导体器件，来解决实际工艺带来的电荷不平衡造成击穿电压降低以及体二极管反向恢复特性恶化的问题。Figure 1 shows the half-cell structure of a traditional Super Junction Metal Oxide Semiconductor Field Effect Transistor (SJ-MOSFET for short). SJ-MOSFET is a multi-subtype device controlled by an insulated gate. Since there are P-type pillar regions and N-type pillar regions with opposite doping types in the drift region, the charge balance effect brought by them can improve the breakdown voltage of the device, but in the actual process, etching the P-type pillar region The process will present a certain angle, so that the etched P-type pillar region trench is trapezoidal, which will cause the charge imbalance on both sides of the P-type pillar region and the N-type pillar region, thereby reducing the impact of the device. Breakthrough voltage. In addition, due to the structural characteristics of the superjunction MOSFET and the high injection efficiency on the source side, a large number of unbalanced carriers will be stored in the drift region during the reverse conduction process, and a large number of unbalanced carriers will increase the bulk The diode reverse recovery time, which in turn increases the turn-off loss, deteriorates the reverse recovery characteristics of the body diode in the MOSFET. Therefore, a new superjunction MOS type power semiconductor device is urgently needed to solve the problems of lower breakdown voltage and deterioration of body diode reverse recovery characteristics caused by charge imbalance caused by the actual process.
发明内容SUMMARY OF THE INVENTION
本发明所要解决的技术问题是针对现有技术存在的问题，提供一种超结MOS型功率半导体器件及其制备方法。The technical problem to be solved by the present invention is to provide a super-junction MOS type power semiconductor device and a preparation method thereof, aiming at the problems existing in the prior art.
为解决上述技术问题，本发明提供一种超结MOS型功率半导体器件，包括：金属化漏极、第一导电类型半导体漏区、第一导电类型半导体场阻止层、第二导电类型半导体柱区、第一导电类型半导体第一柱区、第一导电类型半导体第二柱区、第一导电类型半导体第三柱区、第二导电类型半导体基区、第二导电类型半导体层、第一导电类型半导体源区、平面栅结构和源极金属；In order to solve the above technical problems, the present invention provides a superjunction MOS type power semiconductor device, comprising: a metallized drain, a first conductive type semiconductor drain region, a first conductive type semiconductor field stop layer, and a second conductive type semiconductor column region , first conductive type semiconductor first pillar region, first conductive type semiconductor second pillar region, first conductive type semiconductor third pillar region, second conductive type semiconductor base region, second conductive type semiconductor layer, first conductive type semiconductor Semiconductor source region, planar gate structure and source metal;
所述金属化漏极位于所述第一导电类型半导体漏区的下方；所述第一导电类型半导体场阻止层位于所述第一导电类型半导体漏区的上方；the metallized drain is located below the first conductive type semiconductor drain region; the first conductive type semiconductor field stop layer is located above the first conductive type semiconductor drain region;
所述第二导电类型半导体柱区和所述第一导电类型半导体第一柱区位于所述第一导电类型半导体场阻止层上，所述第一导电类型半导体第二柱区和所述第一导电类型半导体第三柱区依次位于所述第一导电类型半导体第一柱区上；所述第二导电类型半导体柱区的侧面与第一导电类型半导体第一柱区、第一导电类型半导体第二柱区和第一导电类型半导体第三柱区的侧面接触；The second conductive type semiconductor pillar region and the first conductive type semiconductor first pillar region are located on the first conductive type semiconductor field stop layer, the first conductive type semiconductor second pillar region and the first conductive type semiconductor field stop layer The third column region of the conductive type semiconductor is sequentially located on the first column region of the first conductive type semiconductor; the side surface of the second conductive type semiconductor column region is connected to the first column region of the first conductive type semiconductor, the first column region of the first conductive type semiconductor and the first column region of the first conductive type semiconductor. The two pillar regions are in contact with the side surfaces of the third pillar region of the first conductive type semiconductor;
所述第二导电类型半导体基区位于所述第二导电类型半导体柱区的上表面及所述第一导电类型半导体第三柱区的侧面；所述第二导电类型半导体层和所述第一导电类型半导体源区并排位于第二导电类型半导体基区上表面的一侧，且侧面相互接触，所述第一导电类型半导体源区和所述第一导电类型半导体第三柱区之间具有第二导电类型半导体基区；the second conductive type semiconductor base region is located on the upper surface of the second conductive type semiconductor pillar region and the side surface of the first conductive type semiconductor third pillar region; the second conductive type semiconductor layer and the first conductive type semiconductor layer The conductive type semiconductor source regions are located side by side on one side of the upper surface of the second conductive type semiconductor base region, and the side surfaces are in contact with each other, and there is a first conductive type semiconductor source region and the first conductive type semiconductor third pillar region. Two-conductivity-type semiconductor base;
平面栅结构位于所述第一导电类型半导体第三柱区、第二导电类型半导体基区和第一导电类型半导体源区的第一部分上；源极金属位于所述第二导电类型半导体层和所述第一导电类型半导体源区的第二部分上；The planar gate structure is located on the first conductive type semiconductor third pillar region, the second conductive type semiconductor base region and the first part of the first conductive type semiconductor source region; the source metal is located on the second conductive type semiconductor layer and the first conductive type semiconductor layer. on the second portion of the first conductive type semiconductor source region;
第二导电类型半导体层所用半导体材料的禁带宽度小于第二导电类型半导体基区和第一导电类型半导体源区所用半导体材料的禁带宽度；第一导电类型半导体第一柱区的掺杂浓度小于第一导电类型半导体第二柱区的掺杂浓度，第一导电类型半导体第二柱区的掺杂浓度小于第一导电类型半导体第三柱区的掺杂浓度。The forbidden band width of the semiconductor material used in the second conductive type semiconductor layer is smaller than the forbidden band width of the semiconductor material used in the second conductive type semiconductor base region and the first conductive type semiconductor source region; the doping concentration of the first conductive type semiconductor first pillar region The doping concentration of the second column region of the first conductive type semiconductor is smaller than the doping concentration of the second column region of the first conductive type semiconductor, and the doping concentration of the second column region of the first conductive type semiconductor is smaller than the doping concentration of the third column region of the first conductive type semiconductor.
为解决上述技术问题，本发明还提供一种超结MOS型功率半导体器件，包括：金属化集电极、第一导电类型半导体集电区、第二导电类型半导体集电区、第一导电类型半导体场阻止层、第二导电类型半导体柱区、第一导电类型半导体第一柱区、第一导电类型半导体第二柱区、第一导电类型半导体第三柱区、第二导电类型半导体基区、第二导电类型半导体层、第一导电类型半导体发射区、平面栅结构和发射极金属；In order to solve the above technical problems, the present invention also provides a superjunction MOS type power semiconductor device, comprising: a metallized collector, a first conductivity type semiconductor collector region, a second conductivity type semiconductor collector region, a first conductivity type semiconductor collector a field stop layer, a second conductive type semiconductor pillar region, a first conductive type semiconductor first pillar region, a first conductive type semiconductor second pillar region, a first conductive type semiconductor third pillar region, a second conductive type semiconductor base region, A second conductivity type semiconductor layer, a first conductivity type semiconductor emitter region, a planar gate structure, and an emitter metal;
第一导电类型半导体集电区和第二导电类型半导体集电区并排设置且侧面相互接触；金属化集电极位于第一导电类型半导体集电区和第二导电类型半导体集电区的下方；第一导电类型半导体场阻止层位于第一导电类型半导体集电区和第二导电类型半导体集电区的上方；The first conductivity type semiconductor collector region and the second conductivity type semiconductor collector region are arranged side by side and the side surfaces are in contact with each other; the metallized collector electrode is located under the first conductivity type semiconductor collector region and the second conductivity type semiconductor collector region; a conductivity type semiconductor field stop layer overlying the first conductivity type semiconductor collector region and the second conductivity type semiconductor collector region;
所述第二导电类型半导体柱区和所述第一导电类型半导体第一柱区位于所述第一导电类型半导体场阻止层上，所述第一导电类型半导体第二柱区和所述第一导电类型半导体第三柱区依次位于所述第一导电类型半导体第一柱区上；所述第二导电类型半导体柱区的侧面与第一导电类型半导体第一柱区、第一导电类型半导体第二柱区和第一导电类型半导体第三柱区的侧面接触；The second conductive type semiconductor pillar region and the first conductive type semiconductor first pillar region are located on the first conductive type semiconductor field stop layer, the first conductive type semiconductor second pillar region and the first conductive type semiconductor field stop layer The third column region of the conductive type semiconductor is sequentially located on the first column region of the first conductive type semiconductor; the side surface of the second conductive type semiconductor column region is connected to the first column region of the first conductive type semiconductor, the first column region of the first conductive type semiconductor and the first column region of the first conductive type semiconductor. The two pillar regions are in contact with the side surfaces of the third pillar region of the first conductive type semiconductor;
所述第二导电类型半导体基区位于所述第二导电类型半导体柱区的上表面及所述第一导电类型半导体第三柱区的侧面；所述第二导电类型半导体层和所述第一导电类型半导体发射区并排位于第二导电类型半导体基区上表面的一侧，且侧面相互接触，所述第一导电类型半导体发射区和所述第一导电类型半导体第三柱区之间具有第二导电类型半导体基区；the second conductive type semiconductor base region is located on the upper surface of the second conductive type semiconductor pillar region and the side surface of the first conductive type semiconductor third pillar region; the second conductive type semiconductor layer and the first conductive type semiconductor layer The conductive type semiconductor emitter regions are located side by side on one side of the upper surface of the second conductive type semiconductor base region, and the side surfaces are in contact with each other, and there is a first conductive type semiconductor emitter region and the first conductive type semiconductor third pillar region. Two-conductivity-type semiconductor base;
平面栅结构位于所述第一导电类型半导体第三柱区、第二导电类型半导体基区和第一导电类型半导体发射区的第一部分上；发射极金属位于所述第二导电类型半导体层和所述第一导电类型半导体发射区的第二部分上；The planar gate structure is located on the first conductive type semiconductor third pillar region, the second conductive type semiconductor base region and the first part of the first conductive type semiconductor emitter region; the emitter metal is located on the second conductive type semiconductor layer and all the on the second portion of the first conductive type semiconductor emitter region;
第二导电类型半导体层所用半导体材料的禁带宽度小于第二导电类型半导体基区和第一导电类型半导体发射区所用半导体材料的禁带宽度；第一导电类型半导体第一柱区的掺杂浓度小于第一导电类型半导体第二柱区的掺杂浓度，第一导电类型半导体第二柱区的掺杂浓度小于第一导电类型半导体第三柱区的掺杂浓度。The forbidden band width of the semiconductor material used in the second conductive type semiconductor layer is smaller than the forbidden band width of the semiconductor material used in the second conductive type semiconductor base region and the first conductive type semiconductor emitter region; the doping concentration of the first conductive type semiconductor first pillar region The doping concentration of the second column region of the first conductive type semiconductor is smaller than the doping concentration of the second column region of the first conductive type semiconductor, and the doping concentration of the second column region of the first conductive type semiconductor is smaller than the doping concentration of the third column region of the first conductive type semiconductor.
在上述技术方案的基础上，本发明还可以做如下改进。On the basis of the above technical solutions, the present invention can also be improved as follows.
进一步的，所述第二导电类型半导体柱区通过多次外延形成，且所述第二导电类型半导体柱区上部的掺杂浓度小于下部的掺杂浓度。Further, the second conductive type semiconductor pillar region is formed by multiple epitaxy, and the doping concentration of the upper part of the second conductive type semiconductor pillar region is lower than the doping concentration of the lower part.
采用上述进一步方案的有益效果是：实现更好的电荷平衡，从而提高击穿电压。The beneficial effect of adopting the above-mentioned further scheme is that better charge balance is achieved, thereby increasing the breakdown voltage.
进一步的，所述第二导电类型半导体柱区通过多次刻蚀再填充杂质形成，且后一次填充的杂质掺杂浓度小于前一次填充的杂质掺杂浓度。Further, the second conductive type semiconductor pillar region is formed by etching multiple times and then filling with impurities, and the impurity doping concentration of the subsequent filling is smaller than the impurity doping concentration of the previous filling.
采用上述进一步方案的有益效果是：实现更好的电荷平衡，从而提高击穿电压。The beneficial effect of adopting the above-mentioned further scheme is that better charge balance is achieved, thereby increasing the breakdown voltage.
进一步的，所述平面栅结构包括栅介质层和设置在栅介质层上的栅电极，栅电极为金属栅电极或者多晶硅栅电极。Further, the planar gate structure includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer, and the gate electrode is a metal gate electrode or a polysilicon gate electrode.
进一步的，所述第一导电类型半导体第一柱区、第一导电类型半导体第二柱区和第一导电类型半导体第三柱区通过外延工艺形成。Further, the first conductive type semiconductor first pillar region, the first conductive type semiconductor second pillar region and the first conductive type semiconductor third pillar region are formed by an epitaxy process.
进一步的，第一导电类型为N型，第二导电类型为P型，或者第二导电类型为P型，第一导电类型为N型。Further, the first conductivity type is N type and the second conductivity type is P type, or the second conductivity type is P type and the first conductivity type is N type.
进一步的，器件所使用的半导体材料为硅、锗硅、砷化镓、碳化硅、氮化镓、三氧化二镓或金刚石。Further, the semiconductor material used in the device is silicon, silicon germanium, gallium arsenide, silicon carbide, gallium nitride, gallium trioxide or diamond.
为解决上述技术问题，本发明实施例还提供一种超结MOS型功率半导体器件的制备方法，包括步骤：In order to solve the above technical problems, an embodiment of the present invention also provides a preparation method of a superjunction MOS type power semiconductor device, comprising the steps of:
选取第一导电类型半导体基片作为器件的第一导电类型半导体漏区，在第一导电类型半导体基片上形成第一导电类型半导体场阻止层；Selecting a first conductive type semiconductor substrate as the first conductive type semiconductor drain region of the device, and forming a first conductive type semiconductor field stop layer on the first conductive type semiconductor substrate;
在第一导电类型半导体场阻止层上方的一侧形成第一导电类型半导体第一柱区，在第一导电类型半导体第一柱区上依次形成第一导电类型半导体第二柱区和第一导电类型半导体第三柱区，第一导电类型半导体第一柱区的掺杂浓度小于第一导电类型半导体第二柱区的掺杂浓度，第一导电类型半导体第二柱区的掺杂浓度小于第一导电类型半导体第三柱区的掺杂浓度；A first conductive type semiconductor first column region is formed on one side above the first conductive type semiconductor field stop layer, and a first conductive type semiconductor second column region and a first conductive column region are sequentially formed on the first conductive type semiconductor first column region Type semiconductor third pillar region, the doping concentration of the first conductive type semiconductor first pillar region is smaller than the doping concentration of the first conductive type semiconductor second pillar region, the doping concentration of the first conductive type semiconductor second pillar region is smaller than the doping concentration of the first conductive type semiconductor second pillar region a doping concentration of the third column region of the conductive type semiconductor;
在第一导电类型半导体场阻止层上方的另一侧形成第二导电类型半导体柱区，所述第二导电类型半导体柱区的侧面与第一导电类型半导体第一柱区、第一导电类型半导体第二柱区和第一导电类型半导体第三柱区的侧面接触；在第二导电类型半导体柱区的上部中形成第二导电类型半导体基区，第二导电类型半导体基区的侧面与第一导电类型半导体第三柱区的侧面接触；A second conductive type semiconductor pillar region is formed on the other side above the first conductive type semiconductor field stop layer, the side surfaces of the second conductive type semiconductor pillar region are connected with the first conductive type semiconductor first pillar region, the first conductive type semiconductor The second pillar region is in contact with the side surface of the first conductive type semiconductor third pillar region; a second conductive type semiconductor base region is formed in the upper portion of the second conductive type semiconductor pillar region, and the side surface of the second conductive type semiconductor base region is in contact with the first conductive type semiconductor base region. the side contact of the third pillar region of the conductive type semiconductor;
在第二导电类型半导体基区的上部一侧形成第一导电类型半导体源区和第二导电类型半导体层；所述第一导电类型半导体源区的侧面和所述第二导电类型半导体层的侧面接触，且所述第一导电类型半导体源区和所述第一导电类型半导体第三柱区之间具有第二导电类型半导体基区；第二导电类型半导体层所用半导体材料的禁带宽度小于第二导电类型半导体基区和第一导电类型半导体源区所用半导体材料的禁带宽度；A first conductive type semiconductor source region and a second conductive type semiconductor layer are formed on the upper side of the second conductive type semiconductor base region; the side surfaces of the first conductive type semiconductor source region and the side surfaces of the second conductive type semiconductor layer contact, and there is a second conductivity type semiconductor base region between the first conductivity type semiconductor source region and the first conductivity type semiconductor third pillar region; the forbidden band width of the semiconductor material used in the second conductivity type semiconductor layer is smaller than the first conductivity type semiconductor layer. The forbidden band width of the semiconductor material used in the two-conductivity-type semiconductor base region and the first-conductivity-type semiconductor source region;
在所述第一导电类型半导体第三柱区上、第二导电类型半导体基区上和第一导电类型半导体源区的第一部分上形成平面栅结构；在所述第二导电类型半导体层上和所述第一导电类型半导体源区的第二部分上形成源极金属；A planar gate structure is formed on the first conductive type semiconductor third pillar region, the second conductive type semiconductor base region and the first portion of the first conductive type semiconductor source region; on the second conductive type semiconductor layer and forming source metal on the second portion of the first conductive type semiconductor source region;
在第一导电类型半导体基片的下方形成金属化漏极。A metallized drain is formed under the first conductivity type semiconductor substrate.
为解决上述技术问题，本发明实施例还提供一种超结MOS型功率半导体器件的制备方法，包括步骤：In order to solve the above technical problems, an embodiment of the present invention also provides a preparation method of a superjunction MOS type power semiconductor device, comprising the steps of:
选取第二导电类型半导体基片作为器件的第二导电类型半导体集电区，在所述第二导电类型半导体基片的上方形成第一导电类型半导体场阻止层；Selecting a second conductive type semiconductor substrate as a second conductive type semiconductor collector region of the device, and forming a first conductive type semiconductor field stop layer on the second conductive type semiconductor substrate;
在第一导电类型半导体场阻止层上方的一侧形成第一导电类型半导体第一柱区，在第一导电类型半导体第一柱区上依次形成第一导电类型半导体第二柱区和第一导电类型半导体第三柱区，第一导电类型半导体第一柱区的掺杂浓度小于第一导电类型半导体第二柱区的掺杂浓度，第一导电类型半导体第二柱区的掺杂浓度小于第一导电类型半导体第三柱区的掺杂浓度；A first conductive type semiconductor first column region is formed on one side above the first conductive type semiconductor field stop layer, and a first conductive type semiconductor second column region and a first conductive column region are sequentially formed on the first conductive type semiconductor first column region Type semiconductor third pillar region, the doping concentration of the first conductive type semiconductor first pillar region is smaller than the doping concentration of the first conductive type semiconductor second pillar region, the doping concentration of the first conductive type semiconductor second pillar region is smaller than the doping concentration of the first conductive type semiconductor second pillar region a doping concentration of the third column region of the conductive type semiconductor;
在第一导电类型半导体场阻止层上方的另一侧形成第二导电类型半导体柱区，所述第二导电类型半导体柱区的侧面与第一导电类型半导体第一柱区、第一导电类型半导体第二柱区和第一导电类型半导体第三柱区的侧面接触；在第二导电类型半导体柱区的上部中形成第二导电类型半导体基区，第二导电类型半导体基区的侧面与第一导电类型半导体第三柱区的侧面接触；A second conductive type semiconductor pillar region is formed on the other side above the first conductive type semiconductor field stop layer, the side surfaces of the second conductive type semiconductor pillar region are connected with the first conductive type semiconductor first pillar region, the first conductive type semiconductor The second pillar region is in contact with the side surface of the first conductive type semiconductor third pillar region; a second conductive type semiconductor base region is formed in the upper portion of the second conductive type semiconductor pillar region, and the side surface of the second conductive type semiconductor base region is in contact with the first conductive type semiconductor base region. the side contact of the third pillar region of the conductive type semiconductor;
在第二导电类型半导体基区的上部一侧形成第一导电类型半导体发射区和第二导电类型半导体层；所述第一导电类型半导体发射区的侧面和所述第二导电类型半导体层的侧面接触，且所述第一导电类型半导体发射区和所述第一导电类型半导体第三柱区之间具有第二导电类型半导体基区；第二导电类型半导体层所用半导体材料的禁带宽度小于第二导电类型半导体基区和第一导电类型半导体发射区所用半导体材料的禁带宽度；A first conductivity type semiconductor emitter region and a second conductivity type semiconductor layer are formed on the upper side of the second conductivity type semiconductor base region; the side surfaces of the first conductivity type semiconductor emitter region and the side surfaces of the second conductivity type semiconductor layer contact, and there is a second conductive type semiconductor base region between the first conductive type semiconductor emitter region and the first conductive type semiconductor third pillar region; the forbidden band width of the semiconductor material used in the second conductive type semiconductor layer is smaller than the first conductive type semiconductor layer. The forbidden band width of the semiconductor material used in the two-conductivity-type semiconductor base region and the first-conductivity-type semiconductor emitter region;
在所述第一导电类型半导体第三柱区上、第二导电类型半导体基区上和第一导电类型半导体发射区的第一部分上形成平面栅结构；在所述第二导电类型半导体层上和所述第一导电类型半导体发射区的第二部分上形成发射极金属；A planar gate structure is formed on the first conductive type semiconductor third pillar region, the second conductive type semiconductor base region and the first portion of the first conductive type semiconductor emitter region; on the second conductive type semiconductor layer and an emitter metal is formed on the second portion of the first conductive type semiconductor emitter region;
在第二导电类型半导体集电区的一侧形成第一导电类型半导体集电区；forming a first conductivity type semiconductor collector region on one side of the second conductivity type semiconductor collector region;
在第二导电类型半导体集电区和第一导电类型半导体集电区的下方形成金属化集电极。A metallized collector is formed under the second conductivity type semiconductor collector region and the first conductivity type semiconductor collector region.
本发明的有益效果是：本发明提供一种包括多层第一导电类型半导体柱区以及通过异质结作为非平衡载流子势垒的超结MOS型功率半导体器件及其制备方法，实现了电荷平衡效应以及降低了源极一侧的高注入效率，解决了由实际工艺带来的电荷不平衡造成击穿电压降低以及体二极管反向恢复特性恶化的问题，提高了器件的击穿电压以及改善了体二极管的反向恢复特性。The beneficial effects of the present invention are as follows: the present invention provides a superjunction MOS type power semiconductor device including a multi-layer first conductive type semiconductor pillar region and a heterojunction as a non-equilibrium carrier barrier and a preparation method thereof, and realizes the The charge balance effect reduces the high injection efficiency on the source side, solves the problem of lower breakdown voltage and deterioration of the reverse recovery characteristics of the body diode caused by the charge imbalance caused by the actual process, and improves the breakdown voltage of the device and Improved body diode reverse recovery characteristics.
附图说明Description of drawings
图1是传统超结MOSFET的半元胞结构示意图；Figure 1 is a schematic diagram of a half-cell structure of a conventional superjunction MOSFET;
图2是本发明第一实施例的超结MOS型功率半导体器件的半元胞结构示意图；2 is a schematic diagram of a half-cell structure of the superjunction MOS type power semiconductor device according to the first embodiment of the present invention;
图3是本发明第二实施例的超结MOS型功率半导体器件的半元胞结构示意图；3 is a schematic diagram of a half-cell structure of a superjunction MOS type power semiconductor device according to a second embodiment of the present invention;
图4是本发明第三实施例的超结MOS型功率半导体器件的半元胞结构示意图；4 is a schematic diagram of a half-cell structure of a superjunction MOS type power semiconductor device according to a third embodiment of the present invention;
图5是本发明第四实施例的超结MOS型功率半导体器件的半元胞结构示意图；5 is a schematic diagram of a half-cell structure of a superjunction MOS type power semiconductor device according to a fourth embodiment of the present invention;
图6是本发明第五实施例的超结MOS型功率半导体器件的半元胞结构示意图；6 is a schematic diagram of a half-cell structure of a superjunction MOS type power semiconductor device according to a fifth embodiment of the present invention;
图7是本发明第六实施例的超结MOS型功率半导体器件的半元胞结构示意图；7 is a schematic diagram of a half-cell structure of a superjunction MOS type power semiconductor device according to a sixth embodiment of the present invention;
图8是形成异质结之后的能带图。FIG. 8 is an energy band diagram after forming a heterojunction.
附图中，各标号所代表的部件列表如下：In the accompanying drawings, the list of components represented by each number is as follows:
1、栅电极，2、栅介质层，3-1、第一导电类型半导体源区，3-2、第一导电类型半导体发射区，4-1、源极金属，4-2、发射极金属，5、第二导电类型半导体层，6、第二导电类型半导体基区，7-1、第二导电类型半导体第一柱区，7-2、第二导电类型半导体第二柱区，7-3、第二导电类型半导体第三柱区，8、第一导电类型半导体场阻止层，9、第一导电类型半导体漏区，10-1、金属化漏极，10-2、金属化集电极，11、第一导电类型半导体柱区，11-1、第一导电类型半导体第一柱区，11-2、第一导电类型半导体第二柱区，11-3、第一导电类型半导体第三柱区，12、第一导电类型半导体集电区，13、第二导电类型半导体集电区。1. Gate electrode, 2. Gate dielectric layer, 3-1, First conductivity type semiconductor source region, 3-2, First conductivity type semiconductor emitter region, 4-1, Source metal, 4-2, Emitter metal , 5, the second conductivity type semiconductor layer, 6, the second conductivity type semiconductor base region, 7-1, the second conductivity type semiconductor first pillar region, 7-2, the second conductivity type semiconductor second pillar region, 7- 3. Second conductivity type semiconductor third pillar region, 8. First conductivity type semiconductor field stop layer, 9. First conductivity type semiconductor drain region, 10-1, Metallized drain, 10-2, Metallized collector , 11, first conductivity type semiconductor pillar region, 11-1, first conductivity type semiconductor first pillar region, 11-2, first conductivity type semiconductor second pillar region, 11-3, first conductivity type semiconductor third Pillar region, 12, first conductivity type semiconductor collector region, 13, second conductivity type semiconductor collector region.
具体实施方式Detailed ways
以下结合附图对本发明的原理和特征进行描述，所举实例只用于解释本发明，并非用于限定本发明的范围。The principles and features of the present invention will be described below with reference to the accompanying drawings. The examples are only used to explain the present invention, but not to limit the scope of the present invention.
如图2所示，本发明第一实施例提供的一种超结MOS型功率半导体器件，包括：金属化漏极10-1、第一导电类型半导体漏区9、第一导电类型半导体场阻止层8、第二导电类型半导体柱区7、第一导电类型半导体第一柱区11-1、第一导电类型半导体第二柱区11-2、第一导电类型半导体第三柱区11-3、第二导电类型半导体基区6、第二导电类型半导体层5、第一导电类型半导体源区3-1、平面栅结构和源极金属4-1；As shown in FIG. 2, a superjunction MOS type power semiconductor device provided by the first embodiment of the present invention includes: a metallized drain 10-1, a first conductivity type semiconductor drain region 9, a first conductivity type semiconductor field stop Layer 8, second conductive type semiconductor pillar region 7, first conductive type semiconductor first pillar region 11-1, first conductive type semiconductor second pillar region 11-2, first conductive type semiconductor third pillar region 11-3 , a second conductive type semiconductor base region 6, a second conductive type semiconductor layer 5, a first conductive type semiconductor source region 3-1, a planar gate structure and a source metal 4-1;
所述金属化漏极10-1位于所述第一导电类型半导体漏区9的下方；所述第一导电类型半导体场阻止层8位于所述第一导电类型半导体漏区9的上方；The metallized drain 10-1 is located below the first conductive type semiconductor drain region 9; the first conductive type semiconductor field stop layer 8 is located above the first conductive type semiconductor drain region 9;
所述第二导电类型半导体柱区7和所述第一导电类型半导体第一柱区11-1位于所述第一导电类型半导体场阻止层8上，所述第一导电类型半导体第二柱区11-2和所述第一导电类型半导体第三柱区11-3依次位于所述第一导电类型半导体第一柱区11-1上；所述第二导电类型半导体柱区7的侧面与第一导电类型半导体第一柱区11-1、第一导电类型半导体第二柱区11-2和第一导电类型半导体第三柱区11-3的侧面接触；The second conductive type semiconductor column region 7 and the first conductive type semiconductor first column region 11-1 are located on the first conductive type semiconductor field stop layer 8, and the first conductive type semiconductor second column region 11-2 and the first conductive type semiconductor third pillar region 11-3 are sequentially located on the first conductive type semiconductor first pillar region 11-1; A conductive type semiconductor first pillar region 11-1, the first conductive type semiconductor second pillar region 11-2 and the first conductive type semiconductor third pillar region 11-3 are in contact with the side surfaces;
所述第二导电类型半导体基区6位于所述第二导电类型半导体柱区7的上表面及所述第一导电类型半导体第三柱区11-3的侧面；所述第二导电类型半导体层5和所述第一导电类型半导体源区3-1并排位于第二导电类型半导体基区6上表面的一侧，且侧面相互接触，所述第一导电类型半导体源区3-1和所述第一导电类型半导体第三柱区11-3之间具有第二导电类型半导体基区6；The second conductive type semiconductor base region 6 is located on the upper surface of the second conductive type semiconductor pillar region 7 and the side surface of the first conductive type semiconductor third pillar region 11-3; the second conductive type semiconductor layer 5 and the first conductive type semiconductor source region 3-1 are located side by side on one side of the upper surface of the second conductive type semiconductor base region 6, and the side surfaces are in contact with each other, the first conductive type semiconductor source region 3-1 and the There is a second conductive type semiconductor base region 6 between the first conductive type semiconductor third pillar regions 11-3;
平面栅结构位于所述第一导电类型半导体第三柱区11-3、第二导电类型半导体基区6和第一导电类型半导体源区3-1的第一部分上；源极金属4-1位于所述第二导电类型半导体层5和所述第一导电类型半导体源区3-1的第二部分上；The planar gate structure is located on the first part of the first conductive type semiconductor third pillar region 11-3, the second conductive type semiconductor base region 6 and the first conductive type semiconductor source region 3-1; the source metal 4-1 is located on on the second conductive type semiconductor layer 5 and the second portion of the first conductive type semiconductor source region 3-1;
第二导电类型半导体层5所用半导体材料的禁带宽度小于第二导电类型半导体基区6和第一导电类型半导体源区3-1所用半导体材料的禁带宽度；第一导电类型半导体第一柱区11-1的掺杂浓度小于第一导电类型半导体第二柱区11-2的掺杂浓度，第一导电类型半导体第二柱区11-2的掺杂浓度小于第一导电类型半导体第三柱区11-3的掺杂浓度。The forbidden band width of the semiconductor material used in the second conductive type semiconductor layer 5 is smaller than the forbidden band width of the semiconductor material used in the second conductive type semiconductor base region 6 and the first conductive type semiconductor source region 3-1; the first conductive type semiconductor first pillar The doping concentration of the region 11-1 is lower than the doping concentration of the first conductive type semiconductor second column region 11-2, and the doping concentration of the first conductive type semiconductor second column region 11-2 is lower than that of the first conductive type semiconductor third column region 11-2. Doping concentration of the pillar region 11-3.
上述实施例中，所述超结MOS型功率半导体器件为超结金属氧化物半导体场效应晶体管，第二导电类型半导体层5的深度可以与第一导电类型半导体源区3-1相同，也可以不同，但其深度小于第二导电类型半导体基区6结深；第二导电类型半导体层5的掺杂浓度可与第二导电类型半导体基区6的掺杂浓度相同或不同，当二者存在掺杂浓度差时可引入非平衡载流子势垒，并通过调整二者掺杂浓度可实现对非平衡载流子势垒高度的调节。第一导电类型半导体柱区11-1、第一导电类型半导体第二柱区11-2和第一导电类型半导体第三柱区11-3的厚度可以相同，也可以不同。第一导电类型半导体源区3-1可以为N+源区。所述平面栅结构包括栅介质层2和设置在栅介质层2上的栅电极1，栅介质层2可以为栅氧化层。In the above embodiment, the superjunction MOS type power semiconductor device is a superjunction metal oxide semiconductor field effect transistor, and the depth of the second conductive type semiconductor layer 5 can be the same as that of the first conductive type semiconductor source region 3-1, or it can be Different, but its depth is smaller than the junction depth of the second conductive type semiconductor base region 6; the doping concentration of the second conductive type semiconductor layer 5 can be the same or different from the doping concentration of the second conductive type semiconductor base region 6, when the two exist When the doping concentration is different, a non-equilibrium carrier barrier can be introduced, and the height of the non-equilibrium carrier barrier can be adjusted by adjusting the doping concentrations of the two. The thicknesses of the first conductive type semiconductor pillar region 11-1, the first conductive type semiconductor second pillar region 11-2 and the first conductive type semiconductor third pillar region 11-3 may be the same or different. The first conductive type semiconductor source region 3-1 may be an N+ source region. The planar gate structure includes a gate dielectric layer 2 and a gate electrode 1 disposed on the gate dielectric layer 2, and the gate dielectric layer 2 may be a gate oxide layer.
本实施例中，第二导电类型半导体基区6的掺杂浓度为5×1016cm-3～2×1017cm-3，深度为0.5～3μm，第二导电类型半导体层5的掺杂浓度为5×1016cm-3～2×1018cm-3，厚度为0.5～1μm；第一导电类型半导体源区3的掺杂浓度为5×1018cm-3～1×1020cm-3，深度为0.2～0.5μm；栅氧化层厚度为20～100nm；多晶硅栅电极1的厚度为0.5～1.5μm；第二导电类型半导体柱区7的掺杂浓度为7×1013cm-3～2×1016cm-3，厚度为10～120μm；第一导电类型半导体场阻止层8的掺杂浓度为5×1015cm-3～1×1017cm-3，厚度为1～5μm；第一导电类型半导体漏区9的掺杂浓度为5×1017cm-3～1×1019cm-3，厚度为0.5～5μm，第一导电类型半导体柱区11-1的掺杂浓度为5×1015cm-3～1×1016cm-3，厚度为3～40μm，第一导电类型半导体第二柱区11-2的掺杂浓度为1×1016cm-3～5×1016cm-3，厚度为3～40μm，第一导电类型半导体第三柱区11-3的掺杂浓度为5×1016cm-3～2×1017cm-3，厚度为3～40μm。In this embodiment, the doping concentration of the second conductive type semiconductor base region 6 is 5×10 16 cm −3 to 2×10 17 cm −3 , the depth is 0.5 to 3 μm, and the doping concentration of the second conductive type semiconductor layer 5 is The concentration is 5×10 16 cm -3 to 2×10 18 cm -3 , and the thickness is 0.5 to 1 μm; the doping concentration of the first conductive type semiconductor source region 3 is 5×10 18 cm -3 to 1×10 20 cm -3 , the depth is 0.2-0.5 μm; the thickness of the gate oxide layer is 20-100 nm; the thickness of the polysilicon gate electrode 1 is 0.5-1.5 μm; the doping concentration of the second conductive type semiconductor pillar region 7 is 7×10 13 cm − 3 to 2×10 16 cm -3 , with a thickness of 10 to 120 μm; the doping concentration of the first conductive type semiconductor field stop layer 8 is 5×10 15 cm -3 to 1×10 17 cm -3 , and the thickness is 1 to 5 μm; the doping concentration of the first conductive type semiconductor drain region 9 is 5×10 17 cm −3 to 1×10 19 cm −3 , the thickness is 0.5 to 5 μm, and the doping concentration of the first conductive type semiconductor pillar region 11-1 is The concentration is 5×10 15 cm -3 to 1×10 16 cm -3 , the thickness is 3 to 40 μm, and the doping concentration of the second column region 11-2 of the first conductive type semiconductor is 1×10 16 cm -3 to 5 ×10 16 cm -3 , the thickness is 3-40 μm, the doping concentration of the first conductive type semiconductor third pillar region 11-3 is 5×10 16 cm -3 ～2×10 17 cm -3 , the thickness is 3～ 40μm.
下面通过N沟道超结MOSFET为例详细说明本发明的原理，在原理说明中将禁带宽度较小的一方称为(相对另一方而言的)窄禁带半导体，同理将禁带宽度较大的一方称为(相对另一方而言的)宽禁带半导体。具体原理如下：The principle of the present invention will be described in detail below by taking N-channel superjunction MOSFET as an example. In the principle description, the one with the smaller forbidden band width is called (relative to the other) narrow band gap semiconductor. The larger one is called (relative to the other) wide bandgap semiconductor. The specific principles are as follows:
所述第一导电类型半导体柱区11为N型柱区，所述第二导电类型半导体柱区7为P型柱区，所述第一导电类型半导体柱区11包括第一导电类型半导体第一柱区11-1、第一导电类型半导体第二柱区11-2和第一导电类型半导体第三柱区11-3，第一导电类型半导体第一柱区11-1的掺杂浓度小于第一导电类型半导体第二柱区11-2的掺杂浓度，第一导电类型半导体第二柱区11-2的掺杂浓度小于第一导电类型半导体第三柱区11-3的掺杂浓度，使得漂移区内的P型柱区和N型柱区在正向阻断过程中实现了电荷平衡，从而提高了器件的击穿电压。The first conductive type semiconductor column region 11 is an N-type column region, the second conductive type semiconductor column region 7 is a P-type column region, and the first conductive type semiconductor column region 11 includes a first conductive type semiconductor first The pillar region 11-1, the first conductive type semiconductor second pillar region 11-2 and the first conductive type semiconductor third pillar region 11-3, the doping concentration of the first conductive type semiconductor first pillar region 11-1 is smaller than that of the first conductive type semiconductor pillar region 11-1. The doping concentration of the first conductive type semiconductor second column region 11-2, the doping concentration of the first conductive type semiconductor second column region 11-2 is smaller than the doping concentration of the first conductive type semiconductor third column region 11-3, The P-type pillar region and the N-type pillar region in the drift region achieve charge balance in the forward blocking process, thereby increasing the breakdown voltage of the device.
第二导电类型半导体层5所用半导体材料的禁带宽度小于第二导电类型半导体基区6和第一导电类型半导体源区3-1所用半导体材料的禁带宽度，使第二导电类型半导体层5与第二导电类型半导体基区6和第一导电类型半导体源区3-1在其接触界面形成异质结；所述第二导电类型半导体层5例如为P型锗硅层，第二导电类型半导体基区6例如为P型硅层，由于P型窄禁带半导体的存在，其与P型宽禁带半导体形成了异质结，当两种半导体材料紧密接触形成异质结时，由于禁带宽度小的半导体材料的费米能级比禁带宽度大的半导体材料的费米能级高，所以电子将从前者流向后者，造成禁带宽度小的半导体其能带向上弯曲，禁带宽度大的半导体其能带则向下弯曲，如图8所示。能带的不连续性使得器件在反向导通模式下有一个空穴势垒，此势垒降低了源极一侧的注入效率，减少了漂移区内部的非平衡载流子数目，减少了关断时间，降低了关断损耗，改善了体二极管的反向恢复特性。The forbidden band width of the semiconductor material used in the second conductive type semiconductor layer 5 is smaller than the forbidden band width of the semiconductor material used in the second conductive type semiconductor base region 6 and the first conductive type semiconductor source region 3-1, so that the second conductive type semiconductor layer 5 A heterojunction is formed at the contact interface with the second conductive type semiconductor base region 6 and the first conductive type semiconductor source region 3-1; the second conductive type semiconductor layer 5 is, for example, a P-type silicon germanium layer, the second conductive type The semiconductor base region 6 is, for example, a P-type silicon layer. Due to the existence of the P-type narrow-bandgap semiconductor, it forms a heterojunction with the P-type wide-bandgap semiconductor. When the two semiconductor materials are in close contact to form a heterojunction, the The Fermi level of a semiconductor material with a small band gap is higher than that of a semiconductor material with a large band gap, so electrons will flow from the former to the latter, causing the energy band of a semiconductor with a small band gap to bend upward, and the band gap The energy band of a semiconductor with a large width is bent downward, as shown in Figure 8. The discontinuity of the energy band makes the device have a hole barrier in the reverse conduction mode, which reduces the injection efficiency on the source side, reduces the number of non-equilibrium carriers in the drift region, and reduces the off-state. The turn-off time is reduced, the turn-off loss is reduced, and the reverse recovery characteristics of the body diode are improved.
如图3所示，本发明第二实施例提供一种超结MOS型功率半导体器件，本实施例是在第一实施例的基础上，通过多次外延形成所述第二导电类型半导体柱区7，多次外延组成的第二导电类型半导体第一柱区7-1、第二导电类型半导体第二柱区7-2和第二导电类型半导体第三柱区7-3掺杂浓度可控，其浓度是渐变的，第二导电类型半导体第一柱区7-1的掺杂浓度大于第二导电类型半导体第二柱区7-2的掺杂浓度，第二导电类型半导体第二柱区7-2的掺杂浓度大于第二导电类型半导体第三柱区7-3的掺杂浓度，从而可以实现更好的电荷平衡，从而提高击穿电压。As shown in FIG. 3 , a second embodiment of the present invention provides a super-junction MOS type power semiconductor device. In this embodiment, the second conductive type semiconductor pillar region is formed by multiple epitaxy on the basis of the first embodiment. 7. The doping concentration of the second conductive type semiconductor first column region 7-1, the second conductive type semiconductor second column region 7-2 and the second conductive type semiconductor third column region 7-3 composed of multiple epitaxy can be controlled , its concentration is graded, the doping concentration of the second conductive type semiconductor first column region 7-1 is greater than the doping concentration of the second conductive type semiconductor second column region 7-2, the second conductive type semiconductor second column region The doping concentration of 7-2 is greater than the doping concentration of the second conductive type semiconductor third pillar region 7-3, so that better charge balance can be achieved, thereby increasing the breakdown voltage.
如图4所示，本发明第三实施例提供一种超结MOS型功率半导体器件，本实施例是在第一实施例的基础上，通过多次刻蚀再填充杂质形成第二导电类型半导体柱区7，多次刻蚀再填充杂质组成的第二导电类型半导体第一柱区7-1、第二导电类型半导体第二柱区7-2、第二导电类型半导体第三柱区7-3的掺杂浓度是渐变的，第二导电类型半导体第一柱区7-1的掺杂浓度大于第二导电类型半导体第二柱区7-2的掺杂浓度，第二导电类型半导体第二柱区7-2的掺杂浓度大于第二导电类型半导体第三柱区7-3的掺杂浓度，从而可以实现更好的电荷平衡，从而提高击穿电压。As shown in FIG. 4 , a third embodiment of the present invention provides a super-junction MOS type power semiconductor device. In this embodiment, on the basis of the first embodiment, a second conductive type semiconductor is formed by multiple etchings and then filling impurities. Column region 7, the second conductive type semiconductor first column region 7-1, the second conductive type semiconductor second column region 7-2, the second conductive type semiconductor third column region 7- The doping concentration of 3 is graded, the doping concentration of the second conductive type semiconductor first column region 7-1 is greater than the doping concentration of the second conductive type semiconductor second column region 7-2, the second conductive type semiconductor second The doping concentration of the pillar region 7-2 is greater than the doping concentration of the second conductive type semiconductor third pillar region 7-3, so that better charge balance can be achieved, thereby increasing the breakdown voltage.
如图5所示，本发明第四实施例提供一种超结MOS型功率半导体器件，金属化集电极10-2、第一导电类型半导体集电区12、第二导电类型半导体集电区13、第一导电类型半导体场阻止层8、第二导电类型半导体柱区7、第一导电类型半导体第一柱区11-1、第一导电类型半导体第二柱区11-2、第一导电类型半导体第三柱区11-3、第二导电类型半导体基区6、第二导电类型半导体层5、第一导电类型半导体发射区3-2、平面栅结构和发射极金属4-2；As shown in FIG. 5 , the fourth embodiment of the present invention provides a superjunction MOS type power semiconductor device, which includes a metallized collector electrode 10 - 2 , a first conductivity type semiconductor collector region 12 , and a second conductivity type semiconductor collector region 13 , the first conductive type semiconductor field stop layer 8, the second conductive type semiconductor column region 7, the first conductive type semiconductor first column region 11-1, the first conductive type semiconductor second column region 11-2, the first conductive type semiconductor column region 11-2 The semiconductor third pillar region 11-3, the second conductivity type semiconductor base region 6, the second conductivity type semiconductor layer 5, the first conductivity type semiconductor emitter region 3-2, the planar gate structure and the emitter metal 4-2;
第一导电类型半导体集电区12和第二导电类型半导体集电区13并排设置且侧面相互接触；金属化集电极10-2位于第一导电类型半导体集电区12和第二导电类型半导体集电区13的下方；第一导电类型半导体场阻止层8位于第一导电类型半导体集电区12和第二导电类型半导体集电区13的上方；The first conductivity type semiconductor collector region 12 and the second conductivity type semiconductor collector region 13 are arranged side by side and their sides are in contact with each other; the metallized collector electrode 10-2 is located in the first conductivity type semiconductor collector region 12 and the second conductivity type semiconductor collector region Below the electrical region 13; the first conductivity type semiconductor field stop layer 8 is located above the first conductivity type semiconductor collector region 12 and the second conductivity type semiconductor collector region 13;
所述第二导电类型半导体柱区7和所述第一导电类型半导体第一柱区11-1位于所述第一导电类型半导体场阻止层8上，所述第一导电类型半导体第二柱区11-2和所述第一导电类型半导体第三柱区11-3依次位于所述第一导电类型半导体第一柱区11-1上；所述第二导电类型半导体柱区7的侧面与第一导电类型半导体第一柱区11-1、第一导电类型半导体第二柱区11-2和第一导电类型半导体第三柱区11-3的侧面接触；The second conductive type semiconductor column region 7 and the first conductive type semiconductor first column region 11-1 are located on the first conductive type semiconductor field stop layer 8, and the first conductive type semiconductor second column region 11-2 and the first conductive type semiconductor third pillar region 11-3 are sequentially located on the first conductive type semiconductor first pillar region 11-1; A conductive type semiconductor first pillar region 11-1, the first conductive type semiconductor second pillar region 11-2 and the first conductive type semiconductor third pillar region 11-3 are in contact with the side surfaces;
所述第二导电类型半导体基区6位于所述第二导电类型半导体柱区7的上表面及所述第一导电类型半导体第三柱区11-3的侧面；所述第二导电类型半导体层5和所述第一导电类型半导体发射区3-2并排位于第二导电类型半导体基区6上表面的一侧，且侧面相互接触，所述第一导电类型半导体发射区3-2和所述第一导电类型半导体第三柱区11-3之间具有第二导电类型半导体基区6；The second conductive type semiconductor base region 6 is located on the upper surface of the second conductive type semiconductor pillar region 7 and the side surface of the first conductive type semiconductor third pillar region 11-3; the second conductive type semiconductor layer 5 and the first conductivity type semiconductor emitter region 3-2 are located side by side on one side of the upper surface of the second conductivity type semiconductor base region 6, and the side surfaces are in contact with each other, the first conductivity type semiconductor emitter region 3-2 and the There is a second conductive type semiconductor base region 6 between the first conductive type semiconductor third pillar regions 11-3;
平面栅结构位于所述第一导电类型半导体第三柱区11-3、第二导电类型半导体基区6和第一导电类型半导体发射区3-2的第一部分上；发射极金属4-2位于所述第二导电类型半导体层5和所述第一导电类型半导体发射区3-2的第二部分上；The planar gate structure is located on the first conductive type semiconductor third pillar region 11-3, the second conductive type semiconductor base region 6 and the first part of the first conductive type semiconductor emitter region 3-2; the emitter metal 4-2 is located on on the second conductive type semiconductor layer 5 and the second part of the first conductive type semiconductor emitter region 3-2;
第二导电类型半导体层5所用半导体材料的禁带宽度小于第二导电类型半导体基区6和第一导电类型半导体发射区3-2所用半导体材料的禁带宽度；第一导电类型半导体第一柱区11-1的掺杂浓度小于第一导电类型半导体第二柱区11-2的掺杂浓度，第一导电类型半导体第二柱区11-2的掺杂浓度小于第一导电类型半导体第三柱区11-3的掺杂浓度。The forbidden band width of the semiconductor material used in the second conductive type semiconductor layer 5 is smaller than the forbidden band width of the semiconductor material used in the second conductive type semiconductor base region 6 and the first conductive type semiconductor emitter region 3-2; the first conductive type semiconductor first column The doping concentration of the region 11-1 is lower than the doping concentration of the first conductive type semiconductor second column region 11-2, and the doping concentration of the first conductive type semiconductor second column region 11-2 is lower than that of the first conductive type semiconductor third column region 11-2. Doping concentration of the pillar region 11-3.
上述实施例中，所述超结MOS型功率半导体器件为超结反向导通绝缘栅双极晶体管，本实施例是在实施例1的基础上，背部引入了第二导电类型半导体集电区13与第一导电类型半导体集电区12，构成了RC-IGBT结构，其作为双极器件，在正向导通时具有电导调制效应，降低了导通压降，同时也具有反向导通能力。所述第一导电类型半导体发射区3-2可以为N+发射区。In the above-mentioned embodiment, the superjunction MOS type power semiconductor device is a superjunction reverse conducting insulated gate bipolar transistor. In this embodiment, on the basis of Embodiment 1, a second conductive type semiconductor collector region 13 is introduced into the back. Together with the first conductive type semiconductor collector region 12 , an RC-IGBT structure is formed, which, as a bipolar device, has a conductance modulation effect during forward conduction, reduces the conduction voltage drop, and also has reverse conduction capability. The first conductive type semiconductor emitter region 3-2 may be an N+ emitter region.
如图6所示，本发明第五实施例提供一种超结MOS型功率半导体器件，本实施例是在第四实施例的基础上，通过多次外延形成所述第二导电类型半导体柱区7，多次外延组成的第二导电类型半导体第一柱区7-1、第二导电类型半导体第二柱区7-2和第二导电类型半导体第三柱区7-3掺杂浓度可控，其浓度是渐变的，第二导电类型半导体第一柱区7-1的掺杂浓度大于第二导电类型半导体第二柱区7-2的掺杂浓度，第二导电类型半导体第二柱区7-2的掺杂浓度大于第二导电类型半导体第三柱区7-3的掺杂浓度，从而可以实现更好的电荷平衡，从而提高击穿电压。As shown in FIG. 6 , a fifth embodiment of the present invention provides a superjunction MOS type power semiconductor device. In this embodiment, the second conductive type semiconductor pillar region is formed by multiple epitaxy on the basis of the fourth embodiment. 7. The doping concentration of the second conductive type semiconductor first column region 7-1, the second conductive type semiconductor second column region 7-2 and the second conductive type semiconductor third column region 7-3 composed of multiple epitaxy can be controlled , its concentration is graded, the doping concentration of the second conductive type semiconductor first column region 7-1 is greater than the doping concentration of the second conductive type semiconductor second column region 7-2, the second conductive type semiconductor second column region The doping concentration of 7-2 is greater than the doping concentration of the second conductive type semiconductor third pillar region 7-3, so that better charge balance can be achieved, thereby increasing the breakdown voltage.
如图7所示，本发明第六实施例提供一种超结MOS型功率半导体器件，本实施例是在第四实施例的基础上，通过多次刻蚀再填充杂质形成第二导电类型半导体柱区7，多次刻蚀再填充杂质组成的第二导电类型半导体第一柱区7-1、第二导电类型半导体第二柱区7-2、第二导电类型半导体第三柱区7-3的掺杂浓度是渐变的，第二导电类型半导体第一柱区7-1的掺杂浓度大于第二导电类型半导体第二柱区7-2的掺杂浓度，第二导电类型半导体第二柱区7-2的掺杂浓度大于第二导电类型半导体第三柱区7-3的掺杂浓度，从而可以实现更好的电荷平衡，从而提高击穿电压。As shown in FIG. 7 , the sixth embodiment of the present invention provides a super-junction MOS type power semiconductor device. In this embodiment, on the basis of the fourth embodiment, a second conductivity type semiconductor is formed by multiple etchings and then filling impurities. Column region 7, the second conductive type semiconductor first column region 7-1, the second conductive type semiconductor second column region 7-2, the second conductive type semiconductor third column region 7- The doping concentration of 3 is graded, the doping concentration of the second conductive type semiconductor first column region 7-1 is greater than the doping concentration of the second conductive type semiconductor second column region 7-2, the second conductive type semiconductor second The doping concentration of the pillar region 7-2 is greater than the doping concentration of the second conductive type semiconductor third pillar region 7-3, so that better charge balance can be achieved, thereby increasing the breakdown voltage.
可选地，所述平面栅结构包括栅介质层2和设置在栅介质层2上的栅电极1，栅电极1为金属栅电极或者多晶硅栅电极。其中栅介质层2的厚度为20～100nm；栅电极1的厚度为0.5～1.5μm。Optionally, the planar gate structure includes a gate dielectric layer 2 and a gate electrode 1 disposed on the gate dielectric layer 2 , and the gate electrode 1 is a metal gate electrode or a polysilicon gate electrode. The thickness of the gate dielectric layer 2 is 20-100 nm; the thickness of the gate electrode 1 is 0.5-1.5 μm.
可选地，所述第一导电类型半导体第一柱区11-1、第一导电类型半导体第二柱区11-2和第一导电类型半导体第三柱区11-3通过外延工艺形成。Optionally, the first conductive type semiconductor first column region 11-1, the first conductive type semiconductor second column region 11-2 and the first conductive type semiconductor third column region 11-3 are formed by an epitaxy process.
可选地，第一导电类型为N型，第二导电类型为P型，或者第二导电类型为P型，第一导电类型为N型。Optionally, the first conductivity type is N-type and the second conductivity type is P-type, or the second conductivity type is P-type and the first conductivity type is N-type.
可选地，器件所使用的半导体材料为硅、锗硅、砷化镓、碳化硅、氮化镓、三氧化二镓或金刚石。Optionally, the semiconductor material used in the device is silicon, silicon germanium, gallium arsenide, silicon carbide, gallium nitride, gallium trioxide or diamond.
本发明第七实施例提供一种超结MOS型功率半导体器件的制备方法，包括步骤：A seventh embodiment of the present invention provides a method for fabricating a superjunction MOS type power semiconductor device, comprising the steps of:
选取第一导电类型半导体基片作为器件的第一导电类型半导体漏区9，在第一导电类型半导体基片上形成第一导电类型半导体场阻止层8；A first conductive type semiconductor substrate is selected as the first conductive type semiconductor drain region 9 of the device, and a first conductive type semiconductor field stop layer 8 is formed on the first conductive type semiconductor substrate;
在第一导电类型半导体场阻止层8上方的一侧形成第一导电类型半导体第一柱区11-1，在第一导电类型半导体第一柱区11-1上依次形成第一导电类型半导体第二柱区11-2和第一导电类型半导体第三柱区11-3，第一导电类型半导体第一柱区11-1的掺杂浓度小于第一导电类型半导体第二柱区11-2的掺杂浓度，第一导电类型半导体第二柱区11-2的掺杂浓度小于第一导电类型半导体第三柱区11-3的掺杂浓度；A first conductive type semiconductor first pillar region 11-1 is formed on one side above the first conductive type semiconductor field stop layer 8, and a first conductive type semiconductor first pillar region 11-1 is sequentially formed on the first conductive type semiconductor first pillar region 11-1. The second pillar region 11-2 and the first conductive type semiconductor third pillar region 11-3, the doping concentration of the first conductive type semiconductor first pillar region 11-1 is lower than that of the first conductive type semiconductor second pillar region 11-2 Doping concentration, the doping concentration of the second column region 11-2 of the first conductive type semiconductor is lower than the doping concentration of the third column region 11-3 of the first conductive type semiconductor;
在第一导电类型半导体场阻止层8上方的另一侧形成第二导电类型半导体柱区7，所述第二导电类型半导体柱区7的侧面与第一导电类型半导体第一柱区11-1、第一导电类型半导体第二柱区11-2和第一导电类型半导体第三柱区11-3的侧面接触；在第二导电类型半导体柱区7的上部中形成第二导电类型半导体基区6，第二导电类型半导体基区6的侧面与第一导电类型半导体第三柱区11-3的侧面接触；A second conductive type semiconductor pillar region 7 is formed on the other side above the first conductive type semiconductor field stop layer 8, and the side surface of the second conductive type semiconductor pillar region 7 is connected to the first conductive type semiconductor first pillar region 11-1. , the side surfaces of the first conductive type semiconductor second pillar region 11-2 and the first conductive type semiconductor third pillar region 11-3 are in contact; a second conductive type semiconductor base region is formed in the upper portion of the second conductive type semiconductor pillar region 7 6. The side surface of the second conductive type semiconductor base region 6 is in contact with the side surface of the first conductive type semiconductor third pillar region 11-3;
在第二导电类型半导体基区6的上部一侧形成第一导电类型半导体源区3-1和第二导电类型半导体层5；所述第一导电类型半导体源区3-1的侧面和所述第二导电类型半导体层5的侧面接触，且所述第一导电类型半导体源区3-1和所述第一导电类型半导体第三柱区11-3之间具有第二导电类型半导体基区6；第二导电类型半导体层5所用半导体材料的禁带宽度小于第二导电类型半导体基区6和第一导电类型半导体源区3-1所用半导体材料的禁带宽度；A first conductive type semiconductor source region 3-1 and a second conductive type semiconductor layer 5 are formed on the upper side of the second conductive type semiconductor base region 6; the side surfaces of the first conductive type semiconductor source region 3-1 and the The side surfaces of the second conductive type semiconductor layer 5 are in contact, and there is a second conductive type semiconductor base region 6 between the first conductive type semiconductor source region 3-1 and the first conductive type semiconductor third pillar region 11-3 ; The forbidden band width of the semiconductor material used in the second conductivity type semiconductor layer 5 is smaller than the forbidden band width of the semiconductor material used in the second conductivity type semiconductor base region 6 and the first conductivity type semiconductor source region 3-1;
在所述第一导电类型半导体第三柱区11-3上、第二导电类型半导体基区6上和第一导电类型半导体源区3-1的第一部分上形成平面栅结构；在所述第二导电类型半导体层5上和所述第一导电类型半导体源区3-1的第二部分上形成源极金属4-1；A planar gate structure is formed on the first conductive type semiconductor third pillar region 11-3, the second conductive type semiconductor base region 6 and the first portion of the first conductive type semiconductor source region 3-1; A source metal 4-1 is formed on the second conductive type semiconductor layer 5 and on the second part of the first conductive type semiconductor source region 3-1;
在第一导电类型半导体基片的下方形成金属化漏极10-1。A metallized drain 10-1 is formed under the first conductivity type semiconductor substrate.
上述实施例中，所述超结MOS型功率半导体器件为超结金属氧化物半导体场效应晶体管，第一导电类型半导体第一柱区11-1通过外延工艺制作；通过刻蚀所述第一导电类型半导体第一柱区11-1、所述第一导电类型半导体第二柱区11-2和所述第一导电类型半导体第三柱区11-3的一侧，形成第一沟槽，并向第一沟槽填充杂质，从而在第一导电类型半导体场阻止层8上方的另一侧形成第二导电类型半导体柱区7；通过向所述第二导电类型半导体柱区7的表面离子注入第二导电类型半导体型杂质，并进行退火处理，形成第二导电类型半导体型基区6；通过向第二导电类型半导体型基区6离子注入第一导电类型半导体型杂质，并进行退火处理，形成第一导电类型半导体源区3-1；通过刻蚀所述第一导电类型半导体源区3左侧的第二导电类型半导体型基区6，形成第二沟槽，并通过沉积和回刻工艺，在第二沟槽中形成第二导电类型半导体层5；通过表面热氧化工艺获得栅介质，并淀积多晶，然后通过刻蚀工艺形成平面栅结构；通过蒸发或溅射工艺获得金属层，然后通过刻蚀工艺形成源极金属4-1和金属化漏极10-1，在形成金属化漏极10-1之前减薄器件厚度。In the above embodiment, the superjunction MOS type power semiconductor device is a superjunction metal oxide semiconductor field effect transistor, and the first column region 11-1 of the first conductive type semiconductor is fabricated by an epitaxial process; type semiconductor first pillar region 11-1, the first conductive type semiconductor second pillar region 11-2 and one side of the first conductive type semiconductor third pillar region 11-3, a first trench is formed, and Fill the first trench with impurities, thereby forming a second conductive type semiconductor pillar region 7 on the other side above the first conductive type semiconductor field stop layer 8; by implanting ions into the surface of the second conductive type semiconductor pillar region 7 The second conductivity type semiconductor type impurity is annealed to form the second conductivity type semiconductor type base region 6; by ion implantation of the first conductivity type semiconductor type impurity into the second conductivity type semiconductor type base region 6, and the annealing treatment is performed, A first conductive type semiconductor source region 3-1 is formed; by etching the second conductive type semiconductor base region 6 on the left side of the first conductive type semiconductor source region 3, a second trench is formed, and by deposition and etch back The second conductive type semiconductor layer 5 is formed in the second trench; the gate dielectric is obtained by the surface thermal oxidation process, polycrystalline is deposited, and then the planar gate structure is formed by the etching process; the metal is obtained by the evaporation or sputtering process layer, and then the source metal 4-1 and the metallized drain 10-1 are formed by an etching process, and the thickness of the device is reduced before the metallized drain 10-1 is formed.
本发明第八实施例提供一种超结MOS型功率半导体器件的制备方法，包括步骤：The eighth embodiment of the present invention provides a method for fabricating a superjunction MOS type power semiconductor device, comprising the steps of:
选取第二导电类型半导体基片作为器件的第二导电类型半导体集电区13，在所述第二导电类型半导体基片的上方形成第一导电类型半导体场阻止层8；A second conductive type semiconductor substrate is selected as the second conductive type semiconductor collector region 13 of the device, and a first conductive type semiconductor field stop layer 8 is formed on the second conductive type semiconductor substrate;
在第一导电类型半导体场阻止层8上方的一侧形成第一导电类型半导体第一柱区11-1，在第一导电类型半导体第一柱区11-1上依次形成第一导电类型半导体第二柱区11-2和第一导电类型半导体第三柱区11-3，第一导电类型半导体第一柱区11-1的掺杂浓度小于第一导电类型半导体第二柱区11-2的掺杂浓度，第一导电类型半导体第二柱区11-2的掺杂浓度小于第一导电类型半导体第三柱区11-3的掺杂浓度；A first conductive type semiconductor first pillar region 11-1 is formed on one side above the first conductive type semiconductor field stop layer 8, and a first conductive type semiconductor first pillar region 11-1 is sequentially formed on the first conductive type semiconductor first pillar region 11-1. The second pillar region 11-2 and the first conductive type semiconductor third pillar region 11-3, the doping concentration of the first conductive type semiconductor first pillar region 11-1 is lower than that of the first conductive type semiconductor second pillar region 11-2 Doping concentration, the doping concentration of the second column region 11-2 of the first conductive type semiconductor is lower than the doping concentration of the third column region 11-3 of the first conductive type semiconductor;
在第一导电类型半导体场阻止层8上方的另一侧形成第二导电类型半导体柱区7，所述第二导电类型半导体柱区7的侧面与第一导电类型半导体第一柱区11-1、第一导电类型半导体第二柱区11-2和第一导电类型半导体第三柱区11-3的侧面接触；在第二导电类型半导体柱区7的上部中形成第二导电类型半导体基区6，第二导电类型半导体基区6的侧面与第一导电类型半导体第三柱区11-3的侧面接触；A second conductive type semiconductor pillar region 7 is formed on the other side above the first conductive type semiconductor field stop layer 8, and the side surface of the second conductive type semiconductor pillar region 7 is connected to the first conductive type semiconductor first pillar region 11-1. , the side surfaces of the first conductive type semiconductor second pillar region 11-2 and the first conductive type semiconductor third pillar region 11-3 are in contact; a second conductive type semiconductor base region is formed in the upper portion of the second conductive type semiconductor pillar region 7 6. The side surface of the second conductive type semiconductor base region 6 is in contact with the side surface of the first conductive type semiconductor third pillar region 11-3;
在第二导电类型半导体基区6的上部一侧形成第一导电类型半导体发射区3-2和第二导电类型半导体层5；所述第一导电类型半导体发射区3-2的侧面和所述第二导电类型半导体层5的侧面接触，且所述第一导电类型半导体发射区3-2和所述第一导电类型半导体第三柱区11-3之间具有第二导电类型半导体基区6；第二导电类型半导体层5所用半导体材料的禁带宽度小于第二导电类型半导体基区6和第一导电类型半导体发射区3-2所用半导体材料的禁带宽度；A first conductivity type semiconductor emitter region 3-2 and a second conductivity type semiconductor layer 5 are formed on the upper side of the second conductivity type semiconductor base region 6; the side surfaces of the first conductivity type semiconductor emitter region 3-2 and the The side surfaces of the second conductive type semiconductor layer 5 are in contact, and there is a second conductive type semiconductor base region 6 between the first conductive type semiconductor emitter region 3-2 and the first conductive type semiconductor third pillar region 11-3 ; The forbidden band width of the semiconductor material used in the second conductivity type semiconductor layer 5 is smaller than the forbidden band width of the semiconductor material used in the second conductivity type semiconductor base region 6 and the first conductivity type semiconductor emitter region 3-2;
在所述第一导电类型半导体第三柱区11-3上、第二导电类型半导体基区6上和第一导电类型半导体发射区3-2的第一部分上形成平面栅结构；在所述第二导电类型半导体层5上和所述第一导电类型半导体发射区3-2的第二部分上形成发射极金属4-2；A planar gate structure is formed on the first conductive type semiconductor third pillar region 11-3, the second conductive type semiconductor base region 6 and the first portion of the first conductive type semiconductor emitter region 3-2; An emitter metal 4-2 is formed on the second conductive type semiconductor layer 5 and the second part of the first conductive type semiconductor emitter region 3-2;
在第二导电类型半导体集电区13的一侧形成第一导电类型半导体集电区12；forming a first conductivity type semiconductor collector region 12 on one side of the second conductivity type semiconductor collector region 13;
在第二导电类型半导体集电区13和第一导电类型半导体集电区12的下方形成金属化集电极10-2。A metallized collector electrode 10 - 2 is formed under the second conductivity type semiconductor collector region 13 and the first conductivity type semiconductor collector region 12 .
上述实施例中，所述超结MOS型功率半导体器件为超结反向导通绝缘栅双极晶体管，本实施例是在实施例七的基础上，背部引入了第二导电类型半导体集电区13与第一导电类型半导体集电区12，构成了RC-IGBT结构，其中，通过离子注入在第二导电类型半导体集电区13的一侧形成第一导电类型半导体集电区12；通过向第二导电类型半导体型基区6离子注入第一导电类型半导体型杂质，并进行退火处理，形成第一导电类型半导体发射区3-2；通过蒸发或溅射工艺获得金属层，然后通过刻蚀工艺形成发射极金属4-2和金属化集电极10-2，在形成金属化集电极10-2之前减薄器件厚度。In the above embodiment, the superjunction MOS type power semiconductor device is a superjunction reverse conducting insulated gate bipolar transistor. In this embodiment, on the basis of the seventh embodiment, a second conductive type semiconductor collector region 13 is introduced into the back. With the first conductivity type semiconductor collector region 12, an RC-IGBT structure is formed, in which the first conductivity type semiconductor collector region 12 is formed on one side of the second conductivity type semiconductor collector region 13 by ion implantation; The second conductivity type semiconductor type base region 6 is ion-implanted with first conductivity type semiconductor type impurities, and annealed to form the first conductivity type semiconductor emitter region 3-2; the metal layer is obtained by an evaporation or sputtering process, and then an etching process is performed Emitter metal 4-2 and metallized collector 10-2 are formed, and the device thickness is reduced prior to forming metallized collector 10-2.
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本发明的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature delimited with "first", "second" may expressly or implicitly include at least one of that feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise expressly and specifically defined.
在本发明中，除非另有明确的规定和限定，第一特征在第二特征“上”或“下”可以是第一和第二特征直接接触，或第一和第二特征通过中间媒介间接接触。而且，第一特征在第二特征“之上”、“上方”和“上面”可是第一特征在第二特征正上方或斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”可以是第一特征在第二特征正下方或斜下方，或仅仅表示第一特征水平高度小于第二特征。In the present invention, unless otherwise expressly specified and limited, a first feature "on" or "under" a second feature may be in direct contact between the first and second features, or the first and second features indirectly through an intermediary touch. Also, the first feature being "above", "over" and "above" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is level higher than the second feature. The first feature being "below", "below" and "below" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature has a lower level than the second feature.
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。In the description of this specification, description with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples", etc., mean specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine the different embodiments or examples described in this specification, as well as the features of the different embodiments or examples, without conflicting each other.
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection of the present invention. within the range.
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| CN111293177A (en) * | 2020-02-28 | 2020-06-16 | 电子科技大学 | Power semiconductor device |
| CN112635544A (en) * | 2020-12-18 | 2021-04-09 | 华南师范大学 | Enhanced AlGaN-GaN vertical super-junction HEMT with dipole layer and preparation method thereof |
| CN113540205A (en) * | 2020-04-13 | 2021-10-22 | 上海新微技术研发中心有限公司 | Semiconductor device structure |
| CN113540204A (en) * | 2020-04-13 | 2021-10-22 | 上海新微技术研发中心有限公司 | Preparation method of semiconductor device structure |
| CN114256331A (en) * | 2021-12-22 | 2022-03-29 | 电子科技大学 | Super-junction reverse-conducting IGBT with heterojunction |
| CN114823531A (en) * | 2022-06-24 | 2022-07-29 | 北京芯可鉴科技有限公司 | Manufacturing method of super junction device, super junction device, chip and circuit |
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| CN114823531A (en) * | 2022-06-24 | 2022-07-29 | 北京芯可鉴科技有限公司 | Manufacturing method of super junction device, super junction device, chip and circuit |
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Application publication date: 20191115 |