CN117171097A

CN117171097A - Remote loading method and system for field programmable gate array

Info

Publication number: CN117171097A
Application number: CN202311117661.8A
Authority: CN
Inventors: 袁晓飞; 赵青云
Original assignee: Yusur Technology Co ltd
Current assignee: Yusur Technology Co ltd
Priority date: 2023-08-31
Filing date: 2023-08-31
Publication date: 2023-12-05

Abstract

The application provides a remote loading method and device for a field programmable gate array, comprising the following steps: the field programmable gate array receives a data packet which is sent by the host and contains configuration information, and converts the data packet into a binary file by utilizing an internal preset code; analyzing and splitting the binary file through a preset bus protocol, writing one path of analysis data into a register, and transmitting the other path of analysis data to pins of a serial peripheral interface; writing the analysis data at the serial peripheral interface pins into the flash memory by using a preset control module, and performing read-back verification on the written analysis data; under the condition of passing the verification, resetting and restarting the field programmable gate array, and loading the analysis data in the flash memory to the field programmable gate array to realize remote online loading. The field programmable gate array remote loading method provided by the application can realize on-line remote loading and starting, has high loading speed and starting speed, and can meet higher requirements.

Description

Remote loading method and system for field programmable gate array

Technical Field

The application relates to the technical field of remote upgrading, in particular to a field programmable gate array remote loading method and a field programmable gate array remote loading system.

Background

Remote upgrade generally refers to loading a program or firmware into a target device remotely using a host computer or server via a network or other communication means without physically contacting the target device, in a field programmable gate array (Field Programmable GateArray ), remote upgrade refers to loading the field programmable gate array locally with a JTAG port, and remotely loading the program or firmware into the field programmable gate array via the host computer.

The existing remote upgrading scheme is to connect a computer (PC) with a field programmable gate array through an Ethernet, and the Ethernet is used as a transmission path, so that the Ethernet provides a quick and reliable network communication mode, the method can be used for transmitting data between the PC and the field programmable gate array, the PC packages a bin file to be transmitted into a data packet, the data packet is transmitted to the field programmable gate array through the Ethernet, and the field programmable gate array analyzes and processes the received data packet to realize remote reconfiguration or upgrading. Wherein a bin file is a binary file format, typically used to store a computer program, firmware, or other binary data. Which contains binary data consisting of 0 and 1, can be directly read and executed by a computer.

The existing remote upgrade scheme provides a flexible and convenient way to update the embedded device based on the performance of the ethernet without directly physically accessing the target device, and although the ethernet can provide a high bandwidth and low latency communication channel, when there is a high demand for fast loading and starting, such as transmitting a large volume of a bin file, it still takes a long time, and the required speed requirement cannot be met.

Disclosure of Invention

In view of this, the embodiment of the application provides a method and a system for remote loading of a field programmable gate array, so as to eliminate or improve one or more defects existing in the prior art, and solve the problem that the existing remote upgrading scheme is slow in transmission rate and cannot meet the requirements of quick loading and starting.

In one aspect, the present application provides a method for remotely loading a field programmable gate array, wherein the method is performed in a field programmable gate array, the field programmable gate array is connected to a host through an expansion bus, and the field programmable gate array is connected to a flash memory through a serial peripheral interface, the method comprises the following steps:

receiving a data packet sent by the host, and converting the data packet into a binary file by utilizing an internal preset code;

analyzing the binary file through a preset bus protocol, writing analysis data into a register of the field programmable gate array, and simultaneously transmitting the analysis data to a pin of the serial peripheral interface;

writing the analysis data at the serial peripheral interface pin into the flash memory, and performing read-back verification on the written analysis data;

and under the condition of passing the verification, resetting and restarting the field programmable gate array, and receiving the analysis data in the flash memory to realize the remote loading of the field programmable gate array.

In some embodiments of the present application, receiving the data packet sent by the host further includes:

the host writes the data packet into a base address register space of the expansion bus;

the base register space is written into the field programmable gate array according to the serial peripheral interface time sequence.

In some embodiments of the present application, the parsing the binary file through a preset bus protocol further includes:

and analyzing the binary file through an AXI bus, performing shunting treatment, writing one path into the register, and transmitting the other path to a pin of the serial peripheral interface so as to write into the flash memory.

In some embodiments of the application, the parsed data includes flash erase instructions and configuration information.

In some embodiments of the present application, writing the parsed data at the serial peripheral interface pins to the flash memory further comprises:

writing the memory erasing instruction into the flash memory, and erasing original data by the flash memory according to the flash memory erasing instruction;

and writing the configuration information into the flash memory.

In some embodiments of the present application, read-back verification is performed on the written parsed data using a cyclic redundancy check method.

In some embodiments of the present application, in the case of passing the verification, resetting and restarting the field programmable gate array, receiving the resolved data in the flash memory to realize remote loading of the field programmable gate array, and further including:

setting a reset pin of the field programmable gate array at a low level to reset and restart the field programmable gate array;

and placing a control pin of the field programmable gate array at a preset logic level so that the field programmable gate array receives the analysis data in the flash memory.

In another aspect, the present application provides a field programmable gate array remote loading system, comprising:

the host is used for sending a data packet containing configuration information to the field programmable gate array;

a field programmable gate array, being a remotely loaded target device, for performing the steps of the field programmable gate array remote loading method according to any one of claims 1 to 7; the field programmable gate array is connected with the host through an expansion bus;

the flash memory is used for storing configuration information and loading the configuration information to the field programmable gate array; the field programmable gate array is connected with the flash memory through a serial peripheral interface.

In some embodiments of the application, the field programmable gate array includes a register, a flash control module, and a start-up module;

the flash memory control module is used for communicating with the flash memory and controlling the erasure, downloading and verification of the flash memory;

the starting module is provided with a state machine, and the configuration information of the designated address is automatically loaded to the field programmable gate array through the state machine, so that the reconfiguration of the field programmable gate array is realized.

In another aspect, the application also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the field programmable gate array remote loading method as defined in any one of the above mentioned.

The application has the advantages that:

the application provides a remote loading method and device for a field programmable gate array, comprising the following steps: the field programmable gate array receives a data packet which is sent by the host and contains configuration information, and converts the data packet into a binary file by utilizing an internal preset code; analyzing and splitting the binary file through a preset bus protocol, writing one path of analysis data into a register, and transmitting the other path of analysis data to pins of a serial peripheral interface; writing the analysis data at the serial peripheral interface pins into the flash memory by using a preset control module, and performing read-back verification on the written analysis data; under the condition of passing the verification, resetting and restarting the field programmable gate array, and loading the analysis data in the flash memory to the field programmable gate array to realize remote online loading. The field programmable gate array remote loading method provided by the application can realize on-line remote loading and starting, has high loading speed and starting speed, can meet higher requirements, and is suitable for more complex application scenes.

Additional advantages, objects, and features of the application will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.

It will be appreciated by those skilled in the art that the objects and advantages that can be achieved with the present application are not limited to the above-described specific ones, and that the above and other objects that can be achieved with the present application will be more clearly understood from the following detailed description.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate and together with the description serve to explain the application. In the drawings:

FIG. 1 is a schematic diagram showing steps of a method for remote loading of a field programmable gate array according to an embodiment of the application.

FIG. 2 is a schematic diagram of a field programmable gate array remote loading system according to an embodiment of the application.

Detailed Description

The present application will be described in further detail with reference to the following embodiments and the accompanying drawings, in order to make the objects, technical solutions and advantages of the present application more apparent. The exemplary embodiments of the present application and the descriptions thereof are used herein to explain the present application, but are not intended to limit the application.

It should be noted here that, in order to avoid obscuring the present application due to unnecessary details, only structures and/or processing steps closely related to the solution according to the present application are shown in the drawings, while other details not greatly related to the present application are omitted.

It should be emphasized that the term "comprises/comprising" when used herein is taken to specify the presence of stated features, elements, steps or components, but does not preclude the presence or addition of one or more other features, elements, steps or components.

It is also noted herein that the term "coupled" may refer to not only a direct connection, but also an indirect connection in which an intermediate is present, unless otherwise specified.

Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. In the drawings, the same reference numerals represent the same or similar components, or the same or similar steps.

It should be emphasized that the references to steps below are not intended to limit the order of the steps, but rather should be understood to mean that the steps may be performed in a different order than in the embodiments, or that several steps may be performed simultaneously.

In order to solve the problem that the existing remote upgrading scheme is low in transmission rate and cannot meet the requirements of quick loading and starting, the application provides a field programmable gate array remote loading method which is implemented in a Field Programmable Gate Array (FPGA), wherein the FPGA is connected with a host through an expansion bus, and the FPGA is connected with a flash memory through a serial peripheral interface. Illustratively, in the present application the expansion bus is Peripheral Component Interconnect Express (PCIe) and the serial peripheral interface is Serial Peripheral Interface (SPI). It should be noted that, the FPGA and the host may be connected by other connection methods, such as ethernet, serial port, etc.

As shown in fig. 1, the method includes the following steps S101 to S104:

step S101: and receiving the data packet sent by the host computer, and converting the data packet into a binary file by utilizing an internal preset code.

Step S102: and analyzing the binary file through a preset bus protocol, writing the analyzed data into a register of the field programmable gate array, and transmitting the analyzed data to pins of the serial peripheral interface.

Step S103: and writing the analysis data at the serial peripheral interface pin into the flash memory, and performing readback verification on the written analysis data.

Step S104: under the condition of passing the verification, resetting and restarting the field programmable gate array, and receiving the analysis data in the flash memory to realize the remote loading of the field programmable gate array.

In step S101, when loading configuration work, a software module in the host writes a data packet containing configuration information to the field programmable gate array.

In some embodiments, a software module within the host writes the data packet into a base register (BaseAddress Register, BAR) space of an expansion bus (e.g., PCIe), then transfers the data packet from the base register space to the field programmable gate array, writes the data packet to the field programmable gate array at Serial Peripheral Interface (SPI) timing, writes the data packet to a register of the field programmable gate array in a manner equivalent to writing the data packet directly to a Flash Memory (Flash Memory) through the SPI, the Flash Memory being a non-volatile Memory for maintaining data storage after power down.

Wherein the BAR is a memory area on the PCIe device, the field programmable gate array is allocated by the host as a communication interface, and the host can write data into the BAR space using specific commands and addresses, where the data may be control information, configuration information, or actual data that needs to be transferred to the field programmable gate array.

The field programmable gate array converts the written data packets into binary, bin files, illustratively 256 bytes per packet of data, using an internal preset code. A bin file is a binary file containing data encoded in binary form, typically used to store low-level data or firmware information for computer systems and devices, and is used in the present application to store configuration information.

In step S102, the binary file is parsed by a preset bus protocol in the field programmable gate array, and the parsed data is written into a register of the field programmable gate array and transmitted to pins of the serial peripheral interface.

In some embodiments, the bus protocol is an AXI bus. And configuring an AXI interface module in the field programmable gate array, selecting proper AXI version and parameters according to actual requirements and the field programmable gate array platform, and realizing an AXI interface by using an IP core provided by a field programmable gate array development tool or writing interface codes by oneself. Binary data is read over the AXI bus and formatted as required by the AXI bus protocol, e.g., sequential byte data may be combined into higher level data structures, such as structures or arrays, which are sent over the AXI bus interface to the field programmable gate array.

In some embodiments, the parsed data is split, written into registers all the way, and transferred to pins of the serial peripheral interface all the way, so that the data can be sent to an external device, i.e., to the flash memory, through the serial peripheral interface. Specifically, a shunt logic module is designed in advance, and is mainly used for receiving and copying the analysis data to a plurality of targets, and the shunt logic module can be implemented by using a multiplexer, a frequency divider or other circuit elements.

In some embodiments, the timing and conditions of the diversion may also be set by using conditional statements, state machines, or configuration registers, etc., depending on design requirements.

In step S103, the parsing data at the serial peripheral interface pin is written into the flash memory, and the read-back verification is performed on the written parsing data.

In some embodiments, the parsed data includes flash erase instructions and configuration information. Therefore, when the analysis data is written into the flash memory, the original data in the flash memory is firstly erased according to the flash memory erasing instruction, and then the configuration information is written into the flash memory.

After the analysis data are written into the flash memory, read-back verification (readbacking verification) is performed on the data in the flash memory. The read-back verification is an important step in the field programmable gate array programming process for verifying that the configuration data is properly written to the field programmable gate array chip.

In some embodiments, a cyclic redundancy check method (Cyclic Redundancy Check, CRC) is employed for read-back checking. The verification comprises the following steps:

CRC algorithms are determined, and exemplary, common CRC algorithms include CRC-16, CRC-32, and the like.

The CRC check value is calculated using the selected CRC algorithm with the raw parsed data as input.

And configuring the designed logic circuit into the field programmable gate array by using a preset programming tool, waiting for the field programmable gate array to finish the configuration process, and ensuring that the internal logic circuit is successfully loaded and initialized.

Configuration data is read from the field programmable gate array and stored as readback data.

The read-back data is used as input and the same CRC algorithm is used to calculate the CRC check value.

Comparing the calculated CRC check value of the read-back data with the CRC check value of the original analysis data, and if the two CRC check values are completely consistent, indicating that the configuration data is correctly written into the field programmable gate array chip. Otherwise, there may be configuration errors or transmission problems, requiring further inspection and debugging.

In step S104, under the condition of passing the verification, resetting and restarting the field programmable gate array, and receiving the analysis data in the flash memory to realize remote loading of the field programmable gate array.

In some embodiments, if the read-back check of step S103 fails, a storage error is prompted. Illustratively, when the verification fails, the following measures are generally taken:

(1) The interface between the field programmable gate array and the flash memory is checked to ensure that the physical connection is reliable.

(2) The write operation is attempted again, ensuring that the correct data is written to the flash memory.

(3) Check if the checking algorithm and data format are correct.

(4) The flash memory chip or the field programmable gate array is replaced.

In some embodiments, the reset pin of the field programmable gate array may be set to a low level to cause the field programmable gate array to reset and restart, and the control pin of the field programmable gate array may be set to a preset logic level to cause the field programmable gate array to receive the parsed data within the flash memory. Here, the logic level of the reset pin is preset: the reset restarting operation of the field programmable gate array is triggered by setting a low level, and the logic level setting can be adjusted according to actual conditions.

After the reset and restart of the field programmable gate array, the flash memory provides the pre-stored configuration information, and the configuration information is transmitted to the configuration logic in the field programmable gate array through the SPI interface. The configuration logic of the field programmable gate array is initialized and configured according to the configuration information to ensure that the field programmable gate array operates in a desired mode, and finally remote online loading is realized.

In some embodiments, reconfiguring a field programmable gate array by a state machine includes the steps of:

the state machine is pre-designed on the field programmable gate array, and states of the state machine, such as standby state, read configuration data state, configure field programmable gate array state, etc., are defined. The state machine may be written using a hardware description language (e.g., verilog or VHDL).

According to the current state, the analysis data (configuration information) stored in the flash memory is read through the SPI.

And loading the read configuration information into the field programmable gate array.

And updating the state of the state machine according to the current state and the result of loading the configuration information.

When the state machine completes the configuration process, the field programmable gate array will be in a reconfigured state, i.e., the designed logic circuit will begin to operate.

The application also provides a field programmable gate array remote loading system, as shown in fig. 2, comprising a host, a field programmable gate array and a flash memory, in particular:

the host is internally provided with a software module, generates a data packet containing configuration information through the software module, and sends the data packet to a Field Programmable Gate Array (FPGA).

The field programmable gate array is a remotely loaded target device for performing the steps of the field programmable gate array remote loading method described above. The field programmable gate array is connected to the host via an expansion bus (PCIe).

The flash memory is used for storing configuration information and loading the configuration information into the field programmable gate array. The field programmable gate array is connected with the flash memory through a Serial Peripheral Interface (SPI).

In some embodiments, the field programmable gate array further includes a register, a flash control module, and a start-up module.

The register is used for storing analysis data obtained by analyzing the field programmable gate array.

The flash memory control module is used for communicating with the flash memory and controlling operations such as erasing, downloading and checking of the flash memory. The flash memory control module can be a logic circuit in the field programmable gate array or an external controller, and is responsible for managing the read-write and configuration process of the flash memory. Specific:

reading: the flash memory control module is responsible for reading data from the flash memory. It will send a read command and address and receive the data returned by the flash memory. Read operations are typically used to load configuration information or other stored information from flash memory.

Writing: the data can be written into the flash memory through the flash memory control module. It will send write instructions, addresses and data and ensure that the data is written correctly into the flash memory. Write operations are typically used to store configuration information and other information that needs to be preserved.

And (3) erasure: the flash control module may perform an erase operation when it is necessary to reconfigure the field programmable gate array or erase stored data. It will send an erase command and address to erase the designated memory area to the initial state. An erase operation typically erases an entire sector or block, rather than a single byte or page.

And (3) checking: to ensure the integrity and correctness of the data, the flash control module may perform a verification operation. It reads the stored data and uses a verification algorithm (e.g., CRC) to calculate and compare to verify that the data is consistent. The verify operation may be performed before writing or after reading.

In some embodiments, the starting module is further provided with a state machine, and configuration information of the designated address is automatically loaded to the field programmable gate array through the state machine, so that reconfiguration of the field programmable gate array is realized.

The present application also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of a field programmable gate array remote loading method.

Accordingly, the present application also provides an apparatus comprising a computer apparatus including a processor and a memory, the memory having stored therein computer instructions for executing the computer instructions stored in the memory, the apparatus implementing the steps of the method as described above when the computer instructions are executed by the processor.

The embodiments of the present application also provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the edge computing server deployment method described above. The computer readable storage medium may be a tangible storage medium such as Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, floppy disks, hard disk, a removable memory disk, a CD-ROM, or any other form of storage medium known in the art.

In summary, the present application provides a method and an apparatus for remote loading of a field programmable gate array, including: the field programmable gate array receives a data packet which is sent by the host and contains configuration information, and converts the data packet into a binary file by utilizing an internal preset code; analyzing and splitting the binary file through a preset bus protocol, writing one path of analysis data into a register, and transmitting the other path of analysis data to pins of a serial peripheral interface; writing the analysis data at the serial peripheral interface pin into the flash memory, and performing read-back verification on the written analysis data; under the condition of passing the verification, resetting and restarting the field programmable gate array, and loading the analysis data in the flash memory to the field programmable gate array to realize remote online loading. The field programmable gate array remote loading method provided by the application can realize on-line remote loading and starting, has high loading speed and starting speed, can meet higher requirements, and is suitable for more complex application scenes.

Those of ordinary skill in the art will appreciate that the various illustrative components, systems, and methods described in connection with the embodiments disclosed herein can be implemented as hardware, software, or a combination of both. The particular implementation is hardware or software dependent on the specific application of the solution and the design constraints. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, a plug-in, a function card, or the like. When implemented in software, the elements of the application are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine readable medium or transmitted over transmission media or communication links by a data signal carried in a carrier wave.

It should be understood that the application is not limited to the particular arrangements and instrumentality described above and shown in the drawings. For the sake of brevity, a detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between steps, after appreciating the spirit of the present application.

In this disclosure, features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments and/or in combination with or instead of the features of the other embodiments.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, and various modifications and variations can be made to the embodiments of the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A method for remotely loading a field programmable gate array, the method being performed in a field programmable gate array, the field programmable gate array being coupled to a host via an expansion bus, the field programmable gate array being coupled to a flash memory via a serial peripheral interface, the method comprising the steps of:

2. The field programmable gate array remote loading method of claim 1, wherein receiving the data packet sent by the host further comprises:

3. The method for remote loading of a field programmable gate array according to claim 1, wherein the parsing of the binary file by a preset bus protocol further comprises:

4. The field programmable gate array remote loading method of claim 1, wherein the parsed data includes flash erase instructions and configuration information.

5. The field programmable gate array remote loading method of claim 4, wherein writing the parsed data at the serial peripheral interface pins to the flash memory, further comprises:

and writing the configuration information into the flash memory.

6. The field programmable gate array remote loading method of claim 1, wherein the written analytical data is read-back checked by a cyclic redundancy check method.

7. The method for remotely loading a field programmable gate array according to claim 1, wherein in the case of passing the verification, resetting and restarting the field programmable gate array, receiving the analysis data in the flash memory to realize remote loading of the field programmable gate array, further comprising:

8. A field programmable gate array remote loading system, comprising:

9. The field programmable gate array remote loading system of claim 8, wherein the field programmable gate array comprises a register, a flash control module, and a startup module;

10. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the steps of the method according to any one of claims 1 to 7.