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CN114237122B - Circuit and operation method for configuring, reading back and refreshing SRAM type FPGA - Google Patents

Circuit and operation method for configuring, reading back and refreshing SRAM type FPGA Download PDF

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Publication number
CN114237122B
CN114237122B CN202111550030.6A CN202111550030A CN114237122B CN 114237122 B CN114237122 B CN 114237122B CN 202111550030 A CN202111550030 A CN 202111550030A CN 114237122 B CN114237122 B CN 114237122B
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fpga
data
serial port
interface module
controller
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CN114237122A (en
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请求不公布姓名
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Hefei Tengxin Microelectronics Co ltd
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Hefei Tengxin Microelectronics Co ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/25—Pc structure of the system
    • G05B2219/25257—Microcontroller
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The invention discloses a circuit for configuring, reading back and refreshing SRAM type FPGA, comprising: the system comprises a storage controller, a serial port module, a data path, an FPGA interface module, a state machine and a configuration register; the storage controller reads the data in the storage and sends the data to the serial port module or the FPGA interface module through a data channel; the serial port module is in bidirectional communication connection with the upper computer; the FPGA interface module receives data in the memory or data of the serial port module through a data path, and configures, reads back and refreshes the FPGA; the circuit can detect and update the code allocation errors in the SRAM type FPGA chip, and enhances the adaptability of the FPGA to severe environments. The circuit adopts the serial port module to receive the information of the upper computer, can work according to a default preset flow after being electrified, and can monitor the working state of the circuit and set and adjust the working mode through the serial port module.

Description

Circuit and operation method for configuring, reading back and refreshing SRAM type FPGA
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a circuit and an operation method for configuring, reading back and refreshing an SRAM type FPGA.
Background
The FPGA is a field programmable gate array, which is a general-purpose integrated circuit parallel to a CPU and a DSP. The FPGA chip comprises time sequence logic, combination logic, wiring resources, a memory array, an operation logic array, a clock network, IO logic and other resources, and a user can call the resources in the FPGA chip through a graphical design mode or a Hardware Description Language (HDL) design input mode so as to build various digital circuits.
After the user finishes the development design of the FPGA function, the circuit design is required to be converted into a binary code stream, and the code stream only comprises 0 and 1 digital combinations, and the different digital combination modes determine the circuit structure in the FPGA chip. Since the function of an FPGA is determined by the code stream, if the FPGA is expected to perform the intended function, the code stream is first transferred into the FPGA, a process called "Configuration".
Within the FPGA chip, there is a specialized memory array for storing the configuration code stream. Most FPGAs employ SRAM arrays to hold the configuration, referred to as "configuration SRAM", configuration SRAM. Some FPGAs also use nonvolatile memory techniques such as Flash to store the code stream, but these FPGAs have smaller general capacity and limited use.
The FPGA which is configured by adopting the SRAM in the chip is called as SRAM type FPGA, the capacity and the speed are high, and the main stream of high-performance circuit application scenes are all the FPGA of the type. However, SRAM type FPGAs have a disadvantage: when the FPGA is applied to a severe environment such as an irradiation environment, a satellite, etc., SRAM memory cells in its Configuration SRAM array are susceptible to charged particles, and are erroneously flipped, and 0,1 data are erroneous, thus causing the user circuit function of the FPGA to be erroneous.
The circuitry to configure an FPGA is a well known technology in the art: one typical method is JTAG download read back: and transmitting the code stream to the FPGA from the upper computer through the downloading line of the USB interface and the JTAG interface and carrying out readback comparison. The method can realize configuration and readback of the FPGA, but has the defect that configuration information is lost when power is lost, and is only suitable for debugging and cannot be used for field deployment of products and equipment. The other method is as follows: the configuration loading method has the advantages that the PROM can store configuration data in a nonvolatile mode when the FPGA is powered on, and the configuration loading method can be deployed in an actual product because an upper computer is not needed in a working state, but has the defects that the configuration loading method only can be used for powering on the FPGA, and the configuration of the FPGA cannot be read back, compared and refreshed.
Through retrieval, chinese patent publication No. CN202011191407.9 discloses a method and a device for dynamically refreshing configuration data of an SRAM type FPGA, and the patent has the following defects: only SPI NOR Flash is supported, the function is fixed single, and the working mode of the chip cannot be adjusted and set in real time. Chinese patent publication No. CN202011420884.8 discloses an IP core for configuration and refresh control of a satellite-borne SRAM type FPGA, which has the following drawbacks: only support the parallel port NOR Flash, the function is fixed singlely, can't adjust the setting to the working pattern of chip in real time.
In summary, the following technical problems exist in the prior art:
(1) The configuration SRAM array of the SRAM type FPGA is easily influenced by space particles, cosmic rays and charged particles, and further false overturn occurs.
(2) The JTAG configuration mode cannot be used for carrying out field actual deployment of products.
(2) PROM approaches fail to read-back refresh.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a circuit for configuring, reading back and refreshing an SRAM type FPGA, which can detect and update code allocation errors in an SRAM type FPGA chip, and can monitor the working state of the chip and set and adjust the working mode by adopting a serial port module.
In order to achieve the above purpose, the present invention adopts the following technical scheme, including:
A circuit for configuring, reading back and refreshing SRAM type FPGA includes the following components: the system comprises a storage controller, a serial port module, a data path, an FPGA interface module and a state machine;
The data path is a bidirectional data transmission path for data interaction between the storage controller and the FPGA interface module, between the storage controller and the serial port module and between the FPGA interface module and the serial port module;
the storage controller is used for reading the data in the memory and sending the data to the serial port module or the FPGA interface module through a data path;
the serial port module is in bidirectional communication connection with the upper computer and is used for sending data to the upper computer and receiving information sent by the upper computer, wherein the received information content comprises instructions, addresses, data, control information and state information; the serial port module sends data to a corresponding address through a data path; the serial port module is also connected with the state machine and sends the instruction, the control information and the state information sent by the upper computer to the state machine;
The FPGA interface module is used for receiving data sent by the storage controller, namely data in the memory through the data path and configuring the FPGA; the FPGA interface module is also used for receiving the data sent by the serial port module through the data path and configuring the FPGA;
The FPGA interface module is used for reading back the FPGA and acquiring reading back data of the FPGA; the FPGA interface module is also used for sending the readback data of the FPGA to the serial port module through the data path;
The FPGA interface module is used for comparing the read-back data of the FPGA, namely comparing the read-back data of the FPGA with the data in the memory or the data sent by the serial port module, if the read-back data of the FPGA are consistent with the data sent by the serial port module, the FPGA functions normally, and the configuration data of the FPGA are correct; if the configuration data of the FPGA is inconsistent, the configuration data of the FPGA is wrong; the FPGA interface module is also used for refreshing the configuration data of the FPGA by utilizing the data in the memory or the data sent by the serial port module;
The state machine is respectively connected with the storage controller and other components in the circuit and is used for receiving the instruction, the control information and the state information sent by the serial port module; the state machine is used for controlling each component in the circuit; the state machine is used for acquiring the working states/parameters of various components in the circuit.
Further, the storage controller is further configured to receive, through a data path, data sent by the serial port module and write the data into the corresponding memory.
Further, the memory controller includes: SPI Flash controller, parallel port NOR Flash controller, PROM controller;
The SPI Flash controller is used for receiving the data sent by the serial port module through the data path and writing the data into the SPI Flash; the SPI Flash controller is also used for reading data in the SPI Flash and sending the data to the serial port module or the FPGA interface module through a data channel; the SPI Flash controller is used for performing read/write/erase operation on the SPI Flash;
The parallel port NOR Flash controller is used for receiving data sent by the serial port module through a data path and writing the data into NOR Flash; the NOR Flash controller is also used for reading data in NOR Flash and sending the data to the serial port module or the FPGA interface module through a data path; the NOR Flash controller is used for performing read/write/erase operation on NOR Flash;
The PROM controller is used for reading data in the PROM and sending the data to the serial port module or the FPGA interface module through a data channel; the PROM controller is used for performing read operation on the PROM;
The FPGA interface module is used for receiving data sent by the SPI Flash controller/the parallel port NOR Flash controller/the PROM controller through a data path, namely the data in the SPI Flash/NOR Flash/PROM, and configuring the FPGA;
The FPGA interface module compares the read-back data of the FPGA, namely, compares the read-back data of the FPGA with the data in the SPI Flash/NOR Flash/PROM, and if the read-back data of the FPGA is consistent with the data in the SPI Flash/NOR Flash/PROM, the FPGA functions normally, and the configuration data of the FPGA is correct; if the configuration data of the FPGA is inconsistent, the configuration data of the FPGA is wrong; if the configuration data of the FPGA is wrong, the FPGA interface module refreshes the configuration data of the FPGA by utilizing the data in the SPI Flash/NOR Flash/PROM;
the state machine is respectively connected with the SPI Flash controller, the parallel port NOR Flash controller and the PROM controller, and controls the read/write/erase operation of the SPI Flash controller on the SPI Flash; the state machine controls the read/write/erase operation of the NOR Flash controller on the NOR Flash; the state machine controls the read operation of the PROM controller to the PROM; and the state machine also respectively acquires working states/parameters of the SPI Flash controller, the parallel NOR Flash controller and the PROM controller.
Further, the circuit further comprises: a configuration register; the serial port module is also in bidirectional communication connection with the configuration register; the serial port module sends data, control information and state information sent by the upper computer to a configuration register; the configuration register is used for controlling the working state/parameter of each component in the circuit; the configuration registers are also used to obtain the operating state/parameters of the various components in the circuit.
Further, the circuit further comprises: an ECC decoding module; the ECC decoding module is connected with the FPGA interface module;
When writing data into the memory, the data is firstly subjected to ECC coding, namely an error correction and detection code is added, and then the coded data is written into the memory;
and when the FPGA interface module receives the encoded data in the memory through the data path, the ECC decoding module is utilized to detect and correct the error of the encoded data in the memory.
Further, the FPGA interface module is further used for detecting whether SEFI faults occur in the FPGA, and if the SEFI faults occur in the FPGA, the FPGA interface module resets the chip of the FPGA; after the FPGA interface module resets the chip of the FPGA, the FPGA interface module receives the data in the SPI Flash/NOR Flash/PROM again or receives the data sent by the serial port module again, and the FPGA is configured.
The invention also provides an operation method of the circuit for configuring, reading back and refreshing the SRAM type FPGA, which comprises the following steps:
s1, the state machine waits for an instruction sent by the serial port module, judges whether the instruction sent by the serial port module is received, namely instruction information of an upper computer, and if the instruction is received, executes the step S2; if the instruction is not received, executing the step S3;
s2, after the state machine receives the instruction sent by the serial port module, namely the instruction information of the upper computer, the state machine analyzes the instruction and performs corresponding operation:
If the instruction analysis content is to access the memory, controlling the memory controller to read/write/erase the memory according to the control information;
If the instruction analysis content is to access the FPGA, controlling the configuration/readback/refreshing of the FPGA by the FPGA interface module according to the control information;
If the analysis content of the instruction is the setting of the state/parameter of the circuit, setting the state/parameter of the circuit according to the state information;
after the state machine finishes corresponding operation according to the instruction analysis content, jumping to the step S1;
S3, the state machine does not receive the instruction sent by the serial port module, and the state machine controls the storage controller to read the data in the memory and send the data to the FPGA interface module through a data path;
s4, the FPGA interface module receives data sent by the storage controller through a data path, namely, reads the data in the memory and is used for configuring the FPGA, namely, the data in the memory is used as configuration data of the FPGA;
S5, the FPGA enters a user mode;
s6, after waiting for a fixed time length, judging whether readback is carried out or not:
If the read-back is carried out, executing a step S7;
If the read-back is not performed, judging whether to perform the refresh, if so, executing the step S8, and if not, jumping back to the step S6;
s7, the FPGA interface module reads back the FPGA to obtain read-back data of the FPGA; the FPGA interface module is used for comparing the read-back data of the FPGA, namely comparing the read-back data of the FPGA with the data in the memory, if the read-back data are consistent, the configuration data are correct, and the step S6 is skipped to wait for a fixed duration; if not, representing that the configuration data is wrong, refreshing the configuration data, and executing step S8;
S8, the FPGA interface module receives data sent by the storage controller through a data path, namely, reads the data in the memory, and refreshes and covers the configuration data of the FPGA by utilizing the data in the memory; after the refresh is completed, the process jumps back to step S6.
Further, in step S2,
If the instruction analysis content is to access the memory, the state machine controls the memory controller to receive the data sent by the serial port module through the data path and write the data into the corresponding memory; or the state machine controls the storage controller to read the data in the storage and send the data to the serial port module through a data path; or the state machine controls the storage controller to erase the data in the storage;
If the instruction analysis content is that the FPGA is accessed, the state machine controls the FPGA interface module to receive the data sent by the serial port module through the data path and configures the FPGA, namely the data sent by the serial port module is used as configuration data of the FPGA; or the state machine controls the FPGA interface module to read back the FPGA to obtain the read-back data of the FPGA; the FPGA interface module compares the read-back data of the FPGA, compares the read-back data of the FPGA with the data sent by the serial port module, and if the read-back data of the FPGA is consistent with the data sent by the serial port module, the FPGA interface module indicates that the function of the FPGA is normal, and the configuration data of the FPGA is correct; if the configuration data of the FPGA is inconsistent, the configuration data of the FPGA is wrong; or the state machine controls the FPGA interface module to refresh the configuration data of the FPGA by using the data sent by the serial port module; or the state machine controls the FPGA interface module to read back the FPGA to obtain the read-back data of the FPGA, and the FPGA interface module sends the read-back data of the FPGA to the upper computer through the serial port module.
Further, in step S3, the state machine controls the corresponding memory controller to read the data in the memory with high access priority according to the access priority of the memory.
Further, after step S5, waiting for a fixed period of time, judging whether to perform SEFI fault detection, if so, performing SEFI fault detection on the FPGA by the FPGA interface module, and if so, performing chip reset on the FPGA by the FPGA interface module; and after the FPGA interface module resets the chip of the FPGA, the FPGA interface module receives the data in the memory again, or receives the data sent by the serial port module again, and the FPGA is configured.
The invention has the advantages that:
(1) The configuration, readback and refreshing operations can detect and update the code allocation errors in the SRAM type FPGA chip, so that the adaptability of the FPGA to severe environments is enhanced.
(2) Compared with JTAG configuration mode, the method can work without an upper computer and can realize on-site deployment.
(3) Compared with a PROM configuration mode, the method can realize the readback, comparison and refreshing of FPGA configuration codes.
(4) Compared with the prior patent, the method can support a plurality of memory chip types such as parallel ports NOR Flash, SPI Flash, PROM and the like.
(5) Compared with the prior patent, the defect of single function fixation is overcome: the chip can work according to a default preset flow after being powered on, and the working mode of the chip can be adjusted and set in real time through the serial port.
(6) The circuit for configuring read-back refreshing can be realized by 1 ASIC single chip or can be realized by CPLD or another FPGA.
Drawings
Fig. 1 is a circuit configuration diagram of embodiment 1.
Fig. 2 is a circuit configuration diagram of embodiment 2.
FIG. 3 is a flow chart of a method of operation of a circuit for configuring, reading back and refreshing an SRAM type FPGA.
Fig. 4 is a schematic diagram of the host accessing each memory through the serial port module 4 in embodiment 1.
Fig. 5 is a schematic diagram of an upper computer accessing an FPGA through the serial port module 4 in embodiment 1.
Fig. 6 is a schematic diagram of an upper computer accessing the configuration register 9 through the serial port module 4 in embodiment 1.
Fig. 7 is a schematic diagram of a configuration operation of the FPGA according to embodiment 1 by data in the memory.
Fig. 8 is a schematic diagram of the read-back and refresh operation of the FPGA through the data in the memory in embodiment 1.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
As shown in fig. 1, a circuit for configuring, reading back and refreshing an SRAM type FPGA, the circuit includes the following components: SPI Flash controller 1, parallel port NOR Flash controller 2, PROM controller 3, serial port module 4, data path 5, FPGA interface module 6, state machine 8, configuration register 9.
The SPI Flash controller 1, the parallel port NOR Flash controller 2 and the PROM controller 3 are all storage controllers.
The SPI Flash controller 1 performs bidirectional data interaction with the data path 5; the SPI Flash controller 1 receives data sent by the serial port module 4 through the data path 5 and writes the data into the SPI Flash; the SPI Flash controller 1 reads data in the SPI Flash and sends the data to the serial port module 4 or the FPGA interface module 6 through the data path 5; the SPI Flash controller 1 receives the control of the state machine 8, and performs operations such as reading, writing, erasing and the like on the parallel SPI Flash under the control of the state machine 8.
The parallel port NOR Flash controller 2 performs bidirectional data interaction with the data path 5; the parallel port NOR Flash controller 2 receives the data sent by the serial port module 4 through the data path 5 and writes the data into NOR Flash; the parallel port NOR Flash controller 2 reads data in the parallel port NOR Flash and sends the data to the serial port module 4 or the FPGA interface module 6 through the data path 5; the parallel port NOR Flash controller 2 receives the control of the state machine 8, and performs operations such as reading, writing, erasing and the like on the parallel port NOR Flash under the control of the state machine 8.
The PROM controller 3 performs data interaction with the data path 5; the PROM controller 3 reads data in the PROM and sends the data to the serial port module 4 or the FPGA interface module 6 through the data path 5; the PROM controller 3 is controlled by the state machine 8, and performs a read operation on the PROM under the control of the state machine 8. Since PROMs are generally read-only, in a typical scenario, PROM controller 3 is only responsible for reading the data in the PROM, and does not perform operations of reading and erasing the PROM; in this embodiment, programming/programming of the PROM may be implemented by a dedicated interface and path.
The serial port module 4 is in bidirectional communication connection with the upper computer, and receives information such as instructions, addresses, data, control information, state information and the like sent by the upper computer.
The serial port module 4 is also connected with the state machine 8, and sends the instruction, the control information and the state information of the upper computer to the state machine 8, and the state machine 8 controls the SPI Flash controller 1/the parallel port NOR Flash controller 2/the PROM controller 3 to perform operations such as reading, writing, erasing and the like on the SPI Flash/the parallel port NOR Flash/the PROM according to the instruction, the control information and the state information of the upper computer; the FPGA interface module 6 is controlled to perform configuration/readback/refresh and other operations on the FPGA; the SPI Flash controller 1/the parallel port NOR Flash controller 2/the PROM controller 3 is controlled to send the read data from the SPI Flash/NOR/PROM to an upper computer through the serial port module 4; the control FPGA interface module 6 sends the configuration data of the read-back FPGA, that is, the read-back data of the FPGA, to the upper computer through the serial port module 4.
The serial port module 4 is also connected with the configuration register 9 and sends data, control information and state information of the upper computer to the configuration register 9; namely, the upper computer performs read-write operation on the configuration register 9 through the serial port module 4; the configuration register 9 is used for controlling the working state/parameter of each component in the circuit; the configuration register 9 is also used for acquiring the working state/parameter of each component in the circuit; the configuration register 9 is understood to be a control bit inside the circuit for setting, controlling, etc. the functions of the circuit, and corresponds to a control register.
The data path 5 is used as a bidirectional data transmission path among the SPI Flash controller 1, the parallel port NOR Flash controller 2, the PROM controller 3, the serial port module 4 and the FPGA interface module 6; the data path 5 is controlled by a state machine; the state machine 8 controls the selection of the FPGA, memory controller by the data path 5 and the data flow direction of the data path 5.
The FPGA interface module 6 receives data sent by the SPI Flash controller 1/the parallel port NOR Flash controller 2/the PROM controller 3, namely data in the SPI Flash/NOR Flash/PROM, and configures the FPGA; the FPGA interface module 6 receives the data sent by the serial port module 4 and configures the FPGA; the FPGA interface module 6 reads back the FPGA and receives the read-back data of the FPGA; the FPGA interface module 6 compares the read-back data of the FPGA with the data in the SPI Flash/NOR Flash/PROM or with the data sent by the serial port module 4: if the functions are consistent, the functions of the FPGA are normal, and the configuration data of the FPGA are correct; if the configuration data of the FPGA is inconsistent, the configuration data of the FPGA is wrong, which indicates that the configuration SRAM array in the FPGA has wrong overturn of the configuration data, when the configuration data of the FPGA is wrong, the FPGA interface module 6 refreshes the FPGA, and the configuration data used for refreshing is from one of the data in the SPI Flash/NOR Flash/PROM or from the data sent by the serial port module 4.
The FPGA interface module 6 is further configured to detect whether an SEFI fault occurs in the FPGA, if the SEFI fault occurs in the FPGA, the FPGA interface module 6 resets the chip of the FPGA, and the specific mode of the chip reset is to pull down the prog_b or program_b pin of the FPGA, and after the FPGA interface module 6 resets the chip of the FPGA, it is necessary to reacquire data in the SPI Flash/NOR Flash/PROM or reacquire data sent by the serial port module 4, that is, reacquire configuration data, and configure the FPGA.
Wherein the SEFI fault comprises:
the DONE pin signal value of the target FPGA is abnormal, which indicates the occurrence of POR SEFI;
Error of FAR register in target FPGA indicates SELECTMAP SEFI;
The BUSY pin value of the target FPGA is abnormal, which indicates that SELECTMAP SEFI is encountered;
A STATUS register in the target FPGA is abnormal, which indicates that POR SEFI or global SEFI appears;
the CTL register within the target FPGA is abnormal, indicating the occurrence of a POR SEFI or a global SEFI.
The state machine 8 is respectively connected with the controller and other components in the circuit, and the state machine 8 is used for receiving the instruction, the control information and the state information of the serial port module 4; the state machine 8 is used for acquiring the working state/parameter of each component in the circuit; the state machine 8 is also used for controlling various components in the circuit, including: the state machine 8 is used for controlling the operation of the memory controller on the memory; the state machine 8 is used for controlling the selection of the data path 5 to the FPGA and the storage controller and controlling the data flow direction of the data path 5; the state machine 8 controls the configuration/read back/refresh of the FPGA by the FPGA interface module 6. The state machine 8 is also used for performing start-stop control and functional configuration on other components in the circuit; controlling the overall workflow and data flow trend of the circuit; and the circuit is also used for resetting the circuit after power-on.
Example 2
In order to improve the reliability of the system, an ECC decoding module 7 is inserted into the circuit as shown in fig. 2 on the basis of embodiment 1: that is, a circuit for configuring, reading back and refreshing an SRAM type FPGA, the circuit comprising: SPI Flash controller 1, parallel port NOR Flash controller 2, PROM controller 3, serial port module 4, data path 5, FPGA interface module 6, ECC decoding module 7, state machine 8.
The ECC decoding module 7 is connected with the FPGA interface module 6;
When writing data into SPI Flash/NOR Flash/PROM, ECC (Error Correction Code) codes are firstly carried out on the data, namely error correction and detection codes are added, and then the coded data are written into corresponding memories. In the invention, the error correction and detection code can be added by a user by using software in a computer outside the circuit, or can be added by a memory controller inside the circuit, and if the error correction and detection code is added by the memory controller inside the circuit, a corresponding ECC encoding module and a decoding module are needed; if added by computer software external to the circuit, the computer software is provided with ECC encoding functionality.
The FPGA interface module 6 utilizes the coded data in the SPI Flash/NOR Flash/PROM to configure the FPGA, or adopts the ECC decoding module 7 to detect and correct errors of the coded data in the SPI Flash/NOR Flash/PROM when the FPGA is read back and compared, so that the data errors in the SPI Flash/NOR Flash/PROM can be resisted, and the reliability of the circuit is improved.
In this embodiment, the error correction and detection code adopts BCH code or hamming code or LDPC code. Wherein, the BCH coding algorithm can realize 2bit error correction of every 51bit data.
The ECC decoding module 7 is also connected with the state machine 8, and is controlled by the state machine 8, and under the control of the state machine 8, the ECC decoding module 7 performs error detection and correction on the encoded data in the SPI Flash/NOR Flash/PROM.
Example 3
Based on the circuit structure provided in embodiment 1, as shown in fig. 3, an operation method for configuring, reading back and refreshing an SRAM type FPGA according to the present invention is as follows:
s1, after power-on, the state machine 8 resets the circuit, then the state machine 8 waits for instruction information sent by the serial port module 4, judges whether instruction information of an upper computer, which is an instruction sent by the serial port module 4, is received, and if the instruction is received, the step S2 is executed; if the instruction is not received, executing the step S3;
S2, after receiving the instruction sent by the serial port module 4, namely the instruction information of the upper computer, the state machine 8 analyzes the instruction and performs corresponding operation according to the instruction analysis content:
if the command analysis content is that the SPI Flash/NOR Flash/PROM is accessed, the state machine 8 controls the SPI Flash controller 1/the parallel port NOR Flash controller 2/the PROM controller 3 to read/write/erase the SPI Flash/NOR Flash/PROM according to the command analysis content; wherein, read-i-read refers to: the storage controller reads the data in the storage and sends the data to the serial port module 4 through the data path 5; write-once refers to: the storage controller receives the data sent by the serial port module 4 and writes the data into a corresponding memory; erasure, i.e., erasure, means: controlling a storage controller to erase data in a memory;
If the instruction analysis content is the access FPGA, the state machine 8 controls the configuration/readback/refresh of the FPGA by the FPGA interface module 6 according to the instruction analysis content; or the FPGA interface module 6 is controlled to send the readback data of the FPGA to the upper computer through the serial port module; wherein, the configuration refers to: the FPGA interface module 6 receives data sent by the serial port module 4 through the data path 5 and is used for configuring the FPGA, namely, the data sent by the serial port module 4 is used as configuration data of the FPGA; readback refers to: the FPGA interface module 6 reads back the FPGA, acquires the read-back data of the FPGA and sends the read-back data to the serial port module 4; comparing the read-back data of the FPGA, and comparing the read-back data of the FPGA with the data sent by the serial port module 4, if the read-back data of the FPGA is consistent with the data sent by the serial port module 4, the function of the FPGA is normal, and the configuration data of the FPGA is correct; if the configuration data of the FPGA is inconsistent, the configuration data of the FPGA is wrong; refreshing refers to: the FPGA interface module 6 refreshes the configuration data of the FPGA by utilizing the data sent by the serial port module 4;
If the analysis content of the instruction is the setting of the state/parameter of the circuit, setting the state/parameter of the circuit according to the state information;
After the state machine 8 finishes the corresponding operation according to the instruction analysis content, the step S1 is skipped;
S3, the state machine 8 does not receive the instruction sent by the serial port module 4, and the state machine 8 controls the SPI Flash controller 1/the parallel port NOR Flash controller 2/the PROM controller 3 to read the data in the SPI Flash/NOR Flash/PROM and send the data to the FPGA interface module 6 through the data path 5;
In step S3, there is an access priority among the SPI Flash, NOR Flash, PROM, and the state machine 8 controls the corresponding memory controller to read the data in the memory with high access priority according to the access priority of each memory;
S4, the FPGA interface module 6 receives data sent by the storage controller, namely data in the read memory, through the data path 5 and is used for configuring the FPGA, namely the data in the memory is used as configuration data of the FPGA;
S5, the FPGA enters a user mode;
S6, after waiting for a fixed time length, judging whether readback is carried out or not: in the invention, whether to read back depends on whether the serial port module 4 receives the instruction and the control information of the upper computer about the read back, and the control information about the read back is stored in the configuration register 9, namely whether the FPGA interface module 6 performs the read back is controlled by the configuration register 9;
If the read-back is carried out, executing a step S7;
If the read-back is not performed, judging whether to perform the refresh, in the invention, the FPGA interface module 6 performs the refresh under the control of the configuration register 9, if the refresh is performed, executing the step S8, and if the refresh is not performed, jumping to the step S6; in the invention, whether to refresh depends on whether the serial port module 4 receives the command and control information of the upper computer about refreshing, and the control information about refreshing is stored in the configuration register 9;
S7, the FPGA interface module 6 reads back the FPGA to obtain read-back data of the FPGA; the FPGA interface module 6 is configured to compare the read-back data of the FPGA, that is, compare the read-back data of the FPGA with the data in the memory, if the read-back data is consistent with the data in the memory, indicate that the configuration data is correct, and skip the step S6; if not, representing that the configuration data is wrong, refreshing the configuration data, and executing step S8;
S8, the FPGA interface module 6 receives data sent by the storage controller through the data path 5, namely, reads the data in the storage, and refreshes the configuration data of the FPGA by utilizing the data in the storage, namely, covers the configuration data; after the refresh is completed, step S6 is skipped.
In this embodiment, after step S5, a fixed period of time may be further waited to determine whether to perform SEFI fault detection, and in the present invention, whether the FPGA interface module 6 performs SEFI fault detection is controlled by the configuration register 9, if so, the FPGA interface module (6) performs SEFI fault detection on the FPGA, and if it is detected that an SEFI fault occurs in the FPGA, the FPGA interface module (6) performs chip reset on the FPGA; and after the FPGA interface module (6) resets the chip of the FPGA, the FPGA interface module (6) receives the data in the memory again, or receives the data sent by the serial port module (4) again, so as to configure the FPGA.
Based on the circuits and the operation methods for configuring, reading back and refreshing the SRAM type FPGA provided in the above embodiments 1 and 3, the following description is made on the data flow in the circuits:
When receiving information such as an instruction, data, and address from the serial port module 4, the serial port module 4 accesses each memory, and performs a read/write operation of the memory, as shown in fig. 4. The operations of configuring, reading back, refreshing, etc. the FPGA through the serial port module 4 are shown in fig. 5. The read-write operation of the configuration register 9 in the chip by the serial port module 4 is shown in fig. 6. When data is read from the memory, the configuration operation of the FPGA by the data in the memory is shown in fig. 7. Operations such as reading back and refreshing the FPGA through data in the memory are shown in fig. 8.
Based on the circuits for configuring, reading back and refreshing the SRAM type FPGA provided in the above embodiments 1 and 2, the serial port module 4 may be specifically RS232, RS422, RS485; the bus interface CAN also be replaced by a CAN bus, an IIC bus and the like. The memory comprises three types, namely SPI Flash, parallel port NOR Flash and PROM, and can be used for placing only 1 type or 2 or more types when the circuit is applied. SPI, parallel NOR, PROM, the three of which are the most common and mature memories, one equivalent alternative form of which is: novel memories such as RRAM resistive random access memory, FRAM ferroelectric memory, PCRAM phase change memory, etc. can also be used. The number of FPGA chips served by the circuit can be 1,2, 3 and 4, and the circuit can be modified and upgraded to support more FPGA chips.
The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims (10)

1. A circuit for configuring, reading back and refreshing an SRAM type FPGA, the circuit comprising: the device comprises a storage controller, a serial port module (4), a data path (5), an FPGA interface module (6) and a state machine (8);
The data path (5) is a bidirectional data transmission path for data interaction between the storage controller and the FPGA interface module (6), between the storage controller and the serial port module (4) and between the FPGA interface module (6) and the serial port module (4);
The storage controller is used for reading data in the storage and sending the data to the serial port module (4) or the FPGA interface module (6) through the data path (5);
The serial port module (4) is in bidirectional communication connection with the upper computer and is used for sending data to the upper computer and receiving information sent by the upper computer, wherein the received information content comprises instructions, addresses, data, control information and state information; the serial port module (4) sends data to a corresponding address through a data path (5); the serial port module (4) is also connected with the state machine (8) and sends the instruction, the control information and the state information sent by the upper computer to the state machine (8);
The FPGA interface module (6) is used for receiving data sent by the storage controller, namely data in the storage through the data path (5) and configuring the FPGA; the FPGA interface module (6) is also used for receiving data sent by the serial port module (4) through the data path (5) and configuring the FPGA;
the FPGA interface module (6) is used for reading back the FPGA to obtain reading back data of the FPGA; the FPGA interface module (6) is also used for sending the readback data of the FPGA to the serial port module (4) through the data path (5);
The FPGA interface module (6) is used for comparing the read-back data of the FPGA, namely comparing the read-back data of the FPGA with the data in the memory or the data sent by the serial port module (4), if the read-back data of the FPGA and the data are consistent, the FPGA functions normally, and the configuration data of the FPGA are correct; if the configuration data of the FPGA is inconsistent, the configuration data of the FPGA is wrong; the FPGA interface module (6) is also used for refreshing the configuration data of the FPGA by utilizing the data in the memory or the data sent by the serial port module (4);
the state machine (8) is respectively connected with the storage controller and other components in the circuit, and the state machine (8) is used for receiving the instruction, the control information and the state information sent by the serial port module (4); -the state machine (8) is used for controlling the various components in the circuit; the state machine (8) is used for acquiring the working state/parameter of each component in the circuit;
The memory controller includes: SPI Flash controller (1), parallel port NOR Flash controller (2), PROM controller (3).
2. The circuit for configuring, reading back and refreshing an SRAM-type FPGA according to claim 1, wherein the memory controller is further configured to receive data sent by the serial port module (4) through the data path (5) and write the data into the corresponding memory.
3. The circuit for configuring, reading back and refreshing an SRAM type FPGA of claim 1, wherein said memory controller comprises: SPI Flash controller (1), parallel port NOR Flash controller (2), PROM controller (3);
The SPI Flash controller (1) is used for receiving data sent by the serial port module (4) through the data path (5) and writing the data into the SPI Flash; the SPI Flash controller (1) is also used for reading data in the SPI Flash and sending the data to the serial port module (4) or the FPGA interface module (6) through the data path (5); the SPI Flash controller (1) is used for performing read/write/erase operation on the SPI Flash;
The parallel port NOR Flash controller (2) is used for receiving data sent by the serial port module (4) through the data path (5) and writing the data into NOR Flash; the parallel port NOR Flash controller (2) is also used for reading data in NOR Flash and sending the data to the serial port module (4) or the FPGA interface module (6) through the data path (5); the parallel port NOR Flash controller (2) is used for performing read/write/erase operation on NOR Flash;
The PROM controller (3) is used for reading data in the PROM and sending the data to the serial port module (4) or the FPGA interface module (6) through the data path (5); the PROM controller (3) is used for performing read operation on the PROM;
the FPGA interface module (6) is used for receiving data sent by the SPI Flash controller (1)/the parallel-port NOR Flash controller (2)/the PROM controller (3) through the data path (5), namely, the data in the SPI Flash/NOR Flash/PROM, and configuring the FPGA;
The FPGA interface module (6) compares the read-back data of the FPGA, namely, compares the read-back data of the FPGA with the data in the SPI Flash/NOR Flash/PROM, and if the read-back data of the FPGA and the data in the SPI Flash/NOR Flash/PROM are consistent, the function of the FPGA is normal, and the configuration data of the FPGA is correct; if the configuration data of the FPGA is inconsistent, the configuration data of the FPGA is wrong; if the configuration data of the FPGA is wrong, the FPGA interface module (6) refreshes the configuration data of the FPGA by utilizing the data in the SPI Flash/NOR Flash/PROM;
The state machine (8) is respectively connected with the SPI Flash controller (1), the parallel port NOR Flash controller (2) and the PROM controller (3), and the state machine (8) controls the read/write/erase operation of the SPI Flash controller (1) on the SPI Flash; the state machine (8) controls the read/write/erase operation of the parallel port NOR Flash controller (2) on NOR Flash; the state machine (8) controls the read operation of the PROM controller (3) on the PROM; the state machine (8) also respectively acquires working states/parameters of the SPI Flash controller (1), the parallel-port NOR Flash controller (2) and the PROM controller (3).
4. A circuit for configuring, reading back and refreshing an SRAM-type FPGA as claimed in claim 1 or 2 or 3, the circuit further comprising: a configuration register (9); the serial port module (4) is also in bidirectional communication connection with the configuration register (9); the serial port module (4) sends data, control information and state information sent by the upper computer to the configuration register (9); the configuration register (9) is used for controlling the working state/parameter of each component in the circuit; the configuration register (9) is also used to obtain the operating state/parameters of the various components in the circuit.
5. A circuit for configuring, reading back and refreshing an SRAM-type FPGA as claimed in claim 1 or 2 or 3, the circuit further comprising: an ECC decoding module (7); the ECC decoding module (7) is connected with the FPGA interface module (6);
When writing data into the memory, the data is firstly subjected to ECC coding, namely an error correction and detection code is added, and then the coded data is written into the memory;
When the FPGA interface module (6) receives the encoded data in the memory through the data path (5), the ECC decoding module (7) is utilized to detect and correct errors of the encoded data in the memory.
6. A circuit for configuring, reading back and refreshing an SRAM-type FPGA according to claim 1,2 or 3, wherein the FPGA interface module (6) is further configured to detect whether an SEFI fault occurs in the FPGA, and if the SEFI fault occurs in the FPGA, the FPGA interface module (6) resets the chip of the FPGA; after the FPGA interface module (6) resets the chip of the FPGA, the FPGA interface module (6) receives the data in the SPI Flash/NOR Flash/PROM again or receives the data sent by the serial port module (4) again to configure the FPGA.
7. A method of operation for a circuit for configuring, reading back and refreshing an SRAM type FPGA as claimed in claim 1 or 2 or 3, comprising the steps of:
S1, the state machine (8) waits for an instruction sent by the serial port module (4), judges whether instruction information of an upper computer, which is the instruction sent by the serial port module (4), is received, and if the instruction is received, executes the step S2; if the instruction is not received, executing the step S3;
s2, after the state machine (8) receives the instruction sent by the serial port module (4), namely instruction information of the upper computer, the instruction is analyzed, and corresponding operation is carried out:
If the instruction analysis content is to access the memory, controlling the memory controller to read/write/erase the memory according to the control information;
If the instruction analysis content is to access the FPGA, controlling the configuration/readback/refresh of the FPGA by the FPGA interface module (6) according to the control information;
If the analysis content of the instruction is the setting of the state/parameter of the circuit, setting the state/parameter of the circuit according to the state information;
the state machine (8) jumps to step S1 after completing corresponding operation according to the instruction analysis content;
S3, the state machine (8) does not receive the instruction sent by the serial port module (4), and the state machine (8) controls the storage controller to read the data in the storage and sends the data to the FPGA interface module (6) through the data path (5);
s4, the FPGA interface module (6) receives data sent by the storage controller, namely, data in the read memory through the data path (5), and the data is used for configuring the FPGA, namely, the data in the memory is used as configuration data of the FPGA;
S5, the FPGA enters a user mode;
s6, after waiting for a fixed time length, judging whether readback is carried out or not:
If the read-back is carried out, executing a step S7;
If the read-back is not performed, judging whether to perform the refresh, if so, executing the step S8, and if not, jumping back to the step S6;
S7, the FPGA interface module (6) reads back the FPGA to obtain read-back data of the FPGA; the FPGA interface module (6) is used for comparing the read-back data of the FPGA, namely comparing the read-back data of the FPGA with the data in the memory, if the read-back data are consistent, indicating that the configuration data are correct, jumping back to the step S6, and waiting for fixed duration; if not, representing that the configuration data is wrong, refreshing the configuration data, and executing step S8;
S8, the FPGA interface module (6) receives data sent by the storage controller through the data path (5), namely, reads the data in the memory, and refreshes the configuration data of the FPGA through the data in the memory, namely, covers the configuration data; after the refreshing is completed, jumping back to the step S6;
The memory controller includes: SPI Flash controller (1), parallel port NOR Flash controller (2), PROM controller (3).
8. An SRAM type FPGA as claimed in claim 7, configured the method of operation of read-back and refresh, characterized in that in step S2,
If the instruction analysis content is the access memory, the state machine (8) controls the memory controller to receive the data sent by the serial port module (4) through the data path (5) and write the data into the corresponding memory; or the state machine (8) controls the storage controller to read the data in the storage and send the data to the serial port module (4) through the data path (5); or the state machine (8) controls the storage controller to erase the data in the storage;
If the instruction analysis content is to access the FPGA, the state machine (8) controls the FPGA interface module (6) to receive the data sent by the serial port module (4) through the data path (5) and configure the FPGA, namely, the data sent by the serial port module (4) is used as configuration data of the FPGA; or the state machine (8) controls the FPGA interface module (6) to read back the FPGA to obtain the read-back data of the FPGA; the FPGA interface module (6) compares the read-back data of the FPGA, compares the read-back data of the FPGA with the data sent by the serial port module (4), and if the read-back data of the FPGA is consistent with the data sent by the serial port module (4), the function of the FPGA is normal, and the configuration data of the FPGA is correct; if the configuration data of the FPGA is inconsistent, the configuration data of the FPGA is wrong; or the state machine (8) controls the FPGA interface module (6) to refresh the configuration data of the FPGA by utilizing the data sent by the serial port module (4); or the state machine (8) controls the FPGA interface module (6) to read back the FPGA to obtain the read-back data of the FPGA, and the FPGA interface module (6) sends the read-back data of the FPGA to the upper computer through the serial port module (4).
9. The method according to claim 7, wherein in step S3, the state machine (8) controls the corresponding memory controller to read the data in the memory with higher access priority according to the access priority of the memory.
10. The method for configuring, reading back and refreshing an SRAM type FPGA according to claim 7, wherein after step S5, a fixed period of time is waited for, and it is determined whether to perform SEFI fault detection, if so, the FPGA interface module (6) performs SEFI fault detection on the FPGA, and if it is detected that an SEFI fault occurs in the FPGA, the FPGA interface module (6) performs chip reset on the FPGA; and after the FPGA interface module (6) resets the chip of the FPGA, the FPGA interface module (6) receives the data in the memory again, or receives the data sent by the serial port module (4) again, so as to configure the FPGA.
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