CN116960253B - Flip light-emitting diode chip and preparation method thereof - Google Patents
Flip light-emitting diode chip and preparation method thereof Download PDFInfo
- Publication number
- CN116960253B CN116960253B CN202311206427.2A CN202311206427A CN116960253B CN 116960253 B CN116960253 B CN 116960253B CN 202311206427 A CN202311206427 A CN 202311206427A CN 116960253 B CN116960253 B CN 116960253B
- Authority
- CN
- China
- Prior art keywords
- layer
- photoresist
- ohmic contact
- positive photoresist
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/84—Coatings, e.g. passivation layers or antireflective coatings
- H10H20/841—Reflective coatings, e.g. dielectric Bragg reflectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
- H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
- H10H20/0137—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials the light-emitting regions comprising nitride materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/84—Coatings, e.g. passivation layers or antireflective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/034—Manufacture or treatment of coatings
Landscapes
- Led Devices (AREA)
Abstract
本发明涉及半导体技术领域，尤其涉及一种倒装发光二极管芯片及其制备方法，包括以下步骤：提供一衬底，在衬底上沉积外延层；在外延层上沉积第一欧姆接触层，在第一欧姆接触层上沉积多个光角转换层；在第一欧姆接触层上沉积第二欧姆接触层；在第二欧姆接触层的边缘制备外延层凹部；对外延层凹部进行刻蚀处理，形成隔离槽；在第二欧姆接触层上依次涂覆多层光刻胶，在多层光刻胶上制备反射层开口；在光刻胶表面依次沉积Ag层和Ti层，保留反射层开口内的Ag层和Ti层，以形成反射镜层；在反射镜层上沉积绝缘保护层，并制备N型绝缘层通孔和P型绝缘层通孔；在绝缘保护层上沉积N型焊盘层和P型焊盘层。本发明能够有效减少反射镜层脱落的风险。
The invention relates to the field of semiconductor technology, and in particular to a flip-chip light-emitting diode chip and a preparation method thereof, which includes the following steps: providing a substrate, depositing an epitaxial layer on the substrate; depositing a first ohmic contact layer on the epitaxial layer, and A plurality of light angle conversion layers are deposited on the first ohmic contact layer; a second ohmic contact layer is deposited on the first ohmic contact layer; an epitaxial layer concave portion is prepared on the edge of the second ohmic contact layer; the concave portion of the epitaxial layer is etched. Form an isolation trench; apply multiple layers of photoresist on the second ohmic contact layer in sequence, and prepare reflective layer openings on the multi-layer photoresist; deposit an Ag layer and a Ti layer on the surface of the photoresist in sequence, leaving the openings in the reflective layer Ag layer and Ti layer to form a mirror layer; deposit an insulating protective layer on the mirror layer, and prepare N-type insulating layer through holes and P-type insulating layer through holes; deposit an N-type pad layer on the insulating protective layer and P-type pad layer. The invention can effectively reduce the risk of the mirror layer falling off.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a flip LED chip and a preparation method thereof.
Background
The LED chip has the advantages of energy conservation, environmental protection, high efficiency, and semi-permanent service life, is widely applied to the fields of illumination and display, and the flip LED chip has strong heat dissipation capability and can be used with large current.
The Ag metal is used as a reflector of the flip LED chip by virtue of extremely high reflectivity of the Ag metal to visible light, and light rays from the epitaxial layer are reflected to be emitted from the substrate surface, but the cleanliness requirement of the Ag metal on a base material is extremely high, and the bonding degree of the Ag metal and other nonmetallic materials is poor, so that the Ag metal is prepared into the reflector by the conventional flip LED chip, and the Ag metal is extremely easy to fall off from the base material in the process of stripping a blue film, so that the yield of the flip LED chip is reduced.
Disclosure of Invention
In order to solve the technical problems, the invention provides a flip LED chip and a preparation method thereof.
The invention adopts the following technical scheme: a preparation method of a flip LED chip comprises the following steps:
providing a substrate, sequentially depositing an N-type GaN layer, a quantum well layer and a P-type GaN layer on the substrate to form an epitaxial layer, and depositing a first ohmic contact layer on the P-type GaN layer;
depositing a plurality of cone-shaped light angle conversion layers on the first ohmic contact layer;
depositing a second ohmic contact layer on the first ohmic contact layer, wherein the lower end of the second ohmic contact layer is abutted against the first ohmic contact layer, a plurality of through holes corresponding to the light angle conversion layer are formed in the second ohmic contact layer, and the aperture of each through hole is larger than the diameter of the lower end of the light angle conversion layer;
preparing an epitaxial layer concave part at the edge of the second ohmic contact layer, wherein the bottom surface of the epitaxial layer concave part is the N-type GaN layer;
etching the edge of the epitaxial layer concave part to form an isolation groove;
sequentially coating multiple layers of photoresist on the second ohmic contact layer, and sequentially exposing the photoresist to form a reflecting layer opening, wherein the reflecting layer opening is of a structure with a wide lower end and a narrow upper end;
sequentially depositing an Ag layer and a Ti layer on the surface of the photoresist on the uppermost layer, heating the substrate, and removing the photoresist and the Ag layer and the Ti layer on the surface of the photoresist to form a reflector layer;
depositing an insulating protective layer on the reflector layer, and preparing an N-type insulating layer through hole and a P-type insulating layer through hole on the insulating protective layer;
and depositing an N-type bonding pad layer and a P-type bonding pad layer on the insulating protective layer, wherein the N-type bonding pad layer is connected with the N-type GaN layer through the N-type insulating layer through hole, and the P-type bonding pad layer is connected with the reflecting mirror layer through the P-type insulating layer through hole.
According to the preparation method of the flip LED chip, the light angle conversion layer is arranged, so that a reflecting mirror layer deposited on the light angle conversion layer subsequently forms a mesa with a trapezoid inclined plane, and light rays with smaller acute angles clamped by the epitaxial layer and the substrate are converted into light rays with larger acute angles clamped by the substrate through reflection of the mesa with the trapezoid inclined plane, so that total reflection of light transmitted among materials of each layer is reduced, and brightness of the flip LED chip is improved; the photoresist is softened and collapsed by heating the substrate, the edges of the Ag layer and the Ti layer deposited in the opening of the reflecting layer are coated, the risk that the reflecting mirror layer falls off when the subsequent blue film is stripped is reduced, and gaps are formed between the uppermost photoresist and the Ag layer and the Ti layer on the surface of the photoresist along with the softening and collapsing of the photoresist, so that the Ag layer and the Ti layer on the surface of the photoresist fall off from the surface of the photoresist more easily, the viscosity of the blue film can be reduced, the risk that the reflecting mirror layer falls off is further reduced, and the yield of the flip LED is effectively improved.
Further, the light angle conversion layer is an AlN layer, the diameter of the upper end of the light angle conversion layer is 7-11 mu m, the diameter of the lower end of the light angle conversion layer is 8-12 mu m, the thickness of the light angle conversion layer is 0.5-5 mu m, and the center distance between adjacent light angle conversion layers is twice the diameter of the lower end of the light angle conversion layer.
Further, the step of sequentially coating a plurality of photoresist layers on the second ohmic contact layer and sequentially exposing the photoresist layers to light to form a reflective layer opening specifically includes:
coating a first positive photoresist on the light angle conversion layer, and carrying out first exposure on the first positive photoresist by adopting a first mask plate;
coating a first negative photoresist on the first positive photoresist, and performing second exposure on the first negative photoresist by adopting a second mask plate;
coating a second positive photoresist on the first negative photoresist, and performing third exposure on the second positive photoresist by adopting a third mask plate;
and removing the exposed first positive photoresist, the second positive photoresist and the unexposed first negative photoresist by adopting a developing process to form a reflecting layer opening consisting of a first positive photoresist opening, a first negative photoresist opening and a second positive photoresist opening which are communicated with each other.
Further, the cross section of the first positive photoresist opening is in an inverted trapezoid shape, the cross section of the first negative photoresist opening is in a positive trapezoid shape, the cross section of the second positive photoresist opening is in an inverted trapezoid shape, the width of the upper end of the first positive photoresist opening is larger than the width of the lower end of the first negative photoresist opening, and the width of the upper end of the first negative photoresist opening is equal to the width of the lower end of the second positive photoresist opening.
Further, the wavelength of the light used for the third exposure is greater than the wavelength of the light used for the second exposure.
Further, the step of sequentially depositing an Ag layer and a Ti layer on the surface of the photoresist on the uppermost layer specifically includes:
depositing an Ag layer on the surface of the photoresist on the uppermost layer by adopting an electron beam evaporation process, wherein a plating pot in the electron beam evaporation process revolves along a track, and simultaneously the plating pot rotates, and when depositing 1/4 thick Ag layer, the revolution direction of the plating pot and the rotation direction of the plating pot are reversely adjusted;
depositing a Ti layer on the Ag layer by adopting an electron beam evaporation process, wherein the thickness of the Ti layer is 1/10-1/8 of that of the Ag layer;
in the electron beam evaporation process, the included angle between the plating pot and the plane of the metal target is 30-60 degrees.
Further, the temperature for heating the substrate is 150-180 ℃.
Further, the step of depositing an insulating protective layer on the reflector layer specifically includes:
SiO deposition by electron beam 2 Method of target material depositing a first SiO on the mirror layer 2 A film of the first SiO 2 The thickness of the film is between 100A and 200A;
PECVD technology is adopted to carry out on the first SiO 2 Deposition of second SiO on film 2 A film of the second SiO 2 The thickness of the film is 5000A-20000A, and the insulating protection layer is formed by the first SiO 2 Film and the second SiO 2 Film composition.
Further, after the step of preparing the N-type insulating layer through hole and the P-type insulating layer through hole on the insulating protection layer, the method further includes: and sequentially introducing a gas containing Cl atoms and a gas containing Si atoms by adopting a dry etching process.
The invention also provides a flip LED chip, which is prepared by adopting the preparation method of the flip LED chip.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method of fabricating a flip LED chip according to the present invention;
fig. 2 is a schematic structural diagram corresponding to step S1 in fig. 1;
fig. 3 is a schematic structural diagram corresponding to step S2 in fig. 1;
fig. 4 is a schematic structural diagram corresponding to step S3 in fig. 1;
fig. 5 is a schematic structural diagram corresponding to step S4 in fig. 1;
fig. 6 is a schematic structural diagram corresponding to step S5 in fig. 1;
FIG. 7 is a schematic structural diagram of the step S6 of FIG. 1, wherein the first positive photoresist is coated and the first mask plate is used for performing a first exposure;
FIG. 8 is a schematic structural diagram corresponding to step S6 of FIG. 1, in which a first negative photoresist is coated and a second mask plate is used for performing a second exposure;
FIG. 9 is a schematic structural diagram corresponding to step S6 of FIG. 1, in which a second positive photoresist is coated and a third mask is used for performing a third exposure;
FIG. 10 is a schematic diagram showing a structure in which the exposed photoresist is removed by development in step S6 of FIG. 1;
FIG. 11 is an enlarged schematic view of portion A of FIG. 10;
FIG. 12 is a schematic diagram of a structure in which an Ag layer and a Ti layer are sequentially deposited on the surface of the uppermost photoresist in step S7 in FIG. 1;
FIG. 13 is a schematic structural diagram corresponding to the step S7 in FIG. 1 for heating the substrate;
fig. 14 is a schematic diagram of the structure of step S7 in fig. 1, in which the photoresist is removed from the Ag layer and the Ti layer on the surface of the photoresist;
fig. 15 is a schematic structural diagram corresponding to step S8 in fig. 1;
fig. 16 is a schematic structural diagram corresponding to step S9 in fig. 1.
Reference numerals illustrate:
10. a substrate; 11. an epitaxial layer; 111. an N-type GaN layer; 112. a quantum well layer; 113. a P-type GaN layer; 114. an epitaxial layer recess; 115. an isolation groove; 12. a first ohmic contact layer; 13. a light angle conversion layer; 14. a second ohmic contact layer; 15. a mirror layer; 151. a first positive photoresist; 152. a first mask plate; 153. a first negative photoresist; 154. a second mask; 155. a second positive photoresist; 156. a third mask; 157. a first positive photoresist opening; 158. a first negative photoresist opening; 159. a second positive photoresist opening; 1510. a mirror sacrificial layer; 16. an insulating protective layer; 161. a P-type insulating layer through hole; 162. an N-type insulating layer through hole; 171. a P-type bonding pad layer; 172. an N-type bonding pad layer.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and intended to illustrate embodiments of the invention and should not be construed as limiting the invention.
In the description of the embodiments of the present invention, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the embodiments of the present invention and simplify description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless explicitly defined otherwise.
In the embodiments of the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured" and the like are to be construed broadly and include, for example, either permanently connected, removably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the embodiments of the present invention will be understood by those of ordinary skill in the art according to specific circumstances.
Referring to fig. 1 to 16, in an embodiment of the present invention, a method for manufacturing a flip-chip light emitting diode chip includes the following steps:
s1: providing a substrate 10, sequentially depositing an N-type GaN layer 111, a quantum well layer 112 and a P-type GaN layer 113 on the substrate 10 to form an epitaxial layer 11, and depositing a first ohmic contact layer 12 on the P-type GaN layer 113;
specifically, an N-type GaN layer 111 doped with Si, an InGaN/GaN quantum well layer 112 periodically stacked, and a P-type GaN layer 113 doped with mg are sequentially prepared on a substrate 10 by using an MOCVD (metal organic chemical vapor deposition) process to form an epitaxial layer 11, then an ITO film is deposited on the surface of the P-type GaN layer 113 by using a magnetron sputtering technique to serve as a first ohmic contact layer 12, and In the ITO film 2 O 3 And SnO 2 The ratio of (1) is 85wt% (15 wt%) (90 wt% (10 wt%) (80 wt% (120 wt%)) and the thickness of the first ohmic contact layer 12 is 80 a-120 a, then the first ohmic contact layer 12 is subjected to a first rapid annealing with a first rapid annealing gas O 2 And N 2 The ratio is 5:1-10:1, and the first rapid annealing temperature is 500-600 ℃; in this embodiment, in ITO thin film 2 O 3 And SnO 2 The ratio of (C) is 90wt%:10wt%, the thickness of the first ohmic contact layer 12 is 100A, and the first rapid annealing gas O 2 And N 2 The ratio was 6:1, and the first rapid annealing temperature was 550 ℃.
S2: depositing a plurality of light angle conversion layers 13 in a truncated cone shape on the first ohmic contact layer 12; further, the light angle conversion layer 13 is an AlN layer, the diameter of the upper end of the light angle conversion layer 13 is 7 μm-11 μm, the diameter of the lower end of the light angle conversion layer 13 is 8 μm-12 μm, the thickness of the light angle conversion layer 13 is 0.5 μm-5 μm, and the center-to-center distance between adjacent light angle conversion layers 13 is twice the diameter of the lower end of the light angle conversion layer 13;
specifically, an AlN film is prepared on the surface of the first ohmic contact layer 12 by using a PVD (physical vapor deposition) method, then a positive photoresist is coated on the AlN film by using a pattern selection method, then a part of photoresist is removed by using exposure and development, a part of AlN film is exposed, then the exposed AlN film is etched in a first reaction tank by using a first solution, then the exposed AlN film is etched in a second reaction tank by using a second solution, the part of AlN film is positioned at the bottom of the rest of photoresist and contacts with the photoresist, then the rest of AlN film is washed in a third reaction tank by using deionized water, the first solution is a 7% -9% tetramethyl ammonium hydroxide solution, the second solution is a 3% -5% tetramethyl ammonium hydroxide solution, and then the rest of photoresist is removed, so that the light angle conversion layer 13 is obtained, and the diameter of the upper end and the lower end of the light angle conversion layer 13 can be controlled by controlling the difference of the concentration of the first solution and the second solution;
let a be the diameter of the side of the light angle conversion layer 13 contacting the surface of the first ohmic contact layer 12, b be the diameter of the side facing away from the first ohmic contact layer 12, c be the thickness of the light angle conversion layer 13, d be the center-to-center distance of two adjacent light angle conversion layers 13, wherein a > b and (a-b)/2 are between-/>3, d=2a, a is 8-12 μm, b is 7-11 μm, c is 0.5-5 μm, the light angle conversion layer 13 can enable the reflector layer 15 arranged on the light angle conversion layer 13 to form a trapezoid inclined plane table surface, and the light rays with smaller acute angles clamped by the epitaxial layer 11 and the substrate 10 are converted into light rays with larger acute angles clamped by the substrate 10 through reflection of the trapezoid inclined plane table surface, so that the total reflection of light transmitted between materials of each layer is reduced, and the brightness of the flip-chip light-emitting diode chip is improved; in this embodiment, the first solution is an 8% tetramethylammonium hydroxide solution, and the second solution is a 4% tetramethylammonium hydroxide solution; the value of a is 10 μm, the value of b is 9 μm, and the value of c is 2 μm.
S3: depositing a second ohmic contact layer 14 on the first ohmic contact layer 12; wherein, the lower end of the second ohmic contact layer 14 is abutted against the first ohmic contact layer 12, the second ohmic contact layer 14 is provided with a plurality of through holes corresponding to the light angle conversion layer 13, and the aperture of the through holes is larger than the diameter of the lower end of the light angle conversion layer 13;
specifically, a negative photoresist is coated on the surfaces of the first ohmic contact layer 12 and the light angle conversion layer 13, then a part of the photoresist is removed by exposure and development, a part of the first ohmic contact layer 12 is exposed, then an ITO film is evaporated on the surfaces of the rest photoresist and the exposed first ohmic contact layer 12 by an electron beam evaporation process, and then a blue film stripping process is used for removingRemoving the ITO film on the residual photoresist, removing the residual photoresist to form a second ohmic contact layer 14 on the first ohmic contact layer 12 between the light angle conversion layers 13, and then performing a second rapid annealing of the second ohmic contact layer 14 with a second rapid annealing gas O 2 And N 2 The proportion is the same as that of the first rapid annealing gas and is between 5:1 and 10:1, and the second rapid annealing temperature is lower than the first rapid annealing temperature and is between 400 and 500 ℃; in the second ohmic contact layer 14 2 O 3 And SnO 2 The ratio of (1) is 92wt% (8 wt%) (97 wt%) (3 wt%), the thickness of the second ohmic contact layer 14 is 100-600 a, and the distance e between the edge of the second ohmic contact layer 14 near the light angle conversion layer 13 and the edge of the light angle conversion layer 13 is 1-2 mu m, i.e. the aperture of the through hole on the second ohmic contact layer 14 is 1-2 mu m larger than the diameter of the lower end of the light angle conversion layer 13; in this embodiment, the second rapid annealing temperature is 450 ℃, and In the second ohmic contact layer 14 2 O 3 And SnO 2 The second ohmic contact layer 14 has a thickness of 300 a at a ratio of 95Wt%:5Wt%, and the edge of the second ohmic contact layer 14 adjacent to the light angle conversion layer 13 is at a distance e of 1.5 μm from the edge of the light angle conversion layer 13.
S4: preparing an epitaxial layer concave part 114 at the edge of the second ohmic contact layer 14, wherein the bottom surface of the epitaxial layer concave part 114 is an N-type GaN layer 111; specific:
positive photoresist is coated on the second ohmic contact layer 14 and the light angle conversion layer 13 and the first ohmic contact layer 12 which is not covered by the second ohmic contact layer 14 and the light angle conversion layer 13, then the photoresist above the epitaxial layer concave 114 area is needed to be prepared by exposing and developing to remove part of the substrate edge, the second ohmic contact layer 14 below the part of photoresist is exposed, then the exposed second ohmic contact layer 14 and the first ohmic contact layer 12 below the part of the second ohmic contact layer 14 are corroded by ITO corrosive liquid, part of the epitaxial layer 11 is exposed, then the exposed epitaxial layer 11 is etched by utilizing an inductive coupling plasma etching process, part of the epitaxial layer 11 is removed until the N-type GaN layer 111 is exposed, the epitaxial layer concave 114 is formed, then the photoresist is removed, and the epitaxial layer concave 114 and the N-type pad layer 172 which is prepared later are electrically connected to form a current output end.
S5: etching the edge of the epitaxial layer concave 114 to form an isolation groove 115; specific:
positive photoresist is coated on the second ohmic contact layer 14 and the light angle conversion layer 13, and the first ohmic contact layer 12 and the epitaxial layer concave portion 114 which are not covered by the second ohmic contact layer 14 and the light angle conversion layer 13, then the photoresist of part of the epitaxial layer concave portion 114 positioned at the edge of the substrate 10 is exposed and developed, the lower epitaxial layer concave portion 114 is exposed, then the exposed epitaxial layer concave portion 114 is removed by utilizing an inductive coupling plasma etching process to form a separation groove 115, and then the photoresist is removed, and the separation groove 115 can prevent solder paste from being connected with the N-type GaN layer 111 when the flip LED chip is welded on an illuminating lamp plate in a subsequent process, so that the flip LED chip is short-circuited.
S6: sequentially coating multiple layers of photoresist on the second ohmic contact layer 14, and sequentially exposing the photoresist to form a reflecting layer opening, wherein the reflecting layer opening has a structure with a wide lower end and a narrow upper end; further, the steps of sequentially coating a plurality of photoresist layers on the second ohmic contact layer 14 and sequentially exposing the photoresist layers to light to form the reflective layer openings specifically include: coating a first positive photoresist 151 on the light angle conversion layer 13, and performing first exposure on the first positive photoresist 151 by using a first mask plate 152; coating a first negative photoresist 153 on the first positive photoresist 151, and performing second exposure on the first negative photoresist 153 by using a second mask plate 154; coating a second positive photoresist 155 on the first negative photoresist 153, and performing third exposure on the second positive photoresist 155 by using a third mask 156; removing the exposed first positive photoresist 151, the second positive photoresist 155 and the unexposed first negative photoresist 153 by a developing process to form a reflective layer opening composed of a first positive photoresist opening 157, a first negative photoresist opening 158 and a second positive photoresist opening 159 which are communicated with each other;
wherein, the cross section of the first positive photoresist opening 157 is in an inverted trapezoid, the cross section of the first negative photoresist opening 158 is in a positive trapezoid, the cross section of the second positive photoresist opening 159 is in an inverted trapezoid, the width of the upper end of the first positive photoresist opening 157 is larger than the width of the lower end of the first negative photoresist opening 158, and the width of the upper end of the first negative photoresist opening 158 is equal to the width of the lower end of the second positive photoresist opening 159; the third exposure uses light having a wavelength greater than that of the second exposure.
Specifically, the second ohmic contact layer 14, the light angle conversion layer 13, the first ohmic contact layer 12 uncovered by the second ohmic contact layer 14 and the light angle conversion layer 13 and the surface of the epitaxial layer concave 114 are cleaned by a plasma cleaning process, wherein the plasma cleaning process specifically comprises the steps of introducing argon into a reaction cavity, then opening radio frequency power ionization, introducing oxygen to enable ionized oxygen ions to clean the surface of a wafer, then introducing nitrogen to enable ionized nitrogen ions to continuously clean the surface of the wafer, wherein the flow ratio of the argon to the oxygen to the nitrogen is 1:5, the flow of the argon is 20sccm-30sccm, the flow of the oxygen to the nitrogen is 100sccm-150sccm, and the radio frequency power is 50W-500W; in the embodiment, the argon flow is 25sccm, the oxygen and nitrogen flows are 120sccm, and the radio frequency power is 200W;
coating a first positive photoresist 151 on the surfaces of the second ohmic contact layer 14 and the light angle conversion layer 13 and the first ohmic contact layer 12, the epitaxial layer concave portion 114 and the isolation groove 115 which are not covered by the second ohmic contact layer 14 and the light angle conversion layer 13, and then performing first exposure by using a first mask plate 152; the viscosity of the first positive photoresist 151 is between 30CPS and 50CPS, the thickness is 2 times to 10 times that of the reflector layer 15 prepared later, the opening width of the first mask plate 152 is f, the first exposure energy is between 200mj/cm and between 230mj/cm, and the first exposure time is between 0.4S and 0.6S; in this embodiment, the viscosity of the first positive photoresist 151 is 40CPS, the thickness is 5 times of the thickness of the subsequently prepared reflecting mirror layer 15, the first exposure energy is 210mj/cm, and the first exposure time is 0.5S;
coating a first negative photoresist 153 on the first positive photoresist 151, then performing second exposure by using a second mask plate 154, wherein the thickness of the part of the first negative photoresist 153 above the second ohmic contact layer 14 is 5-10 times that of the part of the first positive photoresist 151 above the second ohmic contact layer 14, the viscosity of the first negative photoresist 153 is 200CPS-240CPS, the second exposure energy is 300 mj/cm-350 mj/cm, and the second exposure time is 0.6S-0.8S; the width of the unopened region of the second mask 154 is g; in this embodiment, the thickness of the first negative photoresist 153 is 8 times that of the first positive photoresist 151, the viscosity of the first negative photoresist 153 is 220CPS, the second exposure energy is 330mj/cm, and the second exposure time is 0.7S;
coating a second positive photoresist 155 on the first negative photoresist 153, and then performing third exposure by using a third mask plate 156, wherein the thickness of the second positive photoresist 155 is 1.5-3 times that of the first negative photoresist 153, the viscosity of the second positive photoresist 155 is 150CPS-200CPS, the third exposure energy is 250 mj/cm-300 mj/cm, the third exposure time is 0.8S-1.0S, and the opening width of the third mask plate 156 is consistent with the width of the unopened area of the second mask plate 154 and is g; the wavelength of light used in the third exposure is larger than that of light used in the second exposure, so that damage to the first negative photoresist 153 during the third exposure is avoided, and the first negative photoresist 153 is not completely developed; in this embodiment, the thickness of the second positive photoresist 155 is 2 times that of the first negative photoresist 153, the viscosity of the second positive photoresist 155 is 180CPS, the third exposure energy is 280mj/cm, and the third exposure time is 0.9S;
removing the exposed first positive photoresist 151, the second positive photoresist 155 and the unexposed first negative photoresist 153 by utilizing development to form a first positive photoresist opening 157, a first negative photoresist opening 158 and a second positive photoresist opening 159, wherein the specific method of development is that a wafer is soaked for 5S-10S in a reaction tank provided with developing solution, then is washed for 120S-180S in a reaction tank provided with deionized water by flushing, and then the two actions are repeated twice; in the embodiment, the wafer is soaked in a reaction tank provided with developing solution for 8S, and then is flushed and washed in the reaction tank provided with deionized water for 150S;
the cross section of the obtained first positive photoresist opening 157 is in an inverted trapezoid shape, the opening width close to the substrate 10 is equal to the opening width f of the first mask plate 152, the angle alpha of an acute angle formed between the inclined edge of the inverted trapezoid of the first positive photoresist opening 157 and the upper plane of the substrate 10 is 75-85 degrees, the cross section of the first negative photoresist opening 158 is in a positive trapezoid shape, the opening width away from the substrate 10 is equal to the width g of the second mask plate 154, the angle beta of an acute angle formed between the inclined edge of the positive trapezoid of the first negative photoresist opening 158 and the upper plane of the substrate 10 is 20-45 degrees, the cross section of the second positive photoresist opening 159 is in an inverted trapezoid shape, the opening width close to the substrate 10 is equal to the opening width g of the third mask plate 156, and the acute angle gamma of an acute angle formed between the inclined edge of the inverted trapezoid of the second photoresist opening 159 and the upper plane of the substrate 10 is 60-85 degrees; in this embodiment, the angle α is 80 °, the angle β is 30 °, and the angle γ is 70 °.
S7: sequentially depositing an Ag layer and a Ti layer on the surface of the photoresist on the uppermost layer, heating the substrate 10, and removing the photoresist and the Ag layer and the Ti layer on the surface of the photoresist to form a reflector layer 15; further, the step of sequentially depositing an Ag layer and a Ti layer on the surface of the uppermost photoresist layer specifically includes: depositing an Ag layer on the surface of the uppermost photoresist layer by adopting an electron beam evaporation process, wherein a plating pot in the electron beam evaporation process revolves along a track, and simultaneously the plating pot rotates, and when depositing 1/4 thick Ag layer, the revolution direction of the plating pot and the rotation direction of the plating pot are reversely adjusted; depositing a Ti layer on the Ag layer by adopting an electron beam evaporation process, wherein the thickness of the Ti layer is 1/10 times to 1/8 times of that of the Ag layer; wherein, in the electron beam evaporation process, the included angle between the plating pot and the plane of the metal target is 30-60 degrees; further, the temperature at which the substrate is heated is between 150 ℃ and 180 ℃.
Specifically, an Ag layer and a Ti layer are sequentially deposited on the surface of the remaining second positive photoresist 155 and the surface of the second ohmic contact layer 14, the light angle conversion layer 13 and the surface of the first ohmic contact layer 12 uncovered by the second ohmic contact layer 14 and the light angle conversion layer 13 by using an electron beam deposition process, wherein the Ag layer and the Ti layer disposed on the surface of the second positive photoresist 155 are the mirror sacrificial layer 1510, and the Ag layer and the Ti layer disposed on the surface of the second ohmic contact layer 14, the light angle conversion layer 13 and the surface of the first ohmic contact layer 12 uncovered by the second ohmic contact layer 14 and the light angle conversion layer 13 are the mirror layer 15;
the thickness of the Ti layer is 1/10 times to 1/8 times of that of the Ag layer, and the thickness of the Ag layer is 1200A-5000A; in the process of evaporating Ag layer, firstly, evaporating 1/4 thickness of Ag layer, and in the process of evaporating Ag layer, the plating pot revolves clockwise along the track, and the plating pot also revolves clockwise; then evaporating an Ag layer with the thickness of 1/4, wherein the plating pot revolves anticlockwise along the track in the evaporation process, the plating pot also revolves anticlockwise, then evaporating the Ag layer with the thickness of 1/4 continuously, and the plating pot revolves clockwise along the track in the evaporation process, and the plating pot also revolves clockwise; then continuously evaporating an Ag layer with the thickness of 1/4, wherein the plating pot revolves anticlockwise along the track in the evaporation process, and the plating pot also rotates anticlockwise, so that the whole Ag layer is evaporated in four evaporation processes, and the thickness uniformity of Ag metal on the wafer can be improved by repeatedly changing the revolution and rotation directions of the plating pot; the power of the electron beams is the same in the four Ag metal evaporation processes and is 120W-160W; in the Ti metal evaporation process, the plating pot revolves clockwise along the track, the plating pot rotates clockwise, and the power of the electron beam in the Ti metal evaporation process is 150W-200W; in the four processes of evaporating Ag metal and the process of evaporating Ti metal, the included angles between the plating pot and the plane where the metal target is located are the same, and are all theta, wherein theta is 30-60 degrees, and the angles can ensure that the Ag metal is evaporated into the first positive photoresist opening 157 below the first negative photoresist opening 158; after evaporation is finished, the distance between the edge of the reflecting mirror layer 15 and the edge of the first positive photoresist 151 is h, and h is less than or equal to (f-g)/2; in this embodiment, the thickness of the Ti layer is 1/8 times that of the Ag layer, and the thickness of the Ag layer is 3000A; the power of the electron beam in the process of evaporating Ag metal is 140W; the power of the electron beam in the Ti metal evaporation process is 180W; θ was 45 °.
Then placing the flip-chip light emitting diode on a baking plate, placing the substrate 10 on the baking plate, heating the baking plate to 150-180 ℃ and maintaining the temperature at 180-240S, heating the flip-chip light emitting diode chip from the bottom surface of the substrate 10 to soften the first positive photoresist 151, the first negative photoresist 153 and the second positive photoresist 155, so that the first positive photoresist opening 157, the first negative photoresist opening 158 and the second positive photoresist opening 159 collapse, completely wrapping the edge of the reflector layer 15, avoiding the falling-off of the reflector layer 15 during the subsequent stripping of the blue film, and collapsing the second positive photoresist opening 159, so that the edge of the reflector sacrificial layer 1510 forms a gap with the surface of the second positive photoresist 155, and the reflector sacrificial layer 1510 is easier to fall off from the surface of the second positive photoresist 155, thereby reducing the viscosity of the blue film and further reducing the risk of falling-off of the reflector layer 15; in this example, the baking sheet is heated to 180 ℃ and maintained at this temperature 210S;
finally, the mirror sacrificial layer 1510 on the second positive photoresist 155 is stripped off by a blue film stripping process, and then the remaining first positive photoresist 151, first negative photoresist 153 and second positive photoresist 155 are removed by photoresist stripping, thereby completing the preparation of the mirror layer 15.
S8: depositing an insulating protective layer 16 on the mirror layer 15, and preparing an N-type insulating layer via 162 and a P-type insulating layer via 161 on the insulating protective layer 16; further, the step of depositing the insulating protection layer 16 on the mirror layer 15 specifically includes: siO deposition by electron beam 2 Method of target material first SiO is deposited on the mirror layer 15 2 Film, first SiO 2 The thickness of the film is between 100A and 200A; PECVD process is adopted on the first SiO 2 Deposition of second SiO on film 2 Film, second SiO 2 The thickness of the film is 5000A-20000A, and the insulating protection layer 16 is made of first SiO 2 Film and second SiO 2 Film composition; further, after the step of preparing the N-type insulating layer via 162 and the P-type insulating layer via 161 on the insulating protective layer 16, it further includes: and sequentially introducing a gas containing Cl atoms and a gas containing Si atoms by adopting a dry etching process.
Specific: siO is deposited on the surfaces of the reflector layer 15, the epitaxial layer recess 114 and the isolation groove 115 by electron beam deposition 2 Method for preparing first SiO by target material 2 Thin films, followed by filling SiH using PECVD (plasma enhanced chemical vapor deposition) process 4 And N 2 O is at the first SiO 2 Preparation of second SiO on film surface 2 Film, first SiO 2 The film thickness is far smaller than that of the second SiO 2 Film thickness, first SiO 2 The thickness of the film is between 100A and 200A, and the second SiO 2 The film thickness is 5000A-20000A because the PECVD is used for preparing SiO 2 In the film process, if oxygen ions participate, siO is directly prepared on the surface of the reflecting mirror layer 15 by PECVD process 2 The film can cause the problem of Ag metal in the oxygen ion oxidation reflecting mirror layer, and the SiO is evaporated by the electron beam evaporation process 2 The film process has no participation of oxygen ions, but the SiO vapor deposited by the electron beam vapor deposition process 2 The film has poor coverage on the sides, such as SiO is required on the sides of epitaxial recess 114 and isolation trench 115 2 The film is covered and protected, so the invention firstly utilizes the electron beam evaporation process to prepare an extremely thin SiO 2 The thin film protects the reflector layer 15 and a PECVD process is used to prepare a thicker second SiO 2 A thin film which prevents the mirror layer 15 from being oxidized and protects the sides of the epitaxial layer recess 114 and the isolation trench 115, a first SiO 2 Film and second SiO 2 The films together form an insulating protective layer 16; in the present embodiment, a first SiO 2 The film thickness is 150A, the second SiO 2 The thickness of the film is 10000A;
coating positive photoresist on the surface of the insulating protection layer 16, exposing and developing to remove part of the photoresist to expose part of the insulating protection layer 16, removing the exposed insulating protection layer 16 by using a first dry etching process to form an N-type insulating layer through hole 162 and a P-type insulating layer through hole 161, repairing the surface of the epitaxial layer concave part 114 below the N-type insulating layer through hole 162 damaged by the first dry etching process by using a second dry etching process, and removing the photoresist; because the gas introduced in the first dry etching process can be mixed with SiO 2 The reacted F-atom-containing gas, but the F-atom-containing gas also reacts with Si atoms doped on the surface of the epitaxial layer recess 114 below the N-type insulating layer through hole 162 to increase the surface resistance of the epitaxial layer recess 114 and raise the voltage of the flip-chip light emitting diode chip, so that after the first dry etching is finished, the invention uses the second dry etchingThe dry etching process repairs the surface of the epitaxial layer concave portion 114 below the first dry etching damaged N-type insulating layer through hole 162, and the second dry etching process specifically comprises the steps of introducing gas containing Cl atoms to react with GaN material on the surface of the damaged epitaxial layer concave portion 114 to take away the damaged GaN material, introducing gas containing Si atoms to perform ion implantation in the epitaxial layer concave portion 114, doping the epitaxial layer concave portion 114 again, and reducing the resistivity of the epitaxial layer concave portion 114.
S9: depositing an N-type pad layer 172 and a P-type pad layer 171 on the insulating protective layer 16, the N-type pad layer 172 being connected to the N-type GaN layer 111 through the N-type insulating layer via 162, the P-type pad layer 171 being connected to the mirror layer 15 through the P-type insulating layer via 161;
specifically, negative photoresist is coated on the surfaces of the insulating protection layer 16, the N-type insulating layer through hole 162 and the P-type insulating layer through hole 161, then a first metal layer, a second metal layer and a third metal layer are sequentially evaporated by utilizing an electron beam evaporation process, the first metal layer is close to the insulating protection layer 16, the third metal layer is far away from the insulating protection layer 16, the second metal layer is arranged between the first metal layer and the second metal layer, the first metal layer is a Ni layer, the Ni layer is contacted with the reflector layer 15 in the P-type insulating layer through hole 161, ag metal can be well prevented from migrating outwards, the second metal layer can be one or a combination of a Cr layer, a Ti layer, a Pt layer and a Pb layer, the second metal layer is used for adjusting stress, the third metal layer can be one of an Au layer, a Sn layer, an AuSn layer, a SnCu layer and a SnAgCu layer, the third metal layer is used for being connected with a bonding connection of a circuit board, the first metal layer, the second metal layer and the third metal layer jointly form a pad layer, the pad layer comprises a P-type pad layer 171 and an N-type pad layer 172, and the P-type pad layer 172 is electrically connected with the P-type insulating layer 161 through the P-type insulating layer through hole 114, and the P-type pad layer 172 is electrically connected with the P-type insulating layer 161 through the P-type insulating layer and the P-type insulating layer 161.
According to the preparation method of the flip LED chip, the light angle conversion layer 13 is arranged, so that a reflecting mirror layer 15 deposited on the light angle conversion layer 13 subsequently forms a mesa with a trapezoid inclined plane, and the light rays with smaller acute angles clamped by the epitaxial layer 11 and the substrate 10 are converted into the light rays with larger acute angles clamped by the substrate 10 through the reflection of the mesa with the trapezoid inclined plane, so that the total reflection of light transmitted among materials of each layer is reduced, and the brightness of the flip LED chip is improved; the photoresist is softened and collapsed by heating the substrate 10, the edges of the Ag layer and the Ti layer deposited in the opening of the reflecting layer are coated, the risk that the reflecting mirror layer 15 falls off when the subsequent blue film is stripped is reduced, and gaps are formed between the uppermost photoresist and the Ag layer and the Ti layer on the surface of the photoresist along with the softening and collapsing of the photoresist, so that the Ag layer and the Ti layer on the surface of the photoresist fall off from the surface of the photoresist more easily, the viscosity of the blue film can be reduced, the risk that the reflecting mirror layer 15 falls off is further reduced, and the yield of the flip-chip light-emitting diode is effectively improved.
The invention also provides a flip LED chip, which is prepared by adopting the preparation method of the flip LED chip.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above additional technical features can be freely combined and superimposed by a person skilled in the art without conflict.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (7)
1. The preparation method of the flip LED chip is characterized by comprising the following steps of:
providing a substrate, sequentially depositing an N-type GaN layer, a quantum well layer and a P-type GaN layer on the substrate to form an epitaxial layer, and depositing a first ohmic contact layer on the P-type GaN layer;
depositing a plurality of cone-shaped light angle conversion layers on the first ohmic contact layer; wherein the light angle conversion layer is an AlN layer;
depositing a second ohmic contact layer on the first ohmic contact layer, wherein the lower end of the second ohmic contact layer is abutted against the first ohmic contact layer, a plurality of through holes corresponding to the light angle conversion layer are formed in the second ohmic contact layer, and the aperture of each through hole is larger than the diameter of the lower end of the light angle conversion layer;
preparing an epitaxial layer concave part at the edge of the second ohmic contact layer, wherein the bottom surface of the epitaxial layer concave part is the N-type GaN layer;
etching the edge of the epitaxial layer concave part to form an isolation groove;
sequentially coating multiple layers of photoresist on the second ohmic contact layer, and sequentially exposing the photoresist to form a reflecting layer opening, wherein the reflecting layer opening is of a structure with a wide lower end and a narrow upper end;
sequentially depositing an Ag layer and a Ti layer on the surface of the photoresist on the uppermost layer, heating the substrate, and removing the photoresist and the Ag layer and the Ti layer on the surface of the photoresist to form a reflector layer;
depositing an insulating protective layer on the reflector layer, and preparing an N-type insulating layer through hole and a P-type insulating layer through hole on the insulating protective layer;
depositing an N-type bonding pad layer and a P-type bonding pad layer on the insulating protective layer, wherein the N-type bonding pad layer is connected with the N-type GaN layer through the N-type insulating layer through hole, and the P-type bonding pad layer is connected with the reflecting mirror layer through the P-type insulating layer through hole;
the step of sequentially coating a plurality of photoresist layers on the second ohmic contact layer and sequentially exposing the photoresist layers to form a reflective layer opening specifically comprises the following steps:
coating a first positive photoresist on the light angle conversion layer, and carrying out first exposure on the first positive photoresist by adopting a first mask plate;
coating a first negative photoresist on the first positive photoresist, and performing second exposure on the first negative photoresist by adopting a second mask plate;
coating a second positive photoresist on the first negative photoresist, and performing third exposure on the second positive photoresist by adopting a third mask plate;
removing the exposed first positive photoresist, the second positive photoresist and the unexposed first negative photoresist by adopting a developing process to form a reflecting layer opening consisting of a first positive photoresist opening, a first negative photoresist opening and a second positive photoresist opening which are communicated with each other;
wherein the first positive photoresist adhesive is between 30CPS and 50CPS, the first negative photoresist adhesive is between 200CPS and 240CPS, and the second positive photoresist adhesive is between 150CPS and 200CPS;
the cross section of the first positive photoresist opening is in an inverted trapezoid shape, the cross section of the first negative photoresist opening is in a positive trapezoid shape, the cross section of the second positive photoresist opening is in an inverted trapezoid shape, the width of the upper end of the first positive photoresist opening is larger than that of the lower end of the first negative photoresist opening, and the width of the upper end of the first negative photoresist opening is equal to that of the lower end of the second positive photoresist opening;
the step of sequentially depositing an Ag layer and a Ti layer on the surface of the photoresist on the uppermost layer specifically comprises the following steps:
depositing an Ag layer on the surface of the photoresist on the uppermost layer by adopting an electron beam evaporation process, wherein a plating pot in the electron beam evaporation process revolves along a track, and simultaneously the plating pot rotates, and when depositing 1/4 thick Ag layer, the revolution direction of the plating pot and the rotation direction of the plating pot are reversely adjusted;
depositing a Ti layer on the Ag layer by adopting an electron beam evaporation process, wherein the thickness of the Ti layer is 1/10-1/8 of that of the Ag layer;
wherein, in the electron beam evaporation process, the included angle between the plating pot and the plane of the metal target is 30-60 degrees;
the Ag layer and the Ti layer arranged on the surface of the second positive photoresist are mirror sacrificial layers, and the Ag layer and the Ti layer arranged on the surface of the second ohmic contact layer exposed by the opening of the reflecting layer, the light angle conversion layer and the first ohmic contact layer uncovered by the second ohmic contact layer and the light angle conversion layer are mirror layers;
the step of heating the substrate to remove the photoresist and the Ag layer and the Ti layer on the surface of the photoresist to form a reflector layer specifically comprises the following steps:
firstly, heating the substrate to soften the first positive photoresist, the first negative photoresist and the second positive photoresist, so that the first positive photoresist opening, the first negative photoresist opening and the second positive photoresist opening collapse, the edge of the reflector layer is completely covered, the second positive photoresist opening collapses, and gaps are formed between the edge of the sacrificial layer of the reflector and the surface of the second positive photoresist;
and then stripping the mirror sacrificial layer on the second positive photoresist by using a blue film stripping process, and finally removing the residual first positive photoresist, the residual first negative photoresist and the residual second positive photoresist by using a photoresist stripping solution, thereby completing the preparation of the mirror layer.
2. The method of manufacturing a flip-chip light emitting diode chip according to claim 1, wherein the light angle conversion layer is an AlN layer, the light angle conversion layer has an upper diameter of 7 μm to 11 μm and a lower diameter of 8 μm to 12 μm, the light angle conversion layer has a thickness of 0.5 μm to 5 μm, and a center-to-center distance between adjacent light angle conversion layers is twice the diameter of the lower end of the light angle conversion layer.
3. The method of claim 1, wherein the third exposure uses light having a wavelength greater than that of the second exposure.
4. The method of manufacturing a flip-chip light emitting diode chip according to claim 1, wherein the temperature of heating the substrate is 150 ℃ to 180 ℃.
5. The method of fabricating a flip-chip light emitting diode chip as defined in claim 1, wherein the step of depositing an insulating protective layer on the reflector layer comprises:
SiO deposition by electron beam 2 Method of target material depositing a first SiO on the mirror layer 2 A film of the first SiO 2 The thickness of the film is between 100A and 200A;
PECVD technology is adopted to carry out on the first SiO 2 Deposition of second SiO on film 2 A film of the second SiO 2 The thickness of the film is 5000A-20000A, and the insulating protection layer is formed by the first SiO 2 Film and the second SiO 2 Film composition.
6. The method of manufacturing a flip-chip light emitting diode chip as claimed in claim 1, wherein after the step of manufacturing the N-type insulating layer via hole and the P-type insulating layer via hole on the insulating protection layer, further comprising: and sequentially introducing a gas containing Cl atoms and a gas containing Si atoms by adopting a dry etching process.
7. A flip-chip light emitting diode chip, characterized in that it is manufactured by the manufacturing method of the flip-chip light emitting diode chip according to any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311206427.2A CN116960253B (en) | 2023-09-19 | 2023-09-19 | Flip light-emitting diode chip and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311206427.2A CN116960253B (en) | 2023-09-19 | 2023-09-19 | Flip light-emitting diode chip and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116960253A CN116960253A (en) | 2023-10-27 |
| CN116960253B true CN116960253B (en) | 2023-12-19 |
Family
ID=88460498
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311206427.2A Active CN116960253B (en) | 2023-09-19 | 2023-09-19 | Flip light-emitting diode chip and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116960253B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117393680B (en) * | 2023-12-12 | 2024-04-12 | 江西兆驰半导体有限公司 | A flip-chip light-emitting diode chip and its preparation method |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000183095A (en) * | 1998-12-21 | 2000-06-30 | Sanyo Electric Co Ltd | Manufacture of chip-size package |
| JP2005347700A (en) * | 2004-06-07 | 2005-12-15 | Toyoda Gosei Co Ltd | Light emitting device and its manufacturing method |
| JP2006344710A (en) * | 2005-06-08 | 2006-12-21 | Sony Corp | Semiconductor light emitting element, its manufacturing method, semiconductor light emitting device, and its manufacturing method |
| CN101213678A (en) * | 2005-07-04 | 2008-07-02 | 昭和电工株式会社 | Gallium nitride-based compound semiconductor lihgt-emitting device |
| CN103137441A (en) * | 2011-11-22 | 2013-06-05 | 上海华虹Nec电子有限公司 | Method for manufacturing elongated isolated line pattern in semiconductor process |
| CN109524514A (en) * | 2018-11-23 | 2019-03-26 | 江苏新广联半导体有限公司 | A kind of flip LED chips and preparation method thereof with Ag reflection layer structure |
| WO2019085538A1 (en) * | 2017-11-03 | 2019-05-09 | 江苏新广联半导体有限公司 | Led flip chip for improving current spreading uniformity, and manufacturing method therefor |
| CN111509100A (en) * | 2019-01-31 | 2020-08-07 | 首尔伟傲世有限公司 | led |
| CN215184030U (en) * | 2020-11-04 | 2021-12-14 | 山西中科潞安紫外光电科技有限公司 | Deep ultraviolet light-emitting diode with vertical structure |
-
2023
- 2023-09-19 CN CN202311206427.2A patent/CN116960253B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000183095A (en) * | 1998-12-21 | 2000-06-30 | Sanyo Electric Co Ltd | Manufacture of chip-size package |
| JP2005347700A (en) * | 2004-06-07 | 2005-12-15 | Toyoda Gosei Co Ltd | Light emitting device and its manufacturing method |
| JP2006344710A (en) * | 2005-06-08 | 2006-12-21 | Sony Corp | Semiconductor light emitting element, its manufacturing method, semiconductor light emitting device, and its manufacturing method |
| CN101213678A (en) * | 2005-07-04 | 2008-07-02 | 昭和电工株式会社 | Gallium nitride-based compound semiconductor lihgt-emitting device |
| CN103137441A (en) * | 2011-11-22 | 2013-06-05 | 上海华虹Nec电子有限公司 | Method for manufacturing elongated isolated line pattern in semiconductor process |
| WO2019085538A1 (en) * | 2017-11-03 | 2019-05-09 | 江苏新广联半导体有限公司 | Led flip chip for improving current spreading uniformity, and manufacturing method therefor |
| CN109524514A (en) * | 2018-11-23 | 2019-03-26 | 江苏新广联半导体有限公司 | A kind of flip LED chips and preparation method thereof with Ag reflection layer structure |
| CN111509100A (en) * | 2019-01-31 | 2020-08-07 | 首尔伟傲世有限公司 | led |
| CN215184030U (en) * | 2020-11-04 | 2021-12-14 | 山西中科潞安紫外光电科技有限公司 | Deep ultraviolet light-emitting diode with vertical structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116960253A (en) | 2023-10-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107195747B (en) | Micron-sized flip-chip LED chip and preparation method thereof | |
| CN105070799B (en) | An LED chip manufacture method | |
| CN111244244A (en) | High-power LED chip and manufacturing method thereof | |
| CN116960253B (en) | Flip light-emitting diode chip and preparation method thereof | |
| CN116230733B (en) | A kind of Micro LED chip and preparation method thereof | |
| CN114709307A (en) | A flip-chip light-emitting diode chip and preparation method thereof | |
| CN116936711B (en) | Vertical light emitting diode, preparation method thereof and LED lamp panel | |
| CN206834196U (en) | A kind of micron-scale flip LED chips | |
| CN118588824A (en) | A flip-chip light-emitting diode chip and its preparation method | |
| CN114551680A (en) | Flip light-emitting diode chip and preparation method thereof | |
| CN116646435A (en) | A flip-chip light-emitting diode chip and its preparation method | |
| CN117393680A (en) | Flip light-emitting diode chip and preparation method thereof | |
| CN110828483A (en) | Top-emitting OLED display back plate, manufacturing method thereof and OLED display device | |
| CN115863514B (en) | Vertical LED chip and preparation method thereof | |
| CN116581225A (en) | Flip light-emitting diode chip and preparation method thereof | |
| CN118610339B (en) | Flip light-emitting diode chip and preparation method thereof | |
| CN102931300A (en) | Method for manufacturing back metallic reflector array in manufacturing process of GaN-based LED | |
| CN119317276A (en) | A flip-chip light-emitting diode chip and its preparation method | |
| CN117790659B (en) | Micro-display luminous pixel with omnibearing reflecting mirror structure and its making method | |
| CN118136759A (en) | A reverse polarity LED chip and its manufacturing method | |
| CN115863498B (en) | Preparation method of forward-mounted LED chip | |
| CN116722087A (en) | A flip-chip light-emitting diode chip and its preparation method | |
| CN118825156B (en) | A method for preparing an inverted light emitting diode and an inverted light emitting diode | |
| CN106972088A (en) | A kind of LED metal electrode structures and preparation method thereof | |
| CN111769212A (en) | Anode structure of OLED device and OLED device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |