CN116960253A - Flip light-emitting diode chip and preparation method thereof - Google Patents

Abstract

The invention relates to the technical field of semiconductors, in particular to a flip LED chip and a preparation method thereof, comprising the following steps: providing a substrate, and depositing an epitaxial layer on the substrate; depositing a first ohmic contact layer on the epitaxial layer, and depositing a plurality of light angle conversion layers on the first ohmic contact layer; depositing a second ohmic contact layer on the first ohmic contact layer; preparing an epitaxial layer concave part at the edge of the second ohmic contact layer; etching the concave part of the epitaxial layer to form an isolation groove; sequentially coating a plurality of layers of photoresist on the second ohmic contact layer, and preparing a reflecting layer opening on the plurality of layers of photoresist; sequentially depositing an Ag layer and a Ti layer on the surface of the photoresist, and reserving the Ag layer and the Ti layer in the opening of the reflecting layer to form a reflecting mirror layer; depositing an insulating protective layer on the reflector layer, and preparing an N-type insulating layer through hole and a P-type insulating layer through hole; and depositing an N-type bonding pad layer and a P-type bonding pad layer on the insulating protective layer. The invention can effectively reduce the risk of falling off of the reflecting mirror layer.

Description

Flip-chip light-emitting diode chip and preparation method thereof

Technical field

The present invention relates to the field of semiconductor technology, and in particular to a flip-chip light-emitting diode chip and a preparation method thereof.

Background technique

Light-emitting diode chips are energy-saving, environmentally friendly, highly efficient, and have a semi-permanent life and are widely used in the lighting and display fields. Flip-chip light-emitting diode chips have the advantages of strong heat dissipation and can be used with high current.

Ag metal is used as a reflector for flip-chip light-emitting diode chips due to its extremely high reflectivity of visible light. It reflects the light from the epitaxial layer and makes it emit from the substrate surface. However, Ag metal has extremely high requirements for the cleanliness of the base material, and Ag metal has poor adhesion with other non-metallic materials. Therefore, existing flip-chip light-emitting diode chips use Ag metal as a reflector. During the peeling process of the blue film, the Ag metal easily falls off from the base material, causing flip-chip light emission. Diode chip yield is reduced.

Contents of the invention

In order to solve the above technical problems, the present invention provides a flip-chip light-emitting diode chip and a preparation method thereof.

The present invention adopts the following technical solution: a method for preparing a flip-chip light-emitting diode chip, which includes the following steps:

Provide a substrate, deposit an N-type GaN layer, a quantum well layer and a P-type GaN layer sequentially on the substrate to form an epitaxial layer, and deposit a first ohmic contact layer on the P-type GaN layer;

depositing a plurality of frustum-shaped optical angle conversion layers on the first ohmic contact layer;

A second ohmic contact layer is deposited on the first ohmic contact layer, wherein the lower end of the second ohmic contact layer is in contact with the first ohmic contact layer, and the second ohmic contact layer has a A plurality of through holes corresponding to the light angle conversion layer, and the aperture of the through holes is larger than the diameter of the lower end of the light angle conversion layer;

An epitaxial layer recess is prepared at the edge of the second ohmic contact layer, and the bottom surface of the epitaxial layer recess is the N-type GaN layer;

Perform an etching process on the edge of the recessed portion of the epitaxial layer to form an isolation trench;

Apply multiple layers of photoresist on the second ohmic contact layer in sequence, and expose the photoresist in sequence to form a reflective layer opening, where the reflective layer opening has a structure with a wide lower end and a narrow upper end;

An Ag layer and a Ti layer are sequentially deposited on the surface of the uppermost photoresist, the substrate is heated, and the photoresist and the Ag layer and Ti layer located on the surface of the photoresist are removed to form a reflection mirror layer;

Deposit an insulating protective layer on the mirror layer, and prepare N-type insulating layer through holes and P-type insulating layer through holes on the insulating protective layer;

An N-type pad layer and a P-type pad layer are deposited on the insulating protective layer. The N-type pad layer is connected to the N-type GaN layer through the N-type insulating layer through hole. The P-type bonding layer The disk layer is connected to the mirror layer through the P-type insulation layer through hole.

A method for preparing a flip-chip light-emitting diode chip according to an embodiment of the present invention provides a light angle conversion layer so that the mirror layer subsequently deposited on the light angle conversion layer forms a trapezoidal sloped mesa. The part emitted by the epitaxial layer is in contact with the lining. The light with a smaller acute angle between the bottom and the substrate is converted into a light with a larger acute angle with the substrate through the reflection of the trapezoidal inclined surface, thereby reducing the total reflection of light propagating between each layer of materials and improving the flip-chip light-emitting diode. Chip brightness; by heating the substrate, the photoresist softens and collapses, and the edges of the Ag layer and Ti layer deposited in the opening of the reflective layer are completely covered, reducing the risk of the mirror layer falling off when the subsequent blue film is peeled off, and the uppermost layer The photoresist and the Ag layer and Ti layer on the photoresist surface will collapse as the photoresist softens, forming a gap, making it easier for the Ag layer and Ti layer on the photoresist surface to fall off from the photoresist surface, which can reduce The viscosity of the small blue film further reduces the risk of the mirror layer falling off, effectively improving the yield of flip-chip light-emitting diodes.

Further, the light angle conversion layer is an AlN layer, the upper end diameter of the light angle conversion layer is between 7 μm and 11 μm, the lower end diameter is between 8 μm and 12 μm, and the thickness of the light angle conversion layer is between 0.5 μm and 5 μm. , the center distance between adjacent light angle conversion layers is twice the diameter of the lower end of the light angle conversion layer.

Further, the step of sequentially coating multiple layers of photoresist on the second ohmic contact layer and sequentially exposing the photoresist to form openings in the reflective layer specifically includes:

Coating a first positive photoresist on the light angle conversion layer, and using a first mask to perform a first exposure on the first positive photoresist;

Coating a first negative photoresist on the first positive photoresist, and using a second mask to perform a second exposure on the first negative photoresist;

Coating a second positive photoresist on the first negative photoresist, and using a third mask to perform a third exposure on the second positive photoresist;

A development process is used to remove the exposed first positive photoresist, the second positive photoresist and the unexposed first negative photoresist to form a first positive photoresist interconnected with each other. The reflective layer opening is composed of the resist opening, the first negative photoresist opening and the second positive photoresist opening.

Further, the cross section of the first positive photoresist opening is an inverted trapezoid, the cross section of the first negative photoresist opening is a positive trapezoid, and the cross section of the second positive photoresist opening is an inverted trapezoid, The upper end width of the first positive photoresist opening is greater than the lower end width of the first negative photoresist opening, and the upper end width of the first negative photoresist opening is equal to the second positive photoresist opening. The width of the lower end.

Further, the wavelength of the light used for the third exposure is greater than the wavelength of the light used for the second exposure.

Further, the step of sequentially depositing an Ag layer and a Ti layer on the surface of the uppermost photoresist specifically includes:

An Ag layer is deposited on the surface of the uppermost photoresist using an electron beam evaporation process. In the electron beam evaporation process, the plating pot revolves along the track, and at the same time, the plating pot rotates, and every 1/4 of the thickness of Ag is deposited. When layering, reversely adjust the direction of revolution of the plating pot and the direction of rotation of the plating pot;

A Ti layer is deposited on the Ag layer using an electron beam evaporation process. The thickness of the Ti layer is 1/10-1/8 of the thickness of the Ag layer;

Among them, in the electron beam evaporation process, the angle between the plating pot and the plane where the metal target is located is between 30° and 60°.

Further, the temperature for heating the substrate is between 150°C and 180°C.

Further, the step of depositing an insulating protective layer on the mirror layer specifically includes:

Depositing a first SiO ₂ film on the mirror layer using an electron beam evaporation method of SiO ₂ target material, the thickness of the first SiO ₂ film being between 100Å and 200Å;

A PECVD process is used to deposit a second SiO ₂ film on the first SiO ₂ film. The thickness of the second SiO ₂ film is between 5000Å and 20000Å. The insulating protective layer is composed of the first SiO ₂ film and the third SiO 2 film. Composed of two SiO ₂ films.

Further, after the step of preparing N-type insulating layer through-holes and P-type insulating layer through-holes on the insulating protective layer, the step also includes: using a dry etching process to sequentially pass in a gas containing Cl atoms and a gas containing Si. Atomic gas.

The invention also proposes a flip-chip light-emitting diode chip, which is prepared by the above-mentioned method for preparing a flip-chip light-emitting diode chip.

Description of the drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings in the following description are only illustrative of the present invention. For some embodiments, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a flow chart of the preparation method of the flip-chip light-emitting diode chip of the present invention;

Figure 2 is a schematic structural diagram corresponding to step S1 in Figure 1;

Figure 3 is a schematic structural diagram corresponding to step S2 in Figure 1;

Figure 4 is a schematic structural diagram corresponding to step S3 in Figure 1;

Figure 5 is a schematic structural diagram corresponding to step S4 in Figure 1;

Figure 6 is a schematic structural diagram corresponding to step S5 in Figure 1;

Figure 7 is a schematic structural diagram of applying the first positive photoresist and using the first mask to perform the first exposure in step S6 in Figure 1;

Figure 8 is a schematic structural diagram of applying the first negative photoresist and using the second mask to perform the second exposure in step S6 in Figure 1;

Figure 9 is a schematic structural diagram of applying the second positive photoresist and using the third mask to perform the third exposure in step S6 in Figure 1;

Figure 10 is a schematic structural diagram corresponding to removing the exposed photoresist using development in step S6 in Figure 1;

Figure 11 is an enlarged schematic diagram of part A in Figure 10;

Figure 12 is a schematic diagram of the corresponding structure of sequentially depositing an Ag layer and a Ti layer on the surface of the uppermost photoresist layer in step S7 in Figure 1;

Figure 13 is a schematic structural diagram corresponding to heating the substrate in step S7 in Figure 1;

Figure 14 is a schematic structural diagram of the removal of the photoresist and the Ag layer and Ti layer located on the surface of the photoresist in step S7 in Figure 1;

Figure 15 is a schematic structural diagram corresponding to step S8 in Figure 1;

Figure 16 is a schematic structural diagram corresponding to step S9 in Figure 1.

Explanation of reference symbols:

10. Substrate; 11. Epitaxial layer; 111. N-type GaN layer; 112. Quantum well layer; 113. P-type GaN layer; 114. Epitaxial layer recess; 115. Isolation trench; 12. First ohmic contact layer; 13 , light angle conversion layer; 14. second ohmic contact layer; 15. mirror layer; 151. first positive photoresist; 152. first mask; 153. first negative photoresist; 154. The second mask; 155, the second positive photoresist; 156, the third mask; 157, the first positive photoresist opening; 158, the first negative photoresist opening; 159, the second Positive photoresist opening; 1510, mirror sacrificial layer; 16, insulation protective layer; 161, P-type insulation layer through hole; 162, N-type insulation layer through hole; 171, P-type pad layer; 172, N-type pad layer.

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the drawings are exemplary and are intended to explain the embodiments of the present invention and are not to be construed as limitations of the present invention.

In the description of the embodiments of the present invention, it should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical" ", "horizontal", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for convenience and simplicity in describing the embodiments of the present invention. The description does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore is not to be construed as a limitation of the invention.

In addition, the terms “first” and “second” are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present invention, "plurality" means two or more than two, unless otherwise explicitly and specifically limited.

In the embodiments of the present invention, unless otherwise expressly stipulated and limited, the terms "installation", "connection", "connection", "fixing" and other terms should be understood in a broad sense. For example, it can be a fixed connection or a removable connection. Disassembly and connection, or integration; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two elements or an interaction between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

Referring to Figures 1 to 16, one embodiment of the present invention, a method for preparing a flip-chip light-emitting diode chip, includes the following steps:

S1: Provide a substrate 10, deposit the N-type GaN layer 111, the quantum well layer 112 and the P-type GaN layer 113 sequentially on the substrate 10 to form the epitaxial layer 11, and deposit the first ohm layer on the P-type GaN layer 113. contact layer 12;

Specifically, a MOCVD (Metal Organic Chemical Vapor Deposition) process is used to sequentially prepare a Si-doped N-type GaN layer 111, a periodically stacked InGaN/GaN quantum well layer 112, and an Mg-doped P-type GaN layer on the substrate 10. 113, to form the epitaxial layer 11, and then use magnetron sputtering technology to deposit an ITO film on the surface of the P-type GaN layer 113 as the first ohmic contact layer 12. The ratio of In ₂ O ₃ and SnO ₂ in the ITO film is between 85Wt%: 15Wt%-90Wt%:10Wt%, the thickness of the first ohmic contact layer 12 is between 80Å-120Å, and then the first rapid annealing is performed on the first ohmic contact layer 12, and the ratio of the first rapid annealing gas O ₂ to N ₂ is between 5 :1-10:1, the first rapid annealing temperature is between 500℃-600℃; in this embodiment, the ratio of In ₂ O ₃ and SnO ₂ in the ITO film is 90Wt%:10Wt%, the first ohmic contact layer 12 The thickness is 100Å, the ratio of O ₂ and N ₂ in the first rapid annealing gas is 6:1, and the first rapid annealing temperature is 550°C.

S2: Deposit a plurality of frustum-shaped light angle conversion layers 13 on the first ohmic contact layer 12; further, the light angle conversion layer 13 is an AlN layer, and the upper end diameter of the light angle conversion layer 13 is between 7 μm and 11 μm. The diameter of the lower end is between 8 μm and 12 μm, the thickness of the light angle conversion layer 13 is between 0.5 μm and 5 μm, and the center distance between adjacent light angle conversion layers 13 is twice the diameter of the lower end of the light angle conversion layer 13;

Specifically, a PVD (physical vapor deposition) method is used to prepare an AlN film on the surface of the first ohmic contact layer 12, and then a positive photoresist is coated on the AlN film using a pattern selection method, and then removed by exposure and development. Part of the photoresist is exposed to part of the AlN film, and then the exposed AlN film is etched with the first solution in the first reaction tank, and then the part located at the bottom of the remaining photoresist and the photoresistor is etched with the second solution in the second reaction tank. The AlN film in contact with the resist is then cleaned with deionized water in the third reaction tank. The first solution is 7%-9% tetramethylammonium hydroxide solution, and the second solution is 3%-5% tetramethylammonium hydroxide. ammonium hydroxide solution, and then remove the remaining photoresist to obtain the light angle conversion layer 13. Because the concentration of the second solution is less than the concentration of the first solution, a frustum-shaped light angle conversion layer 13 can be obtained. By controlling the first solution and The difference in concentration of the second solution can control the diameter of the upper and lower ends of the light angle conversion layer 13;

Let the diameter of the side of the light angle conversion layer 13 in contact with the surface of the first ohmic contact layer 12 be a, the diameter of the side facing away from the first ohmic contact layer 12 be b, the thickness of the light angle conversion layer 13 be c, and two adjacent light The center distance of the angle conversion layer 13 is d, where a>b and (ab)/2 is between -/> /3, d=2a, a is between 8μm-12μm, b is between 7μm-11μm, c is between 0.5μm-5μm, the light angle conversion layer 13 can enable the subsequent mirror layer 15 to be placed on the light angle conversion layer 13 A trapezoidal sloping mesa is formed. The part of the light emitted by the epitaxial layer 11 and the substrate 10 has a smaller acute angle. It is reflected by the trapezoidal sloping mesa and is converted into the light rays having a larger acute angle with the substrate 10, thus reducing the The total reflection of light propagating between each layer of materials improves the brightness of the flip-chip light-emitting diode chip; in this embodiment, the first solution is 8% tetramethylammonium hydroxide solution, and the second solution is 4% tetramethylammonium hydroxide. Ammonium hydroxide solution; the value of a is 10 μm, the value of b is 9 μm, and the value of c is 2 μm.

S3: Deposit the second ohmic contact layer 14 on the first ohmic contact layer 12; wherein, the lower end of the second ohmic contact layer 14 is in contact with the first ohmic contact layer 12, and the second ohmic contact layer 14 has a light angle conversion Multiple through holes corresponding to layer 13, and the aperture of the through holes is larger than the diameter of the lower end of the light angle conversion layer 13;

Specifically, a negative photoresist is coated on the surface of the first ohmic contact layer 12 and the light angle conversion layer 13, and then exposed and developed to remove part of the photoresist, exposing part of the first ohmic contact layer 12, and then using an electron beam. The evaporation process evaporates an ITO film on the surface of the remaining photoresist and the exposed first ohmic contact layer 12, and then uses a blue film stripping process to remove the ITO film on the remaining photoresist, and then removes the remaining photoresist. A second ohmic contact layer 14 is formed on the first ohmic contact layer 12 between the light angle conversion layers 13, and then the second ohmic contact layer 14 is subjected to a second rapid annealing using O ₂ and N ₂ gases. The ratio is the same as the first rapid annealing gas ratio, and is between 5:1-10:1. The second rapid annealing temperature is smaller than the first rapid annealing temperature, and is between 400℃-500℃; In in the second ohmic contact layer 14 The ratio of ₂ O ₃ and SnO ₂ is between 92Wt%:8Wt%-97Wt%:3Wt%, the thickness of the second ohmic contact layer 14 is between 100Å-600Å, and the second ohmic contact layer 14 is close to the edge distance of the light angle conversion layer 13 The distance e between the edges of the light angle conversion layer 13 is between 1 μm and 2 μm, that is, the diameter of the through hole on the second ohmic contact layer 14 is 1 μm and 2 μm larger than the diameter of the lower end of the light angle conversion layer 13; in this embodiment, the second fast The annealing temperature is 450°C, the ratio of In ₂ O ₃ and SnO ₂ in the second ohmic contact layer 14 is 95Wt%:5Wt%, the thickness of the second ohmic contact layer 14 is 300Å, and the second ohmic contact layer 14 is close to the light angle conversion The distance e from the edge of the layer 13 to the edge of the light angle conversion layer 13 is 1.5 μm.

S4: Prepare an epitaxial layer recess 114 at the edge of the second ohmic contact layer 14, and the bottom surface of the epitaxial layer recess 114 is the N-type GaN layer 111; specifically:

Coat positive photoresist on the second ohmic contact layer 14 and the light angle conversion layer 13 and the first ohmic contact layer 12 that is not covered by the second ohmic contact layer 14 and the light angle conversion layer 13, and then expose and develop to remove the part. At the edge of the substrate, it is necessary to prepare a photoresist above the recessed portion 114 of the epitaxial layer, exposing the second ohmic contact layer 14 under this part of the photoresist, and then use an ITO etching solution to etch away the exposed second ohmic contact layer 14 and The first ohmic contact layer 12 under this part of the second ohmic contact layer 14 exposes part of the epitaxial layer 11, and then uses an inductively coupled plasma etching process to etch the exposed epitaxial layer 11, and remove part of the epitaxial layer 11 until it is exposed. The N-type GaN layer 111 is removed to form the epitaxial layer recess 114, and then the photoresist is removed. The epitaxial layer recess 114 forms an electrical connection with the subsequently prepared N-type pad layer 172 as a current output terminal.

S5: Etch the edge of the epitaxial layer recess 114 to form an isolation trench 115; specifically:

Coat positive photoresist on the second ohmic contact layer 14 and the light angle conversion layer 13 and the first ohmic contact layer 12 and the epitaxial layer recess 114 that are not covered by the second ohmic contact layer 14 and the light angle conversion layer 13, and then expose Develop and remove part of the photoresist located at the edge of the substrate 10 in the epitaxial layer concave portion 114 to expose the underlying epitaxial layer concave portion 114 , and then use an inductively coupled plasma etching process to remove the exposed epitaxial layer concave portion 114 to form an isolation trench 115 , and then remove the photoresist. The isolation groove 115 can prevent the solder paste from connecting with the N-type GaN layer 111 when the flip-chip LED chip is subsequently welded to the lighting board, causing a short circuit in the flip-chip LED chip.

S6: Coat multiple layers of photoresist on the second ohmic contact layer 14 in sequence, and expose the photoresist in sequence to form a reflective layer opening. The reflective layer opening has a structure with a wide lower end and a narrow upper end; further, in the third The steps of sequentially coating multiple layers of photoresist on the two-ohm contact layer 14 and sequentially exposing the photoresists to form openings in the reflective layer include: coating a first positive photoresist 151 on the light angle conversion layer 13 , using the first mask 152 to perform the first exposure on the first positive photoresist 151; coating the first negative photoresist 153 on the first positive photoresist 151, using the second mask 154 Perform a second exposure on the first negative photoresist 153; apply a second positive photoresist 155 on the first negative photoresist 153, and use a third mask 156 to expose the second positive photoresist 155 for the third exposure; a developing process is used to remove the exposed first positive photoresist 151, the second positive photoresist 155 and the unexposed first negative photoresist 153, forming a first interconnected The reflective layer opening is composed of the positive photoresist opening 157, the first negative photoresist opening 158 and the second positive photoresist opening 159;

Wherein, the cross section of the first positive photoresist opening 157 is an inverted trapezoid, the cross section of the first negative photoresist opening 158 is a positive trapezoid, the cross section of the second positive photoresist opening 159 is an inverted trapezoid, and the cross section of the first positive photoresist opening 159 is an inverted trapezoid. The upper end width of the photoresist opening 157 is greater than the lower end width of the first negative photoresist opening 158, and the upper end width of the first negative photoresist opening 158 is equal to the lower end width of the second positive photoresist opening 159; third The wavelength of light used for the exposure is greater than the wavelength of light used for the second exposure.

Specifically, a plasma cleaning process is first used to clean the second ohmic contact layer 14 and the light angle conversion layer 13 as well as the surfaces of the first ohmic contact layer 12 and the epitaxial layer recess 114 that are not covered by the second ohmic contact layer 14 and the light angle conversion layer 13. The plasma cleaning process specifically involves introducing argon gas into the reaction chamber, then turning on radio frequency power ionization, introducing oxygen, so that the ionized oxygen ions clean the wafer surface, and then introducing nitrogen gas so that the ionized nitrogen ions continue to clean the wafer surface. The flow ratio of argon, oxygen, and nitrogen is 1:5:5, the argon flow is between 20 sccm-30 sccm, the oxygen and nitrogen flow is between 100 sccm-150 sccm, and the radio frequency power is between 50W-500W; in this embodiment, the argon flow is is 25sccm, the oxygen and nitrogen flow is 120sccm, and the RF power is 200W;

The first positive layer is coated on the surface of the second ohmic contact layer 14 and the light angle conversion layer 13 and the first ohmic contact layer 12 and the epitaxial layer recess 114 and the isolation groove 115 that are not covered by the second ohmic contact layer 14 and the light angle conversion layer 13 . Photoresist 151, and then use the first mask 152 to perform the first exposure; the viscosity of the first positive photoresist 151 is between 30CPS-50CPS, and the thickness is 2 times to 10 times the thickness of the subsequently prepared mirror layer 15. The opening width of the first mask 152 is f, the first exposure energy is between 200mj/cm²-230mj/cm², and the first exposure time is between 0.4S-0.6S; in this embodiment, the first positive photoresist 151 The viscosity is 40CPS, the thickness is 5 times the thickness of the subsequently prepared mirror layer 15, the first exposure energy is 210mj/cm², and the first exposure time is 0.5S;

Coat the first negative photoresist 153 on the first positive photoresist 151, and then use the second mask 154 to perform a second exposure. The first negative photoresist 153 is located above the second ohmic contact layer 14. The thickness of the portion is 5 to 10 times the thickness of the portion of the first positive photoresist 151 located above the second ohmic contact layer 14 , the viscosity of the first negative photoresist 153 is between 200CPS and 240CPS, and the second exposure energy is between 300mj/cm²-350mj/cm², the second exposure time is between 0.6S-0.8S; the width of the unopened area of the second mask 154 is g; in this embodiment, the thickness of the first negative photoresist 153 is 8 times the thickness of the positive photoresist 151, the viscosity of the first negative photoresist 153 is 220CPS, the second exposure energy is 330mj/cm², and the second exposure time is 0.7S;

Coat the second positive photoresist 155 on the first negative photoresist 153, and then use the third mask 156 to perform a third exposure. The thickness of the second positive photoresist 155 is the thickness of the first negative photoresist. The viscosity of the second positive photoresist 155 is between 150CPS and 200CPS, the third exposure energy is between 250mj/cm² and 300mj/cm², and the third exposure time is between 0.8S and 1.0S. The opening width of the third mask plate 156 is consistent with the width of the unopened area of the second mask plate 154, both are g; and the wavelength of the light used in the third exposure is greater than the wavelength of the light used in the second exposure, so as to avoid the need for the third exposure. The first negative photoresist 153 is damaged during exposure, causing the first negative photoresist 153 to be incompletely developed; in this embodiment, the thickness of the second positive photoresist 155 is equal to that of the first negative photoresist 153 2 times, the viscosity of the second positive photoresist 155 is 180CPS, the third exposure energy is 280mj/cm², and the third exposure time is 0.9S;

The exposed first positive photoresist 151 and the second positive photoresist 155 as well as the unexposed first negative photoresist 153 are removed using development to form the first positive photoresist opening 157 and the first positive photoresist 157 . The negative photoresist opening 158 and the second positive photoresist opening 159. The specific development method is to soak the wafer in a reaction tank equipped with a developer for 5S-10S, and then immerse it in a reaction tank equipped with deionized water. Flush and clean for 120S-180S, and then repeat the above two actions twice; in this example, the wafer is soaked in a reaction tank equipped with developer for 8S, and then flushed and cleaned for 150S in a reaction tank equipped with deionized water. ;

The cross-section of the obtained first positive photoresist opening 157 is an inverted trapezoid, and the opening width close to the substrate 10 is equal to the opening width f of the first mask plate 152. The slope of the inverted trapezoid of the first positive photoresist opening 157 is The acute angle α between the edge and the upper plane of the substrate 10 is between 75° and 85°. The cross-section of the first negative photoresist opening 158 is a positive trapezoid, and the width of the opening away from the substrate 10 is equal to the second mask plate 154 The unopened width g, the acute angle β between the hypotenuse of the positive trapezoid of the first negative photoresist opening 158 and the upper end plane of the substrate 10 is between 20° and 45°, and the angle β of the second positive photoresist opening 159 is The cross-section is an inverted trapezoid, and the width of the opening close to the substrate 10 is equal to the opening width g of the third mask plate 156. The hypotenuse of the inverted trapezoid of the second positive photoresist opening 159 and the upper end plane of the substrate 10 form an acute angle γ. Between 60°-85°; in this embodiment, the α angle is 80°, the β angle is 30°, and the γ angle is 70°.

S7: sequentially deposit the Ag layer and the Ti layer on the surface of the uppermost photoresist, heat the substrate 10, and remove the photoresist and the Ag layer and Ti layer on the surface of the photoresist to form the mirror layer 15; further The steps of sequentially depositing an Ag layer and a Ti layer on the surface of the uppermost photoresist specifically include: using an electron beam evaporation process to deposit an Ag layer on the surface of the uppermost photoresist, in which the edge of the plating pot in the electron beam evaporation process The orbit revolves and the plating pot rotates at the same time. Every time a 1/4 thick Ag layer is deposited, the direction of revolution of the plating pot and the direction of rotation of the plating pot are reversely adjusted; the Ag layer is deposited using an electron beam evaporation process. Ti layer, the thickness of the Ti layer is 1/10 times to 1/8 times the thickness of the Ag layer; in the electron beam evaporation process, the angle between the plating pot and the plane where the metal target is located is between 30° and 60° °; further, the temperature for heating the substrate is between 150°C and 180°C.

Specifically, the second ohmic contact layer 14 and the light angle conversion layer 13 exposed on the remaining surface of the second positive photoresist 155 and the opening of the reflective layer and the parts not covered by the second ohmic contact layer 14 and the light angle conversion layer 13 An Ag layer and a Ti layer are sequentially evaporated on the surface of the first ohmic contact layer 12 using an electron beam evaporation process. The Ag layer and the Ti layer placed on the surface of the second positive photoresist 155 are the mirror sacrificial layers 1510. The Ag layer and Ti layer placed on the surface of the second ohmic contact layer 14 and the light angle conversion layer 13 exposed by the opening of the reflective layer and the first ohmic contact layer 12 that are not covered by the second ohmic contact layer 14 and the light angle conversion layer 13 are: Reflector layer 15;

The thickness of the Ti layer is 1/10 times to 1/8 times the thickness of the Ag layer, and the thickness of the Ag layer is between 1200Å and 5000Å; the electron beam evaporation process is to evaporate the wafer that needs to evaporate metal in an evaporation chamber. Attached to the plating pot, the plating pot then revolves along the track, and the plating pot performs self-propagation at the same time. During the rotation of the plating pot, high-energy electron beams are used to bombard the metal target to evaporate the metal onto the wafer. The process of evaporating the Ag layer in the present invention , first evaporate a 1/4 thickness Ag layer. During this evaporation process, the plating pot revolves clockwise along the track, and the plating pot also rotates clockwise. Then, a 1/4 thickness Ag layer is evaporated. During this evaporation process The plating pot revolves counterclockwise along the orbit, and the plating pot also rotates counterclockwise, and then continues to evaporate a 1/4 thickness Ag layer. During this evaporation process, the plating pot revolves clockwise along the orbit, and the plating pot also rotates clockwise; and then continues Evaporate 1/4 of the thickness of the Ag layer. During this evaporation process, the plating pot revolves counterclockwise along the track, and the plating pot also rotates counterclockwise. In this way, there are four evaporation processes in total, and the entire Ag layer is evaporated. The plating pot is changed repeatedly in this way. The direction of revolution and self-propagation can improve the uniformity of the thickness of Ag metal on the wafer; the electron beam power in the four processes of evaporating Ag metal is the same, all between 120W and 160W; in the process of evaporating Ti metal in the present invention, the plating pot The plating pot rotates clockwise along the orbit, and the electron beam power during the evaporation of Ti metal is between 150W and 200W. In the above four processes of evaporation of Ag metal and the process of evaporation of Ti metal, the plating pot and the metal The angles between the target planes are the same, both are θ, and θ is between 30° and 60°. This angle can ensure that the Ag metal is evaporated to the first positive photoresist opening below the first negative photoresist opening 158 Within 157; after evaporation, the distance between the edge of the mirror layer 15 and the edge of the first positive photoresist 151 is h, and h≤(f-g)/2; in this embodiment, the thickness of the Ti layer is Ag 1/8 times the thickness of the layer, the thickness of the Ag layer is 3000Å; the electron beam power during the evaporation of Ag metal is 140W; the electron beam power during the evaporation of Ti metal is 180W; θ is 45°.

Then, the flip-chip light-emitting diode is placed on a baking plate, the substrate 10 is in contact with the baking plate, and then the baking plate is heated to 150°C-180°C and maintained at this temperature for 180S-240S. This process starts from the bottom of the substrate 10 Facing the flip-chip light-emitting diode chip, the first positive photoresist 151, the first negative photoresist 153 and the second positive photoresist 155 are softened, so that the first positive photoresist opening 157, the second positive photoresist 157 and the second positive photoresist 157 are softened. The first negative photoresist opening 158 and the second positive photoresist opening 159 collapse, completely covering the edge of the mirror layer 15 to prevent the mirror layer 15 from falling off when the subsequent blue film is peeled off, and the second positive photoresist The opening 159 collapses, causing a gap to form between the edge of the mirror sacrificial layer 1510 and the surface of the second positive photoresist 155, making it easier for the mirror sacrificial layer 1510 to fall off from the surface of the second positive photoresist 155, thus reducing blue The viscosity of the film further reduces the risk of the mirror layer 15 falling off; in this embodiment, the baking plate is heated to 180°C and maintained at this temperature for 210S;

Finally, the blue film stripping process is used to peel off the mirror sacrificial layer 1510 located on the second positive photoresist 155, and then the remaining first positive photoresist 151 and the first negative photoresist are removed using a glue stripper. 153 and the second positive photoresist 155, the preparation of the mirror layer 15 is completed.

S8: Deposit an insulating protective layer 16 on the reflective mirror layer 15, and prepare N-type insulating layer through holes 162 and P-type insulating layer through holes 161 on the insulating protective layer 16; further, deposit an insulating protective layer on the reflective mirror layer 15. Step 16 specifically includes: using an electron beam evaporation SiO ₂ target method to deposit a first SiO ₂ film on the mirror layer 15, with a thickness of the first SiO ₂ film ranging from 100Å to 200Å; using a PECVD process to deposit a first SiO ₂ film on the mirror layer 15 A second SiO ₂ film is deposited on the film. The thickness of the second SiO ₂ film is between 5000Å and 20000Å. The insulating protective layer 16 is composed of the first SiO ₂ film and the second SiO ₂ film; further, N is prepared on the insulating protective layer 16 After the steps of the type insulating layer through hole 162 and the P type insulating layer through hole 161, it also includes: using a dry etching process to sequentially pass in the gas containing Cl atoms and the gas containing Si atoms.

Specifically: the first SiO ₂ film is prepared by electron beam evaporation of SiO ₂ target material on the surface of the mirror layer 15 and the epitaxial layer recess 114 and the isolation groove 115, and then filled using the PECVD (Plasma Enhanced Chemical Vapor Deposition) process. SiH ₄ and N ₂ O prepare a second SiO ₂ film on the surface of the first SiO ₂ film. The thickness of the first SiO ₂ film is much smaller than the thickness of the second SiO ₂ film. The thickness of the first SiO ₂ film is between 100Å-200Å. The thickness of the SiO ₂ film is between 5000Å and 20000Å, because oxygen ions are involved in the process of preparing the SiO ₂ film by PECVD. If the SiO ₂ film is directly prepared by the PECVD process on the surface of the mirror layer 15, oxygen ions will oxidize the mirror layer. The problem with Ag metal is that the SiO ₂ film evaporated by the electron beam evaporation process does not involve the participation of oxygen ions, but the side coverage of the SiO ₂ film evaporated by the electron beam evaporation process is very poor, such as the epitaxial layer recess 114 and isolation. The side of the groove 115 needs to be covered and protected by the SiO ₂ film, so the present invention first uses the electron beam evaporation process to prepare an extremely thin SiO ₂ film to protect the mirror layer 15, and then uses the PECVD process to prepare a thicker second SiO ₂ film , which not only prevents the mirror layer 15 from being oxidized, but also protects the epitaxial layer recess 114 and the side surfaces of the isolation trench 115. The first SiO ₂ film and the second SiO ₂ film together constitute the insulating protective layer 16; in this embodiment, the first The thickness of the SiO ₂ film is 150Å, and the thickness of the second SiO ₂ film is 10000Å;

Coat a positive photoresist on the surface of the insulating protective layer 16, then expose and develop to remove part of the photoresist, exposing part of the insulating protective layer 16, and then use a first dry etching process to remove the exposed insulating protective layer. 16. Form the N-type insulating layer through-hole 162 and the P-type insulating layer through-hole 161, and use the second dry etching process to repair the surface of the epitaxial layer recess 114 below the N-type insulating layer through-hole 162 damaged by the first dry etching. Then remove the photoresist; because the gas introduced during the first dry etching process is a gas containing F atoms that can react with SiO ₂ , but at the same time, the gas containing F atoms will also interact with the N-type insulating layer through hole 162 The Si atoms doped on the surface of the epitaxial layer concave portion 114 below react, causing the surface resistance of the epitaxial layer concave portion 114 to increase, causing the voltage of the flip-chip light-emitting diode chip to increase. Therefore, the present invention uses the second dry etching process after the first dry etching is completed. The dry etching process repairs the surface of the epitaxial layer recess 114 below the N-type insulating layer through hole 162 damaged by the first dry etching process. The second dry etching process specifically involves first passing in a gas containing Cl atoms to separate it from the damage. The GaN material on the surface of the epitaxial layer concave part 114 reacts to take away the damaged GaN material, and then the gas containing Si atoms is passed into the epitaxial layer concave part 114 for ion implantation, and the epitaxial layer concave part 114 is doped again to reduce the epitaxial layer concave part. Resistivity of 114.

S9: Deposit the N-type pad layer 172 and the P-type pad layer 171 on the insulating protective layer 16. The N-type pad layer 172 is connected to the N-type GaN layer 111 through the N-type insulating layer through hole 162. The P-type pad layer 171 is connected to the mirror layer 15 through the P-type insulation layer through hole 161;

Specifically, a negative photoresist is coated on the surface of the insulation protective layer 16 and the N-type insulation layer through hole 162 and the P-type insulation layer through hole 161, and then the first metal layer and the second metal layer are sequentially evaporated using an electron beam evaporation process. Metal layer, third metal layer, the first metal layer is close to the insulating protective layer 16, the third metal layer is away from the insulating protective layer 16, the second metal layer is between the first metal layer and the second metal layer, the first metal layer is a Ni layer. The Ni layer contacts the mirror layer 15 in the P-type insulating layer through hole 161, which can well prevent the Ag metal from migrating outward. The second metal layer can be a Cr layer, a Ti layer, a Pt layer, or a Pb layer. One or a combination of them, the second metal layer is used to adjust stress, the third metal layer can be one of Au layer, Sn layer, AuSn layer, SnCu layer, SnAgCu layer, the third metal is used for subsequent connection with the circuit board The bonding connection, the first metal layer, the second metal layer, and the third metal layer together constitute the pad layer. The pad layer includes a P-type pad layer 171 and an N-type pad layer 172. The P-type pad layer 171 passes The P-type insulation layer through hole 161 is electrically connected to the mirror layer 15 , and the N-type pad layer 172 is electrically connected to the epitaxial layer recess 114 through the N-type insulation layer through hole 162 .

In a method for preparing a flip-chip LED chip according to an embodiment of the present invention, the light angle conversion layer 13 is provided so that the mirror layer 15 subsequently deposited on the light angle conversion layer 13 forms a trapezoidal sloped mesa, and the epitaxial layer 11 emits light The light rays that have a smaller acute angle with the substrate 10 are converted into light rays that have a larger acute angle with the substrate 10 through the reflection of the trapezoidal slope table, thereby reducing the total reflection of light propagating between each layer of materials. , improve the brightness of the flip-chip light-emitting diode chip; by heating the substrate 10, the photoresist softens and collapses, and the edges of the Ag layer and Ti layer deposited in the opening of the reflective layer are completely covered, reducing the reflective mirror layer when the subsequent blue film is peeled off. 15 risk of falling off, and the top layer of photoresist and the Ag layer and Ti layer on the surface of the photoresist will collapse to form a gap as the photoresist softens, making it easier for the Ag layer and Ti layer on the surface of the photoresist to be removed from the photolithography The glue surface is peeled off, which can reduce the viscosity of the blue film, further reduce the risk of the mirror layer 15 falling off, and effectively improve the yield of flip-chip light-emitting diodes.

The invention also proposes a flip-chip light-emitting diode chip, which is prepared by using the above method for preparing a flip-chip light-emitting diode chip.

In the description of this specification, reference to the terms "one embodiment," "some embodiments," "an example," "specific examples," or "some examples" or the like means that specific features are described in connection with the embodiment or example. , structures, materials or features are included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

On the premise that no conflict occurs, those skilled in the art can freely combine and superimpose the above additional technical features.

The above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention shall be included in the protection of the present invention. within the range.

Claims (10)

1. A method for preparing a flip-chip light-emitting diode chip, which is characterized by comprising the following steps: Provide a substrate, deposit an N-type GaN layer, a quantum well layer and a P-type GaN layer sequentially on the substrate to form an epitaxial layer, and deposit a first ohmic contact layer on the P-type GaN layer; depositing a plurality of frustum-shaped optical angle conversion layers on the first ohmic contact layer; A second ohmic contact layer is deposited on the first ohmic contact layer, wherein the lower end of the second ohmic contact layer is in contact with the first ohmic contact layer, and the second ohmic contact layer has a A plurality of through holes corresponding to the light angle conversion layer, and the aperture of the through holes is larger than the diameter of the lower end of the light angle conversion layer; An epitaxial layer recess is prepared at the edge of the second ohmic contact layer, and the bottom surface of the epitaxial layer recess is the N-type GaN layer; Perform an etching process on the edge of the recessed portion of the epitaxial layer to form an isolation trench; Apply multiple layers of photoresist on the second ohmic contact layer in sequence, and expose the photoresist in sequence to form a reflective layer opening, where the reflective layer opening has a structure with a wide lower end and a narrow upper end; An Ag layer and a Ti layer are sequentially deposited on the surface of the uppermost photoresist, the substrate is heated, and the photoresist and the Ag layer and Ti layer located on the surface of the photoresist are removed to form a reflection mirror layer; Deposit an insulating protective layer on the mirror layer, and prepare N-type insulating layer through holes and P-type insulating layer through holes on the insulating protective layer; An N-type pad layer and a P-type pad layer are deposited on the insulating protective layer. The N-type pad layer is connected to the N-type GaN layer through the N-type insulating layer through hole. The P-type bonding layer The disk layer is connected to the mirror layer through the P-type insulation layer through hole. 2. The method for preparing a flip-chip light-emitting diode chip according to claim 1, wherein the light angle conversion layer is an AlN layer, the upper end diameter of the light angle conversion layer is between 7 μm and 11 μm, and the lower end diameter is between 7 μm and 11 μm. The thickness of the light angle conversion layer is between 0.5 μm and 5 μm, and the center distance between adjacent light angle conversion layers is twice the diameter of the lower end of the light angle conversion layer. 3. The method for preparing a flip-chip light-emitting diode chip according to claim 1, characterized in that: sequentially coating multiple layers of photoresist on the second ohmic contact layer, and sequentially coating the photoresist The steps of exposing to form openings in the reflective layer specifically include: Coating a first positive photoresist on the light angle conversion layer, and using a first mask to perform a first exposure on the first positive photoresist; Coating a first negative photoresist on the first positive photoresist, and using a second mask to perform a second exposure on the first negative photoresist; Coating a second positive photoresist on the first negative photoresist, and using a third mask to perform a third exposure on the second positive photoresist; A development process is used to remove the exposed first positive photoresist, the second positive photoresist and the unexposed first negative photoresist to form a first positive photoresist interconnected with each other. The reflective layer opening is composed of the resist opening, the first negative photoresist opening and the second positive photoresist opening. 4. The method for preparing a flip-chip light-emitting diode chip according to claim 3, wherein the cross-section of the first positive photoresist opening is an inverted trapezoid, and the cross-section of the first negative photoresist opening is It is a positive trapezoid, the cross-section of the second positive photoresist opening is an inverted trapezoid, the upper end width of the first positive photoresist opening is greater than the lower end width of the first negative photoresist opening, and the first negative photoresist opening has a positive trapezoid shape. The upper end width of the positive photoresist opening is equal to the lower end width of the second positive photoresist opening. 5. The method for manufacturing a flip-chip light-emitting diode chip according to claim 3, wherein the wavelength of the light used for the third exposure is greater than the wavelength of the light used for the second exposure. 6. The method for preparing a flip-chip light-emitting diode chip according to claim 1, wherein the step of sequentially depositing an Ag layer and a Ti layer on the surface of the uppermost photoresist specifically includes: An Ag layer is deposited on the surface of the uppermost photoresist using an electron beam evaporation process. In the electron beam evaporation process, the plating pot revolves along the track, and at the same time, the plating pot rotates, and every 1/4 of the thickness of Ag is deposited. When layering, reversely adjust the direction of revolution of the plating pot and the direction of rotation of the plating pot; A Ti layer is deposited on the Ag layer using an electron beam evaporation process. The thickness of the Ti layer is 1/10-1/8 of the thickness of the Ag layer; Among them, in the electron beam evaporation process, the angle between the plating pot and the plane where the metal target is located is between 30° and 60°. 7. The method for manufacturing a flip-chip light-emitting diode chip according to claim 1, wherein the temperature for heating the substrate is between 150°C and 180°C. 8. The method for preparing a flip-chip light-emitting diode chip according to claim 1, wherein the step of depositing an insulating protective layer on the mirror layer specifically includes: Depositing a first SiO ₂ film on the mirror layer using an electron beam evaporation method of SiO ₂ target material, the thickness of the first SiO ₂ film being between 100Å and 200Å; A PECVD process is used to deposit a second SiO ₂ film on the first SiO ₂ film. The thickness of the second SiO ₂ film is between 5000Å and 20000Å. The insulating protective layer is composed of the first SiO ₂ film and the third SiO 2 film. Composed of two SiO ₂ films. 9. The method for preparing a flip-chip light-emitting diode chip according to claim 1, wherein after the step of preparing N-type insulating layer through holes and P-type insulating layer through holes on the insulating protective layer, It includes: using a dry etching process to sequentially pass in gas containing Cl atoms and gas containing Si atoms. 10. A flip-chip light-emitting diode chip, characterized in that it is prepared by the method for preparing a flip-chip light-emitting diode chip according to any one of claims 1 to 9.