CN114551680A - Flip light-emitting diode chip and preparation method thereof - Google Patents

Abstract

The invention discloses a flip-chip light emitting diode chip and a preparation method thereof, wherein the method comprises the following steps: etching the epitaxial layer and the Mesa step to the substrate to obtain a cutting channel, wherein an acute included angle formed between the side surface of the epitaxial layer at the cutting channel and the top surface of the substrate is 40-80 degrees; growing a current barrier layer on the epitaxial layer; growing a current extension layer on the epitaxial layer and covering the current barrier layer; respectively preparing N-type conductive metal and P-type conductive metal on the Mesa step and the current expansion layer; preparing a Bragg reflection layer on the N-type conductive metal, the P-type conductive metal and the current expansion layer, and etching the Bragg reflection layer to obtain an N-type conductive through hole and a P-type conductive through hole; and preparing an N-type bonding metal corresponding to the N-type conductive metal and a P-type bonding metal corresponding to the P-type conductive metal on the Bragg reflection layer. The invention can increase the transverse distance between the substrate and the epitaxial layer at the cutting path under the condition of not reducing the area of a light emitting area of the chip and not increasing the size of the chip.

Description

A flip-chip light-emitting diode chip and preparation method thereof

technical field

The invention relates to the technical field of chips, in particular to a flip-chip light emitting diode chip and a preparation method.

Background technique

Light-emitting diodes are widely used in general lighting, special lighting, landscape lighting, plant lighting, outdoor display, indoor display, liquid crystal display, vehicle lighting, vehicle display due to their advantages of energy saving, high brightness, high durability, long life and light weight. and other fields. At present, flip-chip LEDs can be used stably at high power, with high external quantum efficiency, and their applications are gradually mature.

However, the lateral distance between the substrate and the epitaxial layer at the cutting track of the existing flip-chip LED chip is relatively narrow, which affects the cutting yield, and the sidewall leakage is prone to occur after the chip is solidified. Generally, the area of the light-emitting area of the chip is reduced or increased. The chip size method increases the lateral distance between the substrate and the epitaxial layer at the dicing line, and the above solution loses the chip performance and increases the chip cost at the same time.

SUMMARY OF THE INVENTION

In view of the deficiencies of the prior art, the purpose of the present invention is to provide a flip-chip light-emitting diode chip and a preparation method, which can increase the size of the substrate at the dicing line and increase the size of the chip without reducing the area of the light-emitting area of the chip and increasing the size of the chip. Lateral distance of the epitaxial layer.

One aspect of the present invention is to provide a method for preparing a flip-chip light-emitting diode chip for preparing the flip-chip light-emitting diode chip, the method comprising:

providing a substrate;

growing an epitaxial layer on the substrate, and etching the epitaxial layer to expose the Mesa steps;

The epitaxial layer and the Mesa steps are etched and etched to the substrate to etch to obtain a scribe line, wherein the side surface of the epitaxial layer and the top surface of the substrate at the scribe line are located. The acute angle formed between them is 40°-80°;

growing a current blocking layer on the epitaxial layer;

growing a current spreading layer on the epitaxial layer and covering the current blocking layer;

respectively preparing N-type conductive metal and P-type conductive metal on the Mesa step and the current spreading layer;

preparing a Bragg reflection layer on the N-type conductive metal, the P-type conductive metal and the current spreading layer, and etching the Bragg reflection layer to obtain N-type conductive vias and P-type conductive vias;

An N-type bonding metal corresponding to the N-type conductive metal and a P-type bonding metal corresponding to the P-type conductive metal are prepared on the Bragg reflection layer, so that the N-type bonding metal passes through all the The N-type conductive through hole is electrically connected to the N-type conductive metal, and the P-type bonding metal is electrically connected to the P-type conductive metal through the P-type conductive through hole.

According to an aspect of the above technical solution, the epitaxial layer and the Mesa steps are etched and etched to the substrate, and in the step of obtaining a scribe line by etching, the etching process is inductively coupled plasma etching eclipse.

According to one aspect of the above technical solution, the epitaxial layer and the Mesa steps are etched and etched to the substrate to obtain a scribe line by etching, which specifically includes:

Coat photoresist on the surface of the epitaxial layer and the Mesa step;

Hot plate baking is performed on the epitaxial layer and the Mesa steps after gluing;

The epitaxial layer and the Mesa steps are patterned by photolithography;

Carrying out pre-development baking, development, post-development baking and oven baking on the epitaxial layer and the Mesa steps;

Inductively coupled plasma etching is performed on the epitaxial layer, and the etching selectivity ratio is 0.6-1, so as to obtain a scribe line by etching, and remove the photoresist remaining on the epitaxial layer and the Mesa steps.

According to an aspect of the above technical solution, in the step of etching the epitaxial layer and the Mesa steps to the substrate to obtain a scribe line by etching, the side surface of the epitaxial layer at the scribe line is The acute angle formed with the top surface of the substrate is 50°.

According to one aspect of the above technical solution, the epitaxial layer and the Mesa steps are etched and etched to the substrate to obtain a scribe line by etching, which specifically includes:

Coat photoresist on the surface of the epitaxial layer and the Mesa steps, and then bake on a hot plate with glue coating at a temperature of 120°C and a time of 150s;

Exposure is carried out with a photomask, and the exposure energy is 1000mj/cm ² ;

The epitaxial layer and the Mesa steps are developed, and the development time is 200s; the post-hot plate is baked, and the baking temperature is 80°C and the time is 40s;

Baking the epitaxial layer and the Mesa steps in an oven with a baking temperature of 70° C. and a time of 20 minutes;

Inductively coupled plasma etching is performed on the epitaxial layer and the Mesa steps, and the etching selectivity ratio is 0.85, and the photoresist remaining on the epitaxial layer and the Mesa steps is removed;

After the dicing lines are prepared through the above steps, the acute included angle formed between the side surfaces of the epitaxial layer and the top surface of the substrate at the dicing lines is 50°.

According to an aspect of the above technical solution, in the step of etching the epitaxial layer and the Mesa steps to the substrate to obtain a scribe line by etching, the side surface of the epitaxial layer at the scribe line is The acute angle formed with the top surface of the substrate is 65°.

According to one aspect of the above technical solution, the epitaxial layer and the Mesa steps are etched and etched to the substrate to obtain a scribe line by etching, which specifically includes:

Coat photoresist on the surface of the epitaxial layer and the Mesa step, and then bake it on a hot plate with glue coating at a temperature of 110°C and a time of 120s;

Exposure is carried out with a photomask, and the exposure energy is 300mj/cm ² ;

Baking the epitaxial layer and the Mesa steps before developing, with a baking temperature of 115° C. and a time of 100 s, and developing the epitaxial layer for 80 s;

Inductively coupled plasma etching is performed on the epitaxial layer and the Mesa steps, and the etching selection ratio is 0.7, and the residual photoresist on the epitaxial layer and the Mesa steps is removed;

After the dicing lines are prepared through the above steps, the acute included angle formed between the side surfaces of the epitaxial layer and the top surface of the substrate at the dicing lines is 65°.

Another aspect of the present invention is to provide a flip-chip light-emitting diode chip, the chip is prepared by the preparation method shown in the above technical solutions, and the chip includes:

A substrate, an epitaxial layer provided on the substrate, a current blocking layer provided on the epitaxial layer, a current spreading layer provided on the current blocking layer, respectively provided on the Mesa step and the N-type conductive metal and P-type conductive metal on the current spreading layer, a Bragg reflector layer on the N-type conductive metal and the P-type conductive metal, and an N-type conductive metal on the Bragg reflector type bonding metal and P-type bonding metal, the Bragg reflection layer is provided with an N-type conductive through hole and a P-type conductive through hole, the N-type bonding metal communicates with the N-type conductive through hole through the N-type conductive through hole The P-type conductive metal is electrically connected, and the P-type bonding metal is electrically connected to the P-type conductive metal through the P-type conductive through hole;

Wherein, the edge of the epitaxial layer and the Mesa steps are etched to the substrate to obtain a scribe line, and an acute angle is formed between the side surface of the epitaxial layer and the top surface of the substrate at the scribe line. The angle is 40°-80°.

According to an aspect of the above technical solution, the substrate is made of any one of Al ₂ O ₃ , GaN, Si, SiC, GaAs or other acceptable materials.

According to an aspect of the above technical solution, the epitaxial layer sequentially includes a buffer layer, an N-type doped semiconductor layer, an active layer and a P-type doped semiconductor layer from bottom to top.

Compared with the prior art, by adopting the flip-chip light-emitting diode chip and the preparation method of the present invention, the beneficial effects are:

By controlling the photolithography and etching process of the scribe line, the acute angle between the epitaxial layer and the substrate at the scribe line is increased, thereby increasing the lateral distance between the substrate and the epitaxial layer at the scribe line, which can effectively improve the cutting yield, and Preventing sidewall leakage after chip bonding can effectively improve the bonding yield.

Additional aspects and advantages of the present invention will be set forth, in part, from the following description, and in part will be apparent from the following description, or may be learned by practice of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of embodiments in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic flowchart of a method for manufacturing a flip-chip light-emitting diode chip according to the first embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a flip-chip light-emitting diode chip in the first embodiment of the present invention;

3 is a schematic structural diagram of a scribe line in a flip-chip LED chip according to the first embodiment of the present invention;

Description of reference numbers:

Substrate 11, scribe line 111, epitaxial layer 12, Mesa step 121, current blocking layer 13, current spreading layer 14, N-type conductive metal 151, P-type conductive metal 152, Bragg reflection layer 16, N-type conductive via 161, P-type conductive vias 162 , N-type bonding metal 171 , and P-type bonding metal 172 .

Detailed ways

In order to make the objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Several embodiments of the invention are presented in the accompanying drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical", "horizontal", "left", "right", "upper", "lower" and similar expressions used herein are for the purpose of illustration only and do not indicate or imply the referred device or The elements must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be construed as limiting the invention.

In the present invention, unless otherwise expressly specified and limited, the terms "installed", "connected", "connected", "fixed" and other terms should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection , or integrally connected; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or the internal communication between the two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Example 1

Referring to FIG. 1, a first embodiment of the present invention provides a method for preparing a flip-chip light-emitting diode chip, which is used for preparing the flip-chip light-emitting diode chip. The method includes steps S10-S80:

Step S10, providing a substrate;

Wherein, the substrate includes, but is not limited to, any one of Al ₂ O ₃ , GaN, Si, SiC, GaAs or other acceptable materials; in this embodiment, it is preferably a sapphire substrate, that is, Al ₂ O ₃ substrates.

Step S20, growing an epitaxial layer on the substrate, and etching the epitaxial layer to expose the Mesa steps;

By way of example and not limitation, the epitaxial layer sequentially includes a buffer layer, an N-type doped semiconductor layer, an active layer, and a P-type doped semiconductor layer from bottom to top. In this embodiment, by etching the epitaxial layer, the Mesa steps can be exposed, so that an N-type electrode structure connected to the N-type semiconductor layer can be fabricated on the Mesa steps.

Step S30, the epitaxial layer and the Mesa steps are etched and etched to the substrate to obtain a scribe line by etching, wherein the side surface of the epitaxial layer and the substrate at the scribe line are etched. The acute angle formed between the top surfaces is 40°-80°;

Wherein, the etching treatment of the epitaxial layer is specifically inductively coupled plasma etching, and cutting lines are obtained by removing the redundant epitaxial layer until the substrate is exposed.

Step S40, growing a current blocking layer on the epitaxial layer;

Wherein, the current blocking layer includes, but is not limited to, any one of SiO ₂ , Ti ₃ O ₅ , SiN, Al ₂ O ₃ or other acceptable materials; in this embodiment, it is preferably SiO ₂ material.

Step S50, growing a current spreading layer on the epitaxial layer and covering the current blocking layer;

Wherein, the current spreading layer includes but is not limited to being made of ITO (indium tin oxide), Ag and other materials; in this embodiment, it is preferably ITO.

Step S60, preparing N-type conductive metal and P-type conductive metal on the Mesa step and the current spreading layer, respectively;

Specifically, the N-type conductive metal is prepared on the Mesa step of the epitaxial layer, and the P-type conductive metal is prepared on the current spreading layer; wherein, the materials used to prepare the N-type conductive metal and the P-type conductive metal include but are not limited to Cr, A stack of Al, Ni, Ti, Pt, Au and the above metals.

Step S70, a Bragg reflection layer is prepared on the N-type conductive metal, the P-type conductive metal and the current spreading layer, and the Bragg reflection layer is etched to obtain N-type conductive vias and P-type conductive vias through hole;

Wherein, the Bragg reflection layer includes but is not limited to SiO ₂ and Ti 3 O ₅ stack, SiO ₂ and SiN stack; in this embodiment, it is preferably SiO ₂ and Ti ₃ O ₅ stack, and N-type conductive vias and P-type conductive vias The through holes are all obtained by inductively coupled plasma etching.

Step S80, preparing an N-type bonding metal corresponding to the N-type conductive metal and a P-type bonding metal corresponding to the P-type conductive metal on the Bragg reflection layer, so as to make the N-type bonding The metal is electrically connected to the N-type conductive metal through the N-type conductive through hole, and the P-type bonding metal is electrically connected to the P-type conductive metal through the P-type conductive through hole;

Wherein, the N-type bonding metal and the P-type bonding metal include, but are not limited to, Cr, Al, Ni, Ti, Pt, Au and stacks composed of these metals.

The preparation method of the flip-chip light-emitting diode chip shown in this embodiment specifically includes:

First, an epitaxial layer is grown on a substrate;

Then, a pattern is formed on the surface of the epitaxial layer by photolithography, and then ICP (inductively coupled plasma) etching is used to expose the Mesa steps, and then the surface photoresist is removed;

Then prepare the current blocking layer, first deposit SiO ₂ , then use photolithography technology to form patterns, then carry out BOE etching, and then remove the photoresist;

Next, the dicing lines are prepared. First, photoresist is coated on the surface of the epitaxial layer and Mesa step, and then the hot plate is baked after the glue is applied, and then the pattern is lithography by using the photolithography plate, and then the pre-development baking is performed, then the development is performed, and then the development is performed. Post bake, then oven bake, then ICP (Inductively Coupled Plasma) etch, etch to substrate, expose scribe lines, and then remove photoresist;

Then prepare the current spreading layer, first sputter ITO (indium tin oxide), then use photolithography to form patterns on the surface of ITO, then perform ITO etching, and then remove the surface photoresist;

Then prepare the conductive metal layer, first coat the negative photoresist on the surface, then photolithography to form a pattern, then evaporate the metal, then strip off the excess metal, remove the photoresist, and form N-type conductive metal and P-type conductive metal;

Then prepare the Bragg reflection layer, first evaporate _SiO2 and _Ti3O5 stack, then use photolithography to form patterns, and then ICP etching to form N-type conductive vias and P-type conductive vias;

Then prepare the bonding metal layer, first coat the negative photoresist on the surface, then form a pattern by photolithography, then evaporate the bonding metal layer, then strip off the excess metal, remove the photoresist, and form N-type bonding metal and P-type bonding metal; wherein, the N-type bonding metal is electrically connected to the N-type conductive metal through the N-type conductive through hole, and the P-type bonding metal is electrically connected to the P-type conductive metal through the P-type conductive through hole.

In this embodiment, in step S30, the epitaxial layer and the Mesa steps are etched and etched to the substrate to obtain scribe lines by etching, which specifically includes:

Coat photoresist on the surface of epitaxial layer and Mesa step;

After coating the epitaxial layer and Mesa steps, hot plate baking;

The epitaxial layer and Mesa steps are lithographically patterned by a lithography plate;

Pre-development baking, development, post-development baking and oven baking are performed on the epitaxial layer and Mesa steps;

Inductively coupled plasma etching is performed on the epitaxial layer, and the etching selectivity ratio is 0.6-1, so as to obtain the dicing track, the photoresist remaining on the epitaxial layer and the Mesa step by etching.

As an example, the acute angle formed between the side surface of the epitaxial layer and the top surface of the substrate at the scribe line is 50°, and the steps for preparing the scribe line specifically include:

Coat the photoresist on the surface of the epitaxial layer and the Mesa step, and then bake it on a hot plate with a glue coating at a temperature of 120°C and a time of 150s;

Exposure is carried out with a photomask, and the exposure energy is 1000mj/cm ² ;

The epitaxial layer and the Mesa steps were developed, and the development time was 200s; the post-hot plate was baked, and the baking temperature was 80°C and the time was 40s;

The epitaxial layer and the Mesa steps are oven-baked, the baking temperature is 70°C, and the time is 20min;

Inductively coupled plasma etching was performed on the epitaxial layer and the Mesa steps, and the etching selectivity ratio was 0.85, and the photoresist remaining on the epitaxial layer and the Mesa steps was removed;

After the dicing lines are prepared through the above steps, the acute included angle formed between the side surfaces of the epitaxial layer and the top surface of the substrate at the dicing lines is 50°.

In summary, through specific process selection, the acute angle formed between the side surface of the epitaxial layer at the scribe line and the top surface of the substrate can be made to be 50°, correspondingly increasing the lateral distance between the substrate and the epitaxial layer at the scribe line; It is easy to understand that the smaller the acute angle formed between the side surface of the epitaxial layer at the scribe line and the top surface of the substrate, the greater the lateral distance between the substrate and the epitaxial layer at the scribe line.

Compared with the prior art, using the fabrication method of the flip-chip light-emitting diode chip shown in this embodiment, without changing the light-emitting area of the diode chip or increasing the chip size, the side surface of the epitaxial layer at the dicing line can be adjusted to The acute angle formed between the top surfaces of the substrate is controlled within a certain range, which can increase the lateral distance between the substrate and the epitaxial layer at the cutting line to a certain extent, thereby effectively improving the cutting yield. Later, sidewall leakage is not easy to occur.

Embodiment 2

The second embodiment of the present invention provides a method for fabricating a flip-chip light emitting diode. The fabrication method shown in this embodiment is basically the same as the fabrication method shown in the first embodiment, which will not be repeated here. The difference is that :

In this embodiment, the acute angle formed between the side surface of the epitaxial layer and the top surface of the substrate at the scribe line is 65°, and the steps for preparing the scribe line specifically include:

Coat the photoresist on the surface of the epitaxial layer and the Mesa step, and then bake it on a hot plate with a glue coating at a temperature of 110°C and a time of 120s;

Exposure is carried out with a photomask, and the exposure energy is 300mj/cm ² ;

The epitaxial layer and the Mesa steps are baked before developing, the baking temperature is 115°C, and the time is 100s, and the epitaxial layer is developed, and the time is 80s;

Inductively coupled plasma etching was performed on the epitaxial layer and the Mesa steps, and the etching selectivity ratio was 0.7, and the photoresist remaining on the epitaxial layer and the Mesa steps was removed;

After the dicing lines are prepared through the above steps, the acute included angle formed between the side surfaces of the epitaxial layer and the top surface of the substrate at the dicing lines is 65°.

To sum up, in the preparation method shown in this embodiment, by changing the etching selectivity ratio of the epitaxial layer and the Mesa step, and correspondingly changing the exposure energy of the exposure, the baking temperature and baking time of the baking, and the development time of the development, The acute angle formed between the side surface of the epitaxial layer at the scribe line and the top surface of the substrate can be controlled to be between 40°-80°, so that the distance between the side surface of the epitaxial layer at the scribe line and the top surface of the substrate can be controlled. The formed acute included angle correspondingly changes the lateral distance between the substrate and the epitaxial layer at the dicing line.

Embodiment 3

Referring to FIGS. 2-3 , a third embodiment of the present invention provides a flip-chip light-emitting diode chip. The chip shown in this embodiment is manufactured by the preparation method shown in the above embodiments, and the chip includes:

The substrate 11, the epitaxial layer 12 provided on the substrate, the current 13 provided on the epitaxial layer 12, the current spreading layer 14 provided on the current blocking layer 13, the Mesa step 121 and the current spreading layer respectively N-type conductive metal 151 and P-type conductive metal 152 above 14 , Bragg reflection layer 16 provided on N-type conductive metal 151 and P-type conductive metal 152 , and N-type bond provided on Bragg reflection layer 16 The bonding metal 171 and the P-type bonding metal 172, the Bragg reflection layer 16 is provided with an N-type conductive through hole 161 and a P-type conductive through hole 162, and the N-type bonding metal 171 passes through the N-type conductive through hole 161 and the N-type conductive metal 151 is electrically connected, and the P-type bonding metal 172 is electrically connected to the P-type conductive metal 152 through the P-type conductive through hole 162;

Wherein, the edge of the epitaxial layer 12 and the Mesa step 121 are etched to the substrate 11 to obtain a dicing track 111, and the acute angle α formed between the side surface of the epitaxial layer 12 and the top surface of the substrate 11 at the dicing track 111 is 40°-80°; preferably, the acute angle α formed between the side surface of the epitaxial layer 12 at the dicing lane 111 and the top surface of the substrate 11 is 50°, and the substrate 11 and the epitaxy at the dicing lane 111 will be correspondingly increased. The lateral distance w of the layer 12; those skilled in the art can easily understand that the smaller the acute angle α formed between the side surface of the epitaxial layer 12 at the dicing line 111 and the top surface of the substrate 11, the smaller the angle α between the substrate 11 and the substrate 11 at the dicing line 111 The lateral distance w of the epitaxial layer 12 is also larger.

In this embodiment, the substrate 11 is made of any one of Al ₂ O ₃ , GaN, Si, SiC, GaAs or other acceptable materials, preferably a sapphire substrate, that is, an Al ₂ O ₃ substrate ; The epitaxial layer 12 sequentially includes a buffer layer, an N-type doped semiconductor layer, an active layer and a P-type doped semiconductor layer from bottom to top.

Compared with the prior art, using the flip-chip light-emitting diode chip shown in this embodiment, without changing the light-emitting area of the diode chip or increasing the chip size, the side surface of the epitaxial layer at the dicing line can be connected with the substrate. The acute angle formed between the top surfaces is controlled within a certain range, which can increase the lateral distance between the substrate and the epitaxial layer at the cutting line to a certain extent, thereby effectively improving the cutting yield, and it is not easy to occur after the diode chip is solidified. sidewall leakage.

In the description of this specification, description with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples", etc., mean specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The above examples only represent several embodiments of the present invention, and the descriptions thereof are more specific and detailed, but should not be construed as a limitation on the scope of the patent of the present invention. It should be pointed out that for those skilled in the art, without departing from the concept of the present invention, several modifications and improvements can be made, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention should be subject to the appended claims.

Claims (10)

1. A method for preparing a flip-chip light emitting diode chip, which is used for preparing the flip-chip light emitting diode chip, and is characterized by comprising the following steps:

providing a substrate;

growing an epitaxial layer on the substrate, and etching the epitaxial layer to expose the Mesa step;

etching the epitaxial layer and the Mesa step to the substrate to obtain a cutting channel, wherein an acute included angle formed between the side surface of the epitaxial layer and the top surface of the substrate at the cutting channel is 40-80 degrees;

growing a current barrier layer on the epitaxial layer;

growing a current expansion layer on the epitaxial layer and covering the current barrier layer;

respectively preparing N-type conductive metal and P-type conductive metal on the Mesa step and the current expansion layer;

preparing Bragg reflection layers on the N-type conductive metal, the P-type conductive metal and the current extension layer, and etching the Bragg reflection layers to obtain an N-type conductive through hole and a P-type conductive through hole;

preparing an N-type bonding metal corresponding to the N-type conductive metal and a P-type bonding metal corresponding to the P-type conductive metal on the Bragg reflection layer, so that the N-type bonding metal is electrically connected with the N-type conductive metal through the N-type conductive through hole, and the P-type bonding metal is electrically connected with the P-type conductive metal through the P-type conductive through hole.

2. The method for manufacturing the flip chip light emitting diode chip as claimed in claim 1, wherein in the step of etching the epitaxial layer and the Mesa step to the substrate to obtain the scribe line, the etching process is inductively coupled plasma etching.

3. The method for manufacturing the flip-chip light emitting diode chip as claimed in claim 1, wherein the step of etching the epitaxial layer and the Mesa step to the substrate to obtain the scribe line by etching comprises:

coating photoresist on the epitaxial layer and the surface of the Mesa step;

carrying out hot plate baking after gluing the epitaxial layer and the Mesa step;

photoetching graphs of the epitaxial layer and the Mesa step through a photoetching plate;

baking the epitaxial layer and the Mesa step before development, developing, baking after development and baking in an oven;

and carrying out inductively coupled plasma etching on the epitaxial layer, wherein the etching selection ratio is 0.6-1, so as to obtain a cutting path by etching, and removing the residual photoresist on the epitaxial layer and the Mesa step.

4. The method of manufacturing a flip chip light emitting diode chip as claimed in claim 3, wherein in the step of etching the epitaxial layer and the Mesa step to the substrate to obtain the scribe line, an acute angle between a side surface of the epitaxial layer and a top surface of the substrate at the scribe line is 50 °.

5. The method for manufacturing the flip chip light emitting diode chip as claimed in claim 4, wherein the step of etching the epitaxial layer and the Mesa step to the substrate to obtain the scribe line by etching includes:

coating photoresist on the epitaxial layer and the surface of the Mesa step, and then carrying out gluing hot plate baking at the temperature of 120 ℃ for 150 s;

exposing with a photomask at an exposure energy of 1000mj/cm²；

Developing the epitaxial layer and the Mesa step for 200 s; baking in a rear hot plate at 80 ℃ for 40 s;

baking the epitaxial layer and the Mesa step in an oven at the temperature of 70 ℃ for 20 min;

performing inductively coupled plasma etching on the epitaxial layer and the Mesa step, wherein the etching selection ratio is 0.85,

removing the residual photoresist on the epitaxial layer and the Mesa step;

after the dicing street is prepared through the steps, an acute included angle formed between the side surface of the epitaxial layer and the top surface of the substrate at the dicing street is 50 degrees.

6. The method of claim 3, wherein in the step of etching the epitaxial layer and the Mesa step to the substrate to obtain the scribe line, an acute angle of 65 ° is formed between a side surface of the epitaxial layer and a top surface of the substrate at the scribe line.

7. The method for manufacturing the flip chip light emitting diode chip as claimed in claim 6, wherein the step of etching the epitaxial layer and the Mesa step to the substrate to obtain the scribe line by etching includes:

coating photoresist on the epitaxial layer and the surface of the Mesa step, and then carrying out gluing hot plate baking at the temperature of 110 ℃ for 120 s;

exposing with a photomask at an exposure energy of 300mj/cm²；

Baking the epitaxial layer and the Mesa step before developing, wherein the baking temperature is 115 ℃, the baking time is 100s, and the developing time is 80 s;

performing inductively coupled plasma etching on the epitaxial layer and the Mesa step, wherein the etching selection ratio is 0.7,

removing the residual photoresist on the epitaxial layer and the Mesa step;

after the cutting street is prepared through the steps, an acute included angle formed between the side surface of the epitaxial layer and the top surface of the substrate at the cutting street is 65 degrees.

8. A flip chip light emitting diode chip, wherein the chip is produced by the method of any one of claims 1 to 7, the chip comprising:

the device comprises a substrate, an epitaxial layer arranged on the substrate, a current barrier layer arranged on the epitaxial layer, a current expansion layer arranged on the current barrier layer, an N-type conductive metal and a P-type conductive metal which are respectively arranged on a Mesa step and the current expansion layer, a Bragg reflection layer arranged on the N-type conductive metal and the P-type conductive metal, and an N-type bonding metal and a P-type bonding metal which are arranged on the Bragg reflection layer, wherein an N-type conductive through hole and a P-type conductive through hole are arranged on the Bragg reflection layer, the N-type bonding metal is electrically connected with the N-type conductive metal through the N-type conductive through hole, and the P-type bonding metal is electrically connected with the P-type conductive metal through the P-type conductive through hole;

and etching the edge of the epitaxial layer and the Mesa step to the substrate to obtain a cutting channel, wherein an acute included angle formed between the side surface of the epitaxial layer and the top surface of the substrate at the cutting channel is 40-80 degrees.

9. The flip-chip led chip of claim 8 wherein the substrate is made of Al₂O₃Any of GaN, Si, SiC, GaAs or other acceptable materials.

10. The flip-chip led chip of claim 8, wherein the epitaxial layer comprises, in order from bottom to top, a buffer layer, an N-type doped semiconductor layer, an active layer, and a P-type doped semiconductor layer.

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