CN116913792B - Double-sided heat dissipation packaging module and manufacturing method - Google Patents
Double-sided heat dissipation packaging module and manufacturing method Download PDFInfo
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- CN116913792B CN116913792B CN202310900767.9A CN202310900767A CN116913792B CN 116913792 B CN116913792 B CN 116913792B CN 202310900767 A CN202310900767 A CN 202310900767A CN 116913792 B CN116913792 B CN 116913792B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 21
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- 238000000034 method Methods 0.000 claims abstract description 39
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- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention provides a double-sided heat dissipation packaging module and a manufacturing method thereof, wherein the method comprises the following steps: providing a lower heat conducting substrate, and fixing a chip to be packaged on the upper surface of the lower heat conducting substrate; forming a bonding support frame on the upper surface of the lower heat conducting substrate, wherein the bonding support frame is positioned at the side edge of the chip to be packaged, the bonding support frame is in a trapezoid bridge type structure, the end part of the bonding support frame is connected with the lower heat conducting substrate in a bonding way, and the top end of the middle part of the bonding support frame is higher than the upper surface of the chip to be packaged in the vertical direction; providing an upper heat conducting substrate, and welding the top end of the bonding support frame with the upper surface of the upper heat conducting substrate; and forming a plastic sealing layer for coating the lower heat conducting substrate, the chip to be packaged and the upper heat conducting substrate. The bonding support frame is used as a support and heat conduction channel, has the advantages of simple process and low manufacturing cost, has no special requirement on the upper surface of the chip, and is suitable for a conventional power chip; in addition, the bonding process is used as a basis to produce the high-yield product, so that the cost is further reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a double-sided heat dissipation packaging module and a manufacturing method thereof.
Background
In the field of power semiconductors, a power module needs to pass high current, the heat dissipation requirement is high, statistics is based on, and about 40% of product failures are caused by overhigh temperature in the use process. In order to make the heat dissipation of the power module better, a manufacturer has proposed a double-sided heat dissipation power module, as shown in fig. 1, a schematic structure diagram of the double-sided heat dissipation power module is shown, which comprises a lower heat conducting substrate 01, a chip 02, a supporting pad 03 and an upper heat conducting substrate 04, wherein the lower heat conducting substrate 01 adopts a three-layer structure to cover a copper ceramic substrate (copper layer/ceramic layer/copper layer), the supporting pad 03 is positioned on the upper surface of the chip 02, the upper heat conducting substrate 04 is positioned above the supporting pad 03, the upper heat conducting substrate 04 adopts a three-layer structure to cover the copper ceramic substrate (copper layer/ceramic layer/copper layer), after the plastic sealing layer 05 is packaged, electrodes are led out through lead-out terminals 06, arrows represent current directions, and the lower heat conducting substrate 01 and the upper heat conducting substrate 04 realize double-sided heat dissipation. However, the structure shown in fig. 1 has the following disadvantages: 1. the chip needs a special process, and the upper surface and the lower surface of the chip can be welded to realize double-sided heat dissipation; 2. the packaging process is complex, the yield is low, and the manufacturing cost is high; 3. on the basis of a conventional power module packaging production line, a lot of equipment and working procedures such as a mounting working procedure, a welding working procedure, a cleaning working procedure and the like are added; 4. the upper surface of the power chip is usually used as a current path, more wires or welded copper bridges are usually bonded on the upper surface of the chip, if the upper surface of the chip is occupied by the supporting pad 03 with a larger area, the overcurrent capacity of the module is reduced, the power chip is not suitable for occasions with low power grades, if the supporting pad 03 on the upper surface of the chip has heat dissipation and electric conduction effects, for single-tube products of a single chip, the current flow from the collector/drain electrode on the lower surface of the chip is required to be constructed, and the current flow from the circuit of the upper heat conduction layer to other terminals is also required to be constructed, so that the design is very complex; 5. when the supporting pad 03 is welded on the upper surface of the chip 02, solder paste or solder paste particles are easy to splash around the chip, and the residual solder paste particles on the passivation layer around the chip can influence the reliability of the product when the subsequent process is not good.
Therefore, how to provide a dual-sided heat dissipation package module and a manufacturing method thereof, so as to be suitable for a package module of a conventional power chip, reduce process complexity, reduce cost, and improve product reliability, is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a dual-sided heat dissipation package module and a manufacturing method thereof, which are used for solving the problems of complex process and high manufacturing cost of the dual-sided heat dissipation package module in the prior art.
To achieve the above and other related objects, the present invention provides a method for manufacturing a dual-sided heat dissipation package module, comprising the steps of:
providing a lower heat conducting substrate, wherein the lower heat conducting substrate comprises an upper surface and a lower surface which are oppositely arranged, the lower heat conducting substrate is provided with a leading-out terminal protruding out of the lower heat conducting substrate in the horizontal direction, and a chip to be packaged is fixed on the upper surface of the lower heat conducting substrate;
forming a bonding support frame on the upper surface of the lower heat conducting substrate, wherein the bonding support frame is positioned on the side edge of the chip to be packaged and is spaced from the chip to be packaged by a preset distance, the bonding support frame is in a trapezoid bridge type structure, the end part of the bonding support frame is connected with the lower heat conducting substrate in a bonding way, and the top end of the middle part of the bonding support frame is higher than the bonding lead on the upper surface of the chip to be packaged in the vertical direction;
providing an upper heat conducting substrate, wherein the upper heat conducting substrate comprises an upper surface and a lower surface which are oppositely arranged, and the top end of the bonding support frame is welded with the upper surface of the upper heat conducting substrate;
and forming a plastic layer, wherein the plastic layer coats the lower heat conducting substrate, the chip to be packaged and the upper heat conducting substrate.
Optionally, the upper heat conducting substrate comprises an aluminum nitride layer/copper layer sequentially stacked from bottom to top.
Optionally, the bonding support frame includes a first bonding support frame and a second bonding support frame, where the first bonding support frame is located at a left side of the chip to be packaged, and the second bonding support frame is located at a right side of the chip to be packaged; or the first bonding support frame is positioned on the upper side of the chip to be packaged, and the second bonding support piece is arranged on the lower side of the chip to be packaged.
Optionally, the bonding support frame includes first bonding support frame, second bonding support frame, third bonding support frame and fourth bonding support frame, wherein, first bonding support frame is located wait to encapsulate the left side of chip, the second bonding support frame is located wait to encapsulate the right side of chip, third bonding support frame is located wait to encapsulate the upside of chip, fourth bonding support frame is located wait to encapsulate the downside of chip.
Optionally, the method for welding the top end of the bonding support frame to the upper surface of the upper heat conducting substrate includes: and placing a pre-soldering lug between the upper surface of the upper heat-conducting substrate and the bonding support frame, and welding the upper heat-conducting substrate and the bonding support frame by adopting a vacuum welding method.
The invention also provides a double-sided heat dissipation packaging module, which comprises:
the lower heat conducting substrate comprises an upper surface and a lower surface which are oppositely arranged, and the lower heat conducting substrate is provided with a leading-out terminal protruding out of the lower heat conducting substrate in the horizontal direction;
the chip to be packaged is positioned on the upper surface of the lower heat conducting substrate and fixedly connected with the lower heat conducting substrate;
the bonding support frame is positioned on the upper surface of the lower heat conducting substrate, the bonding support frame is positioned on the side edge of the chip to be packaged and is spaced from the chip to be packaged by a preset distance, the bonding support frame is in a trapezoid bridge type structure, the end part of the bonding support frame is connected with the lower heat conducting substrate in a bonding way, and the top end of the middle part of the bonding support frame is higher than the bonding lead on the upper surface of the chip to be packaged in the vertical direction;
the upper heat conducting substrate is positioned above the bonding support frame, and the top end of the bonding support frame is welded with the upper heat conducting substrate;
and the plastic layer is used for coating the lower heat conducting substrate, the chip to be packaged and the upper heat conducting substrate.
Optionally, the upper heat conducting substrate comprises a copper layer/an aluminum nitride layer sequentially stacked from bottom to top.
Optionally, the thickness of the aluminum nitride layer ranges from 0.25 to 1mm, and the thickness of the copper layer ranges from 0.5 to 1mm.
Optionally, the bonding support frame includes a first bonding support frame and a second bonding support frame, where the first bonding support frame is located at a left side of the chip to be packaged, and the second bonding support frame is located at a right side of the chip to be packaged; or the first bonding support frame is positioned on the upper side of the chip to be packaged, and the second bonding support piece is positioned on the lower side of the chip to be packaged.
Optionally, the bonding support frame includes first bonding support frame, second bonding support frame, third bonding support frame and fourth bonding support frame, wherein, first bonding support frame is located wait to encapsulate the left side of chip, the second bonding support frame is located wait to encapsulate the right side of chip, third bonding support frame is located wait to encapsulate the upside of chip, fourth bonding support frame is located wait to encapsulate the downside of chip.
As described above, in the double-sided heat dissipation packaging module and the manufacturing method, the bonding support frame is adopted as the support and heat conduction channel, so that the double-sided heat dissipation packaging module has the advantages of simple process and low manufacturing cost, has no special requirement on the upper surface of the chip, and is suitable for a conventional power chip; in addition, the bonding process is used as a basis to produce the high-yield product, so that the cost is further reduced.
Drawings
Fig. 1 is a schematic structural diagram of a dual-sided heat dissipation package module.
Fig. 2 is a flow chart of a method for manufacturing a dual-sided heat dissipation package module according to the present invention.
Fig. 3 is a schematic view illustrating a chip to be packaged fixed on a lower heat conductive substrate according to the present invention.
Fig. 4 is a top view of a chip to be packaged fixed on a lower heat conductive substrate according to the present invention.
Fig. 5 is a schematic view of forming bonding wires and bonding support frames according to the present invention.
Fig. 6 is a top view of a bonding wire and bonding support formed in accordance with the present invention.
Fig. 7 is a photograph of an electron microscope bonded with a support frame according to the present invention.
Fig. 8 is a schematic diagram showing the bonding of the top end of the bonding support frame and the upper thermally conductive substrate after the flip-chip bonding of the lower thermally conductive substrate.
Fig. 9 is a schematic view showing the formation of a molding layer according to the present invention.
Description of element numbers: 01-lower heat conducting substrate, 02-chip, 03-supporting pad, 04-upper heat conducting substrate, 05-plastic layer and 06-leading-out terminal; 1-a lower heat conduction substrate, 10-a first copper layer, 11-an aluminum oxide layer and 12-a second copper layer; 2-out terminal, 20-emitter terminal, 21-collector terminal, 22-gate terminal; 3-FRD chip, 30-anode; 4-IGBT chip, 40-grid electrode and 41-emitter electrode; 50-first bond wire, 51-second bond wire, 52-third bond wire; 60-first bonding support frame, 61-second bonding support frame, 62-third bonding support frame, 63-fourth bonding support frame; 7-pre-soldering lug; 8-an upper heat conducting substrate, 80-an aluminum nitride layer and 81-a copper layer; 9-plastic sealing layer; S1-S4-steps.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 9. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The embodiment provides a method for manufacturing a double-sided heat dissipation package module, please refer to fig. 2, which shows a manufacturing flow chart of the method, comprising the following steps:
s1: providing a lower heat conducting substrate, wherein the lower heat conducting substrate comprises an upper surface and a lower surface which are oppositely arranged, the lower heat conducting substrate is provided with a leading-out terminal protruding out of the lower heat conducting substrate in the horizontal direction, and a chip to be packaged is fixed on the upper surface of the lower heat conducting substrate;
s2: forming a bonding support frame on the upper surface of the lower heat conducting substrate, wherein the bonding support frame is positioned on the side edge of the chip to be packaged and is spaced from the chip to be packaged by a preset distance, the bonding support frame is in a trapezoid bridge type structure, the end part of the bonding support frame is connected with the lower heat conducting substrate in a bonding way, and the top end of the middle part of the bonding support frame is higher than the bonding lead on the upper surface of the chip to be packaged in the vertical direction;
s3: providing an upper heat conducting substrate, wherein the upper heat conducting substrate comprises an upper surface and a lower surface which are oppositely arranged, and the top end of the bonding support frame is welded with the upper surface of the upper heat conducting substrate;
s4: and forming a plastic layer, wherein the plastic layer coats the lower heat conducting substrate, the chip to be packaged and the upper heat conducting substrate.
First, referring to fig. 3 and 4, step S1 is performed: the method comprises the steps of providing a lower heat conducting substrate 1, wherein the lower heat conducting substrate 1 comprises an upper surface and a lower surface which are oppositely arranged, the lower heat conducting substrate 1 is provided with a leading-out terminal 2 protruding out of the lower heat conducting substrate 1 in the horizontal direction, and a chip to be packaged is fixed on the upper surface of the lower heat conducting substrate 1.
As an example, the lower heat conducting substrate 1 is a copper-clad ceramic substrate with a three-layer structure, and includes a first copper layer 10, an aluminum oxide layer 11, and a second copper layer 12 sequentially stacked from bottom to top, and the upper surface of the lower heat conducting substrate 1 is the upper surface of the second copper layer 12.
As an example, the lead-out terminals 2 include an emitter terminal 20, a collector terminal 21, and a gate terminal 22, and the lead-out terminals 2 are used for electrode lead-out of the package module.
As an example, the chip to be packaged includes an Insulated Gate Bipolar Transistor (IGBT) chip, a metal oxide semiconductor field effect transistor (Mosfet) chip, a SiC power chip, or the like; specifically, the chip to be packaged in this embodiment adopts an IGBT chip, and typically an IGBT is used with a Fast Recovery Diode (FRD), so the FRD chip 3 and the IGBT chip 4 are disposed on the upper surface of the lower thermally conductive substrate 1, and the FRD chip 3 and the IGBT chip 4 are combined to form the structure to be packaged, however, in other examples, only the IGBT chip 4 may be disposed.
As an example, the FRD chip 3 and the IGBT chip 4 are fixed to the upper surface of the lower heat conductive substrate 1 using a soldering process or a sintering process; wherein the FRD chip 3 includes an upper surface and a lower surface which are oppositely disposed, an anode 30 is disposed on the upper surface of the FRD chip 3, and a cathode is disposed on the lower surface of the FRD chip 3 and electrically connected to the collector terminal 21; the IGBT chip 4 includes an upper surface and a lower surface that are disposed opposite to each other, the upper surface of the IGBT chip 4 is provided with a gate 40 and an emitter 41, and the lower surface of the IGBT chip 4 is provided with a collector electrically connected to the collector terminal 21; preferably, the IGBT chip 4 is a vertical double diffusion type, and two emitters 41 are disposed on the upper surface of the IGBT chip 4.
Next, referring to fig. 5 and 6, step S2 is performed: and a bonding support frame is formed on the upper surface of the lower heat conducting substrate 1, the bonding support frame is positioned on the side edge of the chip to be packaged and is spaced from the chip to be packaged by a preset distance, wherein the bonding support frame is in a trapezoid bridge type structure, the end part of the bonding support frame is connected with the lower heat conducting substrate 1 in a bonding way, and the top end of the middle part of the bonding support frame is higher than the bonding lead on the upper surface of the chip to be packaged in the vertical direction.
As an example, before forming the bonding support frame, the bonding wires are formed on a bonding apparatus, the bonding wires include a first bonding wire 50, a second bonding wire 51, and a third bonding wire 52, wherein one end of the first bonding wire 50 is electrically connected to the anode 30 of the FRD chip 3, and the other end of the first bonding wire 50 is electrically connected to the emitter terminal 20; one end of the second bonding wire 51 is electrically connected to the emitter 41 of the IGBT chip 4, and the other end of the second bonding wire 51 is electrically connected to the emitter terminal 20; one end of the third bonding wire 52 is electrically connected to the gate 40 of the IGBT chip 4, and the other end of the third bonding wire 52 is electrically connected to the gate terminal 22.
As an example, the bonding wire includes a copper wire, a copper tape, an aluminum wire, an aluminum tape, or the like, and specifically, in this embodiment, the bonding wire employs a copper wire.
As an example, the bonding support frame is formed on a bonding device, and the bonding support frame includes a first bonding support frame 60, a second bonding support frame 61, a third bonding support frame 62, and a fourth bonding support frame 63, where in a horizontal direction, the first bonding support frame 60 is located at a left side of the structure to be packaged, the second bonding support frame 61 is located at a right side of the structure to be packaged, and the first bonding support frame 60 and the second bonding support frame 61 are symmetrically distributed at left and right sides of the structure to be packaged; the third bonding support frame 62 is located at the upper side of the structure to be packaged, the fourth bonding support frame 63 is located at the lower side of the structure to be packaged, and the third bonding support frame 62 and the fourth bonding support frame 63 are symmetrically distributed at the upper side and the lower side of the structure to be packaged.
As an example, as shown in fig. 7, an electron microscope picture displayed as a bonding support frame, in a vertical direction, the top ends of the first bonding support frame 60, the second bonding support frame 61, the third bonding support frame 62, and the fourth bonding support frame 63 are higher than the top ends of the bonding wires and the top ends of the chip to be packaged; in addition, the precision of the bonding device is very high, the repeatability error in three dimensions of XYZ can reach within ±3.0 μm, the top height error of the bonding support frame is very good in consistency of a wire arc plane under the condition of meeting the requirements of process machining and appearance size, and the top ends of the first bonding support frame 60, the second bonding support frame 61, the third bonding support frame 62 and the fourth bonding support frame 63 can form a very flat supporting surface for supporting and welding the upper heat conducting substrate 8 (see the following figure 8).
As an example, the two ends of the first bonding support 60 are located on the same potential copper layer, the two ends of the second bonding support 61 are located on the same potential copper layer, the two ends of the third bonding support 61 are located on the same potential copper layer, the two ends of the fourth bonding support 63 are located on the same potential copper layer, the two ends of each bonding support are located on the same potential copper layer, no current flows during operation, and no additional heat is generated by the bonding supports with supporting function.
By way of example, the bond support comprises copper wire, copper strap, aluminum wire or aluminum strap, wherein the copper has a thermal conductivity of approximately 398W/(K.m) and the aluminum has a thermal conductivity of approximately 238W/(K.m), and the bond support in this embodiment is preferably copper wire or copper strap.
It should be noted that, in other examples, only the first bonding support frame 60 and the second bonding support frame 61, or only the third bonding support frame 62 and the fourth bonding support frame 63 are provided, which falls within the protection scope of the present invention.
As an example, compared with the prior art that a double-sided heat dissipation packaging module adopts a metal column or a metal gasket as a support, and needs to be subjected to working procedures such as printing tin paste, attaching the metal column/the metal gasket, welding, cleaning and the like, the double-sided heat dissipation packaging module adopts a bonding support frame as the support and is formed in a bonding working procedure like a bonding lead, so that working procedures of printing tin paste, attaching the metal column/the metal gasket, welding and cleaning are reduced, the process complexity is reduced, the cost is reduced, meanwhile, factors which influence on the reliability of a product are reduced, and the reliability of the product is improved; in addition, the bonding support frame is positioned at the side edge of the chip to be packaged, so that the upper surface of the chip is provided with enough space bonding wires, the bonding support frame is suitable for the surface of a conventional power chip, the adjustment or the addition of a chip manufacturing process is not required for adapting to a welding process on the upper surface of the chip, and the chip processing cost is reduced; in addition, the bonding support frame can be adjusted according to the size and the position of the chip, and the design is more flexible and convenient.
As an example, compared with the prior art that the double-sided heat dissipation packaging module adopts a metal column or a metal gasket as a support, the bonding support frame is adopted as the support, so that the manufacturing of a clamp and related special support materials and the debugging of more procedures are reduced, the period of product research and development manufacturing can be greatly shortened, the research and development manufacturing period can be shortened by more than 5 months, and the cost is further reduced.
Next, referring to fig. 8, step S3 is performed: an upper heat conducting substrate 8 is provided, wherein the upper heat conducting substrate 8 comprises an upper surface and a lower surface which are oppositely arranged, and the top end of the bonding support frame is welded with the upper surface of the upper heat conducting substrate 8.
As an example, the upper heat conducting substrate 8 is a copper-clad ceramic substrate with a two-layer structure, and includes an aluminum nitride layer 80 and a copper layer 81 sequentially stacked from bottom to top, where the thickness range of the aluminum nitride layer 80 is 0.25-1mm, and the thickness range of the copper layer 81 is 0.5-1mm, where the upper surface of the upper heat conducting substrate 8 is the upper surface of the copper layer 81. Specifically, in this embodiment, the thickness of the aluminum nitride layer 80 is 0.25mm, and the thickness of the copper layer 81 is 0.8mm.
As an example, the step of soldering the top end of the bonding support frame to the upper surface of the upper thermally conductive substrate 8 includes:
placing the upper heat conducting substrate 8 on a welding fixture, and placing a pre-soldering tab 7 on the upper surface of the upper heat conducting substrate 8, wherein the pre-soldering tab 7 comprises a solder paste pre-soldering tab;
secondly, the lower heat conduction substrate 1 after bonding is inverted, so that the top end of the bonding support frame is in contact with the pre-soldering piece 7;
and thirdly, welding the bonding support frame and the upper heat conduction substrate 8 through the pre-welding sheet 7 in a formic acid vacuum welding furnace, wherein formic acid is introduced in the welding process, so that the welded structure does not need to be subjected to a cleaning step.
As an example, compared with the conventional copper-clad ceramic substrate in which the ceramic layer is an aluminum oxide layer, the thermal conductivity of the ceramic layer is 24W/(k·m), and in this embodiment, the ceramic layer in the upper thermally conductive substrate 8 is an aluminum nitride layer 80, which has a thermal conductivity of about 170-180W/(k·m), and has a better thermal conductivity, so that the heat of the package module is advantageously conducted out through the upper thermally conductive substrate 8. And compared with the conventional double-sided heat dissipation module which adopts three layers of copper-clad ceramic plates (copper layers, aluminum oxide and copper layers) as the upper heat conduction substrate, the embodiment adopts the upper heat conduction substrate with a two-layer structure, so that a heat dissipation system can be reduced by one layer of copper, one less factor of heat resistance influence is caused, and meanwhile, the cost of processing the copper-clad ceramic substrate with one less copper layer can be reduced by 20%.
Next, referring to fig. 9, step S4 is performed: and forming a plastic sealing layer 9, wherein the plastic sealing layer 9 coats the lower heat conducting substrate 1, the chip to be packaged and the upper heat conducting substrate 8.
As an example, after the top end of the bonding support frame is welded to the upper surface of the upper heat conducting substrate 8, the welded structure is placed in a plastic package mold, and is injection molded, cured at 175 ℃ to form the plastic package layer 9, so as to realize electrical and mechanical protection.
As an example, compared with the prior art that a metal column or a metal gasket is used as a support, the bonding support frame in the embodiment is of a trapezoid bridge structure, has a certain buffering effect in the plastic packaging process, and is good in product flexibility.
As an example, the plastic-encapsulated package module has a lower surface exposed to the first copper layer 10 and an upper surface exposed to the aluminum nitride layer 80 for heat dissipation; compared with the upper surface in fig. 1, if the conventional air cooling condition is used and the radiating fins are not installed for sealing, a copper layer needs to be exposed in the air, oxidation problem exists when the copper layer is used for a long time, the generated copper oxide can increase thermal resistance so as to influence the heat conduction effect and the reliability of the product, and the product failure can be accelerated along with the increasing of the thermal resistance of the upper surface of the oxide on the copper surface, the aluminum nitride layer 80 exposed on the upper surface in the embodiment is used as an insulating pressure-resistant and oxidation-resistant heat dissipation path, so that the aluminum nitride layer is convenient for customers to flexibly use and improves the reliability of the product.
To this end, a double-sided heat dissipation packaging module is prepared, please refer to fig. 9, the double-sided heat dissipation packaging module comprises a lower heat conduction substrate, a chip to be packaged, a bonding support frame, an upper heat conduction substrate and a plastic sealing layer 9, the lower heat conduction substrate comprises an upper surface and a lower surface which are oppositely arranged, and the lower heat conduction substrate is provided with a lead-out terminal 2 protruding out of the lower heat conduction substrate in the horizontal direction; the chip to be packaged is positioned on the upper surface of the lower heat conducting substrate and is fixedly connected with the lower heat conducting substrate; the bonding support frame is positioned on the upper surface of the lower heat conducting substrate, the bonding support frame is positioned on the side edge of the chip to be packaged and is spaced from the chip to be packaged by a preset distance, the bonding support frame is in a trapezoid bridge type structure, the end part of the bonding support frame is connected with the lower heat conducting substrate in a bonding way, and the top end of the middle part of the bonding support frame is higher than the bonding lead on the upper surface of the chip to be packaged in the vertical direction; the upper heat conducting substrate is positioned above the bonding support frame, and the top end of the bonding support frame is welded with the upper heat conducting substrate; the plastic layer 9 encapsulates the lower heat conducting substrate, the chip to be packaged and the upper heat conducting substrate.
As an example, the lower heat conducting substrate adopts a copper-clad ceramic substrate with a three-layer structure, and comprises a first copper layer 10, an aluminum oxide layer 11 and a second copper layer 12 which are sequentially laminated from bottom to top; the upper heat conducting substrate adopts a two-layer copper-clad ceramic substrate and comprises a copper layer 81 and an aluminum nitride layer 80 which are sequentially laminated from bottom to top.
As an example, referring to fig. 6, the lead-out terminal 2 includes an emitter terminal 20, a collector terminal 21, and a gate terminal 22, and the lead-out terminal 2 is used for electrode lead-out of the package module; the chip to be packaged comprises an FRD chip 3 and an IGBT chip 4, wherein the FRD chip 3 comprises an upper surface and a lower surface which are oppositely arranged, an anode 30 is arranged on the upper surface of the FRD chip 3, the anode 30 is electrically connected with the emitter terminal 20 through a first bonding wire 50, and a cathode is arranged on the lower surface of the FRD chip 3 and is electrically connected with the collector terminal 21; the IGBT chip 4 includes an upper surface and a lower surface that are disposed opposite to each other, the upper surface of the IGBT chip 4 is provided with a gate 40 and an emitter 41, the gate 40 is electrically connected to the gate terminal 22 through a third bonding wire 52, the emitter 41 is electrically connected to the emitter terminal 20 through a second bonding wire 51, and the lower surface of the IGBT chip 4 is provided with a collector electrically connected to the collector terminal 21.
As an example, the bonding support frames include a first bonding support frame 60, a second bonding support frame 61, a third bonding support frame 62, and a fourth bonding support frame 63, wherein, in a horizontal direction, the first bonding support frame 60 is located at a left side of the chip to be packaged, the second bonding support frame 61 is located at a right side of the chip to be packaged, and the first bonding support frame 60 and the second bonding support frame 61 are symmetrically arranged; the third bonding support 62 is located at the upper side of the chip to be packaged, the fourth bonding support 63 is located at the lower side of the chip to be packaged, and the third bonding support 62 and the fourth bonding support 63 are symmetrically arranged; in the vertical direction, the top ends of the first bonding support frame 60, the second bonding support frame 61, the third bonding support frame 62 and the fourth bonding support frame 63 are higher than the top ends of the Yu Jian bonding wires and the top ends of the chips to be packaged, and the top ends of the first bonding support frame 60, the second bonding support frame 61, the third bonding support frame 62 and the fourth bonding support frame 63 can form a flat supporting surface.
As an example, the lower surface of the package module exposes the second copper layer 12, and the upper surface exposes the aluminum nitride layer 80 for heat dissipation.
Specifically, the calculation formula of the thermal resistance is:
R th ＝L/(λS)
wherein R is th Is thermal resistance, L is material thickness, lambda is material thermal conductivity, and S is heat transfer area.
As an example, taking 20 copper wires with diameter of 500um as an example, a bonding support frame with thickness of 2mm is formed, the thermal resistance is: r is R th ＝2mm/[398W/(K·m)×20×π×0.25mm×0.25mm]＝2mm/[398W/(K·m)×3.925mm 2 ]The method comprises the steps of carrying out a first treatment on the surface of the With a thickness of 2mm and an area of 4mm 2 For example, the thermal resistance of the molding compound (thermal conductivity of about 1W/(K.m)) is: r is R th ＝2mm/[1W/(K·m)×4mm 2 ]The method comprises the steps of carrying out a first treatment on the surface of the Taking a copper layer with the thickness of 0.8mm and an aluminum nitride layer with the thickness of 0.25mm as an example of the upper heat conducting substrate, the heat resistance is as follows: r is R th ＝0.8mm/[398W/(K·m)]×S+0.25mm/[180W/(K·m)]X S; taking plastic package material with thickness of 1.05mm as an example, the thermal resistance is as follows: r is R th ＝1.05mm/[1W/(K·m)]X S; the comprehensive evaluation is available, and the bonding support frame with the thickness of 2mm and the bonding support frameThe heat of the upper heat conducting substrate with the thickness of 1.05mm is transferred to the lower heat conducting substrate, compared with the heat of the plastic sealing layer with the thickness of 3.05mm, the heat resistance is reduced by more than 300 times, and the heat dissipation capacity of the upper part of the packaging module is greatly enhanced.
In summary, in the double-sided heat dissipation packaging module and the manufacturing method, the bonding support frame is adopted as the supporting and heat conducting channel, so that the double-sided heat dissipation packaging module has the advantages of simple process and low manufacturing cost, has no special requirement on the upper surface of the chip, and is suitable for a conventional power chip; in addition, the bonding process is used as a basis to produce the high-yield product, so that the cost is further reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. The manufacturing method of the double-sided heat dissipation packaging module is characterized by comprising the following steps of:
providing a lower heat conducting substrate, wherein the lower heat conducting substrate comprises an upper surface and a lower surface which are oppositely arranged, the lower heat conducting substrate is provided with a leading-out terminal protruding out of the lower heat conducting substrate in the horizontal direction, and a chip to be packaged is fixed on the upper surface of the lower heat conducting substrate;
forming a bonding support frame on the upper surface of the lower heat conducting substrate, wherein the bonding support frame is positioned on the side edge of the chip to be packaged and is spaced from the chip to be packaged by a preset distance, the bonding support frame is in a trapezoid bridge type structure, the end part of the bonding support frame is connected with the lower heat conducting substrate in a bonding way, and the top end of the middle part of the bonding support frame is higher than the bonding lead on the upper surface of the chip to be packaged in the vertical direction;
providing an upper heat conducting substrate, wherein the upper heat conducting substrate comprises an upper surface and a lower surface which are oppositely arranged, and the top end of the bonding support frame is welded with the upper surface of the upper heat conducting substrate;
and forming a plastic layer, wherein the plastic layer coats the lower heat conducting substrate, the chip to be packaged and the upper heat conducting substrate.
2. The method for manufacturing the double-sided heat dissipation package module according to claim 1, wherein: the upper heat conductive substrate comprises a laminated aluminum nitride layer and a copper layer, wherein the copper layer is positioned on one side facing the lower heat conductive substrate.
3. The method for manufacturing the double-sided heat dissipation package module according to claim 1, wherein: the bonding support frame comprises a first bonding support frame and a second bonding support frame, the first bonding support frame is positioned on the left side of the chip to be packaged, and the second bonding support frame is positioned on the right side of the chip to be packaged; or the first bonding support frame is positioned on the upper side of the chip to be packaged, and the second bonding support frame is positioned on the lower side of the chip to be packaged.
4. The method for manufacturing the double-sided heat dissipation package module according to claim 1, wherein: the bonding support frame comprises a first bonding support frame, a second bonding support frame, a third bonding support frame and a fourth bonding support frame, wherein the first bonding support frame is positioned on the left side of a chip to be packaged, the second bonding support frame is positioned on the right side of the chip to be packaged, the third bonding support frame is positioned on the upper side of the chip to be packaged, and the fourth bonding support frame is positioned on the lower side of the chip to be packaged.
5. The method of manufacturing a dual sided heat spreader package of claim 1, wherein the bonding support frame comprises: and placing a pre-soldering lug between the upper surface of the upper heat conducting substrate and the bonding support frame, and welding the upper heat conducting substrate and the bonding support frame by adopting a vacuum welding method.
6. A dual sided heat dissipating package module, comprising:
the lower heat conducting substrate comprises an upper surface and a lower surface which are oppositely arranged, and the lower heat conducting substrate is provided with a leading-out terminal protruding out of the lower heat conducting substrate in the horizontal direction;
the chip to be packaged is positioned on the upper surface of the lower heat conducting substrate and fixedly connected with the lower heat conducting substrate;
the bonding support frame is positioned on the upper surface of the lower heat conducting substrate, the bonding support frame is positioned on the side edge of the chip to be packaged and is spaced from the chip to be packaged by a preset distance, the bonding support frame is in a trapezoid bridge type structure, the end part of the bonding support frame is connected with the lower heat conducting substrate in a bonding way, and the top end of the middle part of the bonding support frame is higher than the bonding lead on the upper surface of the chip to be packaged in the vertical direction;
the upper heat conducting substrate is positioned above the bonding support frame, and the top end of the bonding support frame is welded with the upper heat conducting substrate;
and the plastic layer is used for coating the lower heat conducting substrate, the chip to be packaged and the upper heat conducting substrate.
7. The dual sided heat sink packaging module of claim 6, wherein: the upper heat conductive substrate comprises a copper layer and an aluminum nitride layer which are stacked, wherein the copper layer is positioned on one side facing the lower heat conductive substrate.
8. The dual sided heat sink packaging module of claim 7, wherein: the thickness of the aluminum nitride layer ranges from 0.25mm to 1mm, and the thickness of the copper layer ranges from 0.5 mm to 1mm.
9. The dual sided heat sink packaging module of claim 6, wherein: the bonding support frame comprises a first bonding support frame and a second bonding support frame, the first bonding support frame is positioned on the left side of the chip to be packaged, and the second bonding support frame is positioned on the right side of the chip to be packaged; or the first bonding support frame is positioned on the upper side of the chip to be packaged, and the second bonding support frame is positioned on the lower side of the chip to be packaged.
10. The dual sided heat sink packaging module of claim 6, wherein: the bonding support frame comprises a first bonding support frame, a second bonding support frame, a third bonding support frame and a fourth bonding support frame, wherein the first bonding support frame is positioned on the left side of a chip to be packaged, the second bonding support frame is positioned on the right side of the chip to be packaged, the third bonding support frame is positioned on the upper side of the chip to be packaged, and the fourth bonding support frame is positioned on the lower side of the chip to be packaged.
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