JP7492375B2 - Semiconductor Device - Google Patents

Description

The present invention relates to a semiconductor device, for example a semiconductor device having a semiconductor chip connected to a chip connection portion via solder.

JP 2007-109834 A (Patent Document 1) describes a configuration in which solders of different compositions are arranged on the central surface and the outer peripheral surface of a semiconductor device in which a semiconductor chip is mounted via a solder bonding layer as a power IGBT module.

JP 2007-109834 A

Semiconductor devices called power semiconductor devices (power modules) have elements for controlling electric power. Power semiconductor devices are semiconductor devices in which power semiconductor chips are mounted via solder on chip connection parts such as a substrate, and heat dissipation members are connected as necessary. Power semiconductor devices require improved connection reliability of the solder alloy layer used to connect the semiconductor chips. Particularly in recent years, there has been progress in the development of power semiconductor chips that can operate at high temperatures. For this reason, power semiconductor devices require connection reliability in high-temperature environments.

The object of the present invention is to provide a technology that improves the connection reliability of the solder alloy layer interposed between the semiconductor chip and the chip connection part.

A semiconductor device according to one embodiment includes a first semiconductor chip having a first surface and a second surface opposite to the first surface, a first chip connection portion made of metal and connected to the second surface of the first semiconductor chip via a first solder alloy layer, the first solder alloy layer disposed between the second surface of the first semiconductor chip and the first chip connection portion, and a first intermetallic compound layer formed at the boundary between the second surface of the first semiconductor chip and the first solder alloy layer and having an uneven surface extending from the second surface side toward the first chip connection portion side. The second surface includes a first region including the center of the second surface and a second region including the periphery of the second surface. The thickness of the first intermetallic compound layer is such that the average thickness of the first portion overlapping the first region of the second surface is thicker than the average thickness of the second portion overlapping the second region.

A semiconductor device according to another embodiment includes a first semiconductor chip having a first surface and a second surface opposite to the first surface, a first chip connection portion made of metal and connected to the second surface of the first semiconductor chip via a first solder alloy layer, the first solder alloy layer disposed between the second surface of the first semiconductor chip and the first chip connection portion, and a first intermetallic compound layer formed at the boundary between the second surface of the first semiconductor chip and the first solder alloy layer and having an uneven surface extending from the second surface side toward the first chip connection portion side. The second surface includes a first region including the center of the second surface and a second region including the periphery of the second surface. The first intermetallic compound layer has a first portion overlapping the first region of the second surface and a second portion overlapping the second region. The height difference of the uneven surface in the first portion is greater than the height difference of the uneven surface in the second portion.

The invention disclosed in this application can improve the connection reliability of the solder alloy layer interposed between the semiconductor chip and the chip connection portion.

Issues, configurations and advantages other than those mentioned above will become clear from the description of the embodiments below.

1 is an explanatory diagram illustrating a configuration example of a semiconductor device according to an embodiment; 2 is an enlarged cross-sectional view showing the periphery of a solder alloy layer that electrically connects one of the semiconductor chips shown in FIG. 1 to a conductor pattern. FIG. 3 is a plan view of the lower surface side of the semiconductor chip shown in FIG. 2. FIG. 3 is an enlarged cross-sectional view showing the same enlarged cross section as FIG. 2, but clearly showing the range for comparing the thicknesses of the solder alloy layers. 4 is a plan view of the lower surface side of a semiconductor chip included in a semiconductor device that is a modified example of the semiconductor device shown in FIG. 3. 2 is a plan view of a conductor pattern on which the semiconductor chip shown in FIG. 1 is mounted. 3 is an enlarged cross-sectional view of the periphery of a semiconductor chip included in a semiconductor device which is a modified example of the semiconductor device shown in FIG. 2; 3 is an enlarged cross-sectional view showing a typical type of crack that occurs in a connection structure of a semiconductor device that is an example of a study on FIG. 2 . FIG.

In each of the figures for explaining the following embodiments, the same components are generally given the same reference numerals, and repeated explanations are omitted. Furthermore, functionally identical elements may be indicated by the same or corresponding numerals. Furthermore, in the following, hatching may be used even in plan views to make the drawings easier to understand. Note that the attached drawings show embodiments and implementation examples in accordance with the principles of this disclosure, but these are intended to aid in understanding this disclosure and are in no way intended to be used to interpret this disclosure in a restrictive manner. The descriptions in this specification are typical examples.

In this embodiment, the disclosure has been described in sufficient detail for a person skilled in the art to implement the disclosure, but it should be understood that other implementations and forms are possible, and that changes to the configuration and structure and substitutions of various elements are possible without departing from the scope and spirit of the technical ideas of the disclosure.

In the following description of the embodiment, a modularized semiconductor device (power semiconductor device, power module) in which multiple semiconductor chips are mounted via solder on a metal pattern formed on an insulating substrate is taken as an example of a semiconductor device. However, the technology described below can be applied to various modified examples of semiconductor devices that include semiconductor chips that are connected to chip connectors via solder.

In the following description of the embodiment, a metallic conductor pattern formed on an insulating substrate is used as an example of a chip connection portion to which a semiconductor chip is connected via a solder alloy layer. However, there are various variations in the chip connection portion, and examples include a lead member electrically connected to the semiconductor chip, a die pad of a lead frame supporting the semiconductor chip, or an electrode of another electronic component electrically connected to the semiconductor chip.

<Configuration Example of Semiconductor Device>
FIG. 1 is a cross-sectional view showing a schematic configuration example of a semiconductor device according to the present embodiment. The semiconductor device 100 has a plurality of semiconductor chips (semiconductor chips 10 and 20) and a substrate 30 on which the semiconductor chips 10 and 20 are mounted. The substrate 30 has an insulating substrate 31, a plurality of conductor patterns 32 formed on an upper surface 31t of the insulating substrate 31, and a conductor pattern 33 formed on a lower surface 31b of the insulating substrate 31. The semiconductor chips 10 and 20 are mounted on a conductor pattern 32A included in the plurality of conductor patterns 32. The substrate 30 on which the semiconductor chips 10 and 20 are mounted is mounted on a base plate 3 via a solder alloy layer 2. The substrate 30 mounted on the base plate 3 is covered with a cover 4 together with the semiconductor chips 10 and 20, and is accommodated in a space surrounded by the cover 4 and the base plate 3. The space surrounded by the cover 4 and the base plate 3 is filled with a sealant 5, which is, for example, a gel-like insulating material, and the semiconductor chips 10 and 20 and the wires 6 are sealed by the sealant 5.

The substrate 30 is formed by attaching a metal film to both sides of an insulating substrate 31, which is, for example, a ceramic substrate, and patterning the metal film to form a circuit. The substrate 30 can be DBC (Direct Bond Copper), which uses a metal mainly composed of copper as the conductor patterns 32 and 33, or DBA (Direct Bond Aluminum), which uses a metal mainly composed of aluminum as the conductor patterns 32 and 33. However, various metal materials can be used as materials for the chip mounting portion (chip connection portion) on which the semiconductor chips 10 and 20 are mounted. For example, even when connecting to a chip connection portion made of metals such as Cu, Al, Cu-Mo, Al-SiC (a composite material of aluminum and silicon carbide), Mg-SiC (a composite material of magnesium and silicon carbide), 42 Alloy, or CIC (Copper Invar Copper), the connection reliability of the solder alloy layer interposed between the semiconductor chip and the chip connection portion can be improved by applying the technology described below.

In the cross section shown in FIG. 1, the multiple conductor patterns 32 include conductor pattern 32A on which semiconductor chips 10 and 20 are mounted, conductor pattern 32B electrically connected to semiconductor chips 10 and 20 via wires 6, and conductor pattern 32C to which leads 7 are electrically connected. A portion of lead 7 is led out of cover 4 and connected to a terminal of semiconductor device 100. Alternatively, lead 7 itself is used as a terminal.

The semiconductor device 100 is an electronic component (power semiconductor device, power module) for power control incorporated in a power supply circuit. An example of a power module is an inverter using the semiconductor chips 10 and 20 as switching elements. The semiconductor device 100 is incorporated in a power supply device mounted on, for example, a railroad car, an automobile body, an aircraft, an industrial device, etc. In such applications, the semiconductor device 100 may be exposed to a high-temperature environment, and each component constituting the semiconductor device 100 is required to be reliable at high temperatures. For example, when SiC or GaN is used as the semiconductor substrate constituting the semiconductor chips 10 and 20, it is possible to operate at a higher temperature than when Si is used. For this reason, it is necessary to ensure the reliability of the connection at the part that electrically or thermally connects the semiconductor chips 10 and 20 to the chip connection part at a higher temperature.

As shown in FIG. 2, the semiconductor chip 10 has a metallized film 11 formed on the lower surface 10b and an electrode pad 12 formed on the upper surface 10t. The electrode pad 12 is electrically connected to the conductor pattern 32B via the wire 6 shown in FIG. 1. The metallized film 11 is electrically connected to the conductor pattern 32A via the solder alloy layer 40. The metallized film 11 and the electrode pad 12 each function as an electrode of the semiconductor chip 10. For example, when the semiconductor chip 10 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), one of the electrode pad 12 and the metallized film 11 is a source electrode, and the other is a drain electrode. For example, when the semiconductor chip 10 is a bipolar transistor, one of the electrode pad 12 and the metallized film 11 is an emitter electrode, and the other is a collector electrode. In the case of a transistor, in addition to the electrode pad 12, an electrode pad for a gate electrode is formed on the upper surface 10t. Also, for example, if the semiconductor chip 10 is a diode, one of the electrode pad 12 and the metallization film 11 is an anode electrode, and the other is a cathode electrode.

<Connection structure of semiconductor chip>
Based on the above, a configuration example of the present embodiment in which the reliability of the connection part between the semiconductor chip and the chip connection part is improved will be described. FIG. 2 is an enlarged cross-sectional view showing the periphery of the solder alloy layer electrically connecting one of the multiple semiconductor chips shown in FIG. 1 to the conductor pattern. FIG. 3 is a plan view of the lower surface side of the semiconductor chip shown in FIG. 2. FIG. 8 is an enlarged cross-sectional view showing the type of cracks that occur in the connection structure of a semiconductor device, which is an example of the connection structure of FIG. 2. In the following, the technology for improving the reliability of the connection part between the semiconductor chip and the chip connection part will be described by taking the connection structure of the semiconductor chip 10 and the conductor pattern 32A shown in FIG. 1 as an example. However, it is applicable to various parts connected via the solder alloy layer 40, such as the connection structure of the semiconductor chip 20 and the conductor pattern 32A.

As shown in FIG. 2, the semiconductor device 100 has a semiconductor chip 10, a conductor pattern 32A, a solder alloy layer 40, and an intermetallic compound layer 50. The semiconductor chip 10 has an upper surface 10t and a lower surface 10b opposite to the upper surface 10t. The conductor pattern 32A is made of a metal (e.g., Cu) and is connected to the lower surface 10b of the semiconductor chip 10 via the solder alloy layer 40. The intermetallic compound layer 50 is formed at the boundary between the lower surface 10b of the semiconductor chip 10 and the solder alloy layer 40, and has an uneven surface extending from the lower surface 10b side toward the conductor pattern 32A side. As shown in FIG. 3, the lower surface 10b of the semiconductor chip 10 has a region R1 including the center of the lower surface 10b, and a region R2 including the outer periphery of the lower surface 10b. As shown in FIG. 2, the average thickness of the intermetallic compound layer 50 at the portion 50R1 that overlaps with the region R1 (see FIG. 3) of the lower surface 10b is greater than the average thickness of the portion 50R2 that overlaps with the region R2 (see FIG. 3).

Below, we will explain the failure modes of the connection part using the semiconductor device 100C shown in Figure 8, and then explain why the connection structure of this embodiment shown in Figures 2 and 3 can improve the reliability of the connection part. According to the inventor's research, the failure modes that cause a decrease in the connection reliability of the solder alloy layer 40 that electrically connects the semiconductor chip 10 and the conductor pattern 32A can be broadly divided into the following two types.

First, there is a failure mode caused by thermal stress resulting from differences in the linear expansion coefficients of the components that make up the periphery of the connection. This first failure mode occurs in the outer peripheral portion of the solder alloy layer 40 (the portion close to the side of the semiconductor chip 10) and progresses toward the inside of the solder alloy layer 40, in other words, toward the central portion. When a crack CR1 occurs in the solder alloy layer 40 due to the first failure mode, a crack that extends in a direction along the bottom surface 10b of the semiconductor chip 10 is likely to occur. When repeated temperature cycle loads are applied, the crack CR1 extends toward the central portion.

The second failure mode is caused by deterioration of the solder alloy layer 40 in the semiconductor chip 10 due to heat generated when electricity is applied. This second failure mode occurs in the central portion, which has relatively poor heat dissipation characteristics. When cracks CR2 occur due to the second failure mode, they tend to occur in the thickness direction of the solder alloy layer 40 (in other words, in the out-of-plane direction of the lower surface 10b). When repeated temperature cycle loads are applied, the location where cracks CR2 occur expands from the central portion toward the outer periphery. In the case of this second failure mode, it is the expansion of the range in which cracks CR2 occur, rather than the occurrence of cracks CR2 itself, that causes a decrease in connection reliability.

In order to suppress the first failure mode, it is preferable to use a solder alloy with low elasticity. If the peripheral portion of the solder alloy layer 40 has low elasticity, it is possible to reduce thermal stress and suppress the occurrence of the crack CR1 that is the starting point, or the progression of the crack CR1 after it has occurred. In order to suppress the second failure mode, it is preferable to use a solder alloy layer 40 with high heat resistance in the center. However, when using different types of solder alloys, the degree of mixing of the two types of solder alloys changes depending on the conditions of the application process or the reflow conditions, so it is difficult to stably form two types of solder alloy layers at the designed position. Due to variations in manufacturing conditions, there is a possibility that the connection reliability will decrease. Therefore, it is preferable that the solder alloy layer 40 arranged between the semiconductor chip 10 and the conductor pattern 32A is made of one type of solder alloy.

The inventors of the present application therefore focused on providing a member at the connection interface of the central portion that prevents the location of crack CR2 from expanding from the central portion toward the peripheral portion as a method of suppressing the second failure mode. As shown in FIG. 2, in the case of this embodiment, portion 50R1 of intermetallic compound layer 50 corresponds to the member that prevents the location of crack CR2 from expanding from the central portion toward the peripheral portion.

The intermetallic compound layer 50 shown in FIG. 2 is a compound formed between the metal contained in the solder alloy layer 40 and the metal constituting the metallized film 11 formed on the lower surface 10b of the semiconductor chip 10. For example, in the case of the present embodiment, the solder alloy of the solder alloy layer 40 contains copper (Cu) and antimony (Sb) in addition to tin (Sn), and contains 0.7% by weight or more of copper. In addition, although a general lead-free solder can be used for the solder alloy constituting the solder alloy layer 40, it is preferable that it contains antimony and 0.7% by weight or more of copper. In addition, in consideration of improving the stress relaxation characteristics, Sn-3 to 5Cu-10Sb solder is particularly preferable. In addition, as a modified example of the solder alloy, for example, Sn-3 to 7Cu solder can be used. For the metallized film 11 of the semiconductor chip 10, various metals and alloys such as Cu, Ni, Au, Ag, Pt, Pd, Ti, TiN, Fe light alloys such as Fe-Ni and Fe-Co can be applied. For example, in the present embodiment, the metallized film 11 is made of nickel (Ni). In this case, the intermetallic compound layer is an intermetallic compound layer of Ni-Sn, which is the main metal component of the solder alloy and the metallized film 11.

The intermetallic compound layer 50 is formed by the reaction between the solder alloy and the metallized film 11 during the reflow process in which the semiconductor chip 10 is mounted on the conductor pattern 32A. Therefore, the intermetallic compound layer 50 grows downward (toward the conductor pattern 32A) from the lower surface 10b of the semiconductor chip 10, i.e., the metallized film 11. At this time, the intermetallic compound layer 50 is not formed uniformly, but is formed to form an uneven surface from the lower surface 10b side toward the conductor pattern 32A side, as shown in FIG. 2. If the height difference of this uneven surface is large, it is possible to suppress the cracks caused by the second failure mode described above from expanding to the outer periphery. In other words, in the case of this embodiment, by increasing the height difference of the uneven surface of the intermetallic compound layer 50, the cracks caused by the second failure mode are suppressed from expanding to the outer periphery.

On the other hand, the intermetallic compound layer 50 is fragile and easily damaged by external forces perpendicular to its growth direction. For this reason, if the intermetallic compound layer 50 is formed with an uneven surface with a large difference in height even on the outer periphery of the lower surface 10b of the semiconductor chip 10, the intermetallic compound layer 50 will be damaged due to thermal stress, which is the first failure mode described above. Therefore, from the viewpoint of suppressing the first failure mode, it is better for the uneven surface of the intermetallic compound layer 50 formed in the outer periphery to have a small difference in height.

Therefore, in the present embodiment, the intermetallic compound layer 50 is formed in the peripheral region so that the height difference of the uneven surface is small. More specifically, as shown in FIG. 3, the lower surface 10b of the semiconductor chip 10 has a region R1 including the center of the lower surface 10b, and a region R2 including the outer periphery of the lower surface 10b. As shown in FIG. 2, the intermetallic compound layer 50 has a portion 50R1 that overlaps with the region R1 (see FIG. 3) of the lower surface 10b, and a portion 50R2 that overlaps with the region R2 (see FIG. 3). The height difference of the uneven surface of the intermetallic compound layer 50 is greater in the portion 50R1 of the lower surface 10b than in the portion 50R2.

The height difference of the uneven surface of the intermetallic compound layer 50 can be formed, for example, as follows. The height difference of the uneven surface of the intermetallic compound layer 50 increases in proportion to the time of reflow processing in a state where the solder alloy and the metallized film 11 are in contact with each other. Therefore, in the reflow process, if the reflow process is started in a state where only the region R1 (see FIG. 3) of the lower surface 10b of the semiconductor chip 10 is in contact with the solder alloy, and the reflow process is controlled so that the solder alloy comes into contact with the region R2 during the reflow process, the connection structure shown in FIG. 2 can be manufactured. In this method, first, a paste or sheet-like solder alloy is applied (placed) on the conductor pattern 32A. Next, the semiconductor chip 10 is placed on the paste or sheet-like solder alloy. At this time, only the region R1 is in contact with the solder alloy, and the region R2 is not in contact with the solder alloy. Next, the solder alloy is heated as a heating process. At this time, an intermetallic compound layer is generated at the connection interface between the solder alloy and the lower surface 10b of the semiconductor chip 10, and grows toward the conductor pattern 32A. Next, the distance between the semiconductor chip 10 and the conductor pattern 32 is reduced. This causes the molten solder to spread around, and the solder alloy comes into contact with region R2 (see FIG. 3). When the solder alloy is heated again in this state, an intermetallic compound layer 50 is obtained in which the height difference between each part is controlled, as shown in FIG. 2.

In this case, the height difference of the uneven surface can be expressed as the average thickness of portion 50R1 (the average value of the distance from lower surface 10b to the apex of the multiple convex portions of the uneven surface) and the average thickness of portion 50R2. That is, as described above, the thickness of the intermetallic compound layer 50 is such that the average thickness of portion 50R1 overlapping with region R1 (see FIG. 3) of lower surface 10b is thicker than the average thickness of portion 50R2 overlapping with region R2 (see FIG. 3). In this case, the height difference of the uneven surface is large in portion 50R1, which has a thick average thickness, and the height difference of the uneven surface is small in portion 50R2, which has a thin average thickness.

Also, as a modified example of the method for forming the intermetallic compound layer 50, the following method is also available. That is, a metal film with an uneven shape is formed in advance in the region R1 (see FIG. 3) of the lower surface 10b so that the height difference of the intermetallic compound layer 50 is large. This metal film can be formed, for example, by a plating method. By selectively forming a metal film with unevenness in the region R1 by a plating method while the region R2 (see FIG. 3) is masked, the height difference of the intermetallic compound layer 50 can be controlled as shown in FIG. 2 even if reflow is started in a state where the solder alloy is in contact with the entire lower surface 10b during the reflow process.

In the case of the semiconductor device 100 of this embodiment, as described above, the height difference (in other words, the average thickness) of the uneven surface is different between the portion 50R1 and the portion 50R2, so that the first failure mode and the second failure mode described above can be suppressed. In addition, since the solder alloy layer 40 is made of one type of solder alloy, the connection structure shown in FIG. 2 can be stably realized. As a result, the connection reliability at the connection interface between the lower surface 10b of the semiconductor chip 10 and the solder alloy layer 40 can be improved.

In addition, since the solder alloy layer 40 connects the semiconductor chip 10 and the conductor pattern 32A, it is preferable that an intermetallic compound layer 60 similar to the intermetallic compound layer 50 is formed on the conductor pattern 32A side in addition to the lower surface 10b side of the semiconductor chip 10. In the case of this embodiment, as shown in FIG. 2, the conductor pattern 32A has an upper surface 32t that faces the entire lower surface 10b in a plan view of the semiconductor chip 10 viewed from the upper surface 10t. At the boundary between the upper surface 32t of the conductor pattern 32A and the solder alloy layer 40, an intermetallic compound layer 60 having an uneven surface from the upper surface 32t side toward the semiconductor chip 10 side is formed. The thickness of the intermetallic compound layer 60 is such that the average thickness of a portion 60R1 overlapping with the region R1 (see FIG. 3) of the lower surface 10b is thicker than the average thickness of a portion 60R2 overlapping with the region R2 (see FIG. 3).

The intermetallic compound layer 60 shown in FIG. 2 can be expressed as follows. The intermetallic compound layer 60 has a portion 60R1 that overlaps with region R1 (see FIG. 3) of the lower surface 10b, and a portion 60R2 that overlaps with region R2 (see FIG. 3). The height difference of the uneven surface of the intermetallic compound layer 60 is greater in portion 60R1 of the lower surface 10b than in portion 60R2. This can improve the connection reliability at the connection interface on the lower surface side of the solder alloy layer 40, in other words, at the connection interface between the solder alloy layer 40 and the conductor pattern 32.

In addition, from the viewpoint of improving the stress relaxation function of the solder alloy layer 40 at the outer periphery of the solder alloy layer 40, it is preferable to increase the thickness of the solder alloy layer 40 at the outer periphery. As shown in FIG. 4, the average thickness T2 of the portion 40R2 overlapping with the region R2 (see FIG. 3) of the lower surface 10b of the solder alloy layer 40 is thicker than the average thickness T1 of the portion 40R1 overlapping with the region R1 (see FIG. 3). In the present embodiment, the average thickness of the solder alloy layer 40 can be controlled by configuring the average thicknesses of the intermetallic compound layers 50 and 60 as described above. Note that FIG. 4 is an enlarged cross-sectional view of the same cross section as FIG. 2, but is shown as a separate view for ease of viewing the symbols.

By the way, there are various examples within the range of region R1 and region R2 shown in FIG. 3. In the following, a preferred embodiment from the viewpoint of improving connection reliability will be described. First, region R1 and region R2 are adjacent to each other. Region R1 can be defined as the portion of the lower surface 10b that is in contact with the paste or sheet-like solder alloy, which is the raw material of the solder alloy layer 40, at the start of the reflow process. Region R2 can be defined as the portion surrounding region R2, and as the region that comes into contact with the paste or sheet-like solder alloy after the start of the reflow process by spreading. When controlling the thickness (height difference) of the intermetallic compound layers 50 and 60 by the contact time during the reflow process, strictly speaking, the solder alloy gradually spreads from the central portion to the outer periphery, so that there is a region in the vicinity of region R1 where the thickness of the intermetallic compound layers 50 and 60 is thicker than that of the outermost periphery of region R2. In the present application, this region is considered to belong to region R2. As a modified example, if a metal film having an uneven surface is selectively formed in region R1, the region in which this metal film is formed can be defined as region R1, and the surrounding region as region R2.

In the above definition, in order to suppress damage to the intermetallic compound layers 50 and 60 (see FIG. 2), it is preferable that the range of region R1 is not too large. More specifically, region R2 is provided so as to surround region R1, and the area of region R2 is preferably larger than the area of region R1. By making the area of region R2 larger than the area of region R1, it is possible to suppress damage caused by thermal stress to portion 50R1 of intermetallic compound layer 50 and portion 60R1 of intermetallic compound layer 60, which have a large difference in height.

Ideally, the contour of region R1 is preferably a circle or an ellipse. If the shape of the lower surface 10b is a square, a circle is preferable. Also, if the shape of the lower surface 10b is a rectangle, an ellipse having a major axis in the direction along the long side is preferable. Also, if a perpendicular line (imaginary line) is drawn from the center of the lower surface 10b to each side of the lower surface 10b, region R1 is preferably positioned inside the circle or ellipse that passes through a position 80% of the total length of the perpendicular line toward the center.

In addition, in the above definition, it is preferable that the diameter length D1 of region R1 shown in FIG. 3 when converted to a circle is equal to or greater than 1/3 of the length L1 of one side when underside 10b is converted to a square. By increasing the area of region R1, it is possible to suppress the expansion of crack CR2 shown in FIG. 8 even if the location where crack CR2 occurs is shifted from the center. As will be described later, the shape of region R1 is not limited to a circle, and the shape of underside 10b is not limited to a square, but when comparing the approximate areas of each region, they can be evaluated using the values converted as described above.

In addition, from the viewpoint of suppressing the above-mentioned first and second failure modes, it is particularly preferable that the average thickness of portion 50R1 of intermetallic compound layer 50 is at least three times thicker than the average thickness of portion 50R2. Similarly, it is preferable that the average thickness of portion 60R1 of intermetallic compound layer 60 is at least three times thicker than the average thickness of portion 60R2.

<Modification 1>
Next, a modified example of the connection structure of the semiconductor device 100 shown in Fig. 2 will be described. Fig. 5 is a plan view of the underside of a semiconductor chip included in a semiconductor device which is a modified example of the semiconductor device shown in Fig. 3. This modified example is an effective technique when a plurality of semiconductor chips are arranged adjacent to each other at a close distance. The semiconductor device 200 described below is similar to the semiconductor device 100 described above, except that the positional relationship of the regions on the underside of the semiconductor chips 10 and 20 is different from that shown in Fig. 3. In the following description, Figs. 1 to 4 will be referred to as necessary.

As shown in FIG. 5, the semiconductor device 200 has a semiconductor chip 20 mounted next to the semiconductor chip 10 in a plan view, similar to the semiconductor device 100 shown in FIG. 1. The bottom surface 10b of the semiconductor chip 10 forms a quadrangle with a side 10s1 facing the semiconductor chip 20, a side 10s2 opposite the side 10s1, a side 10s3 intersecting with the sides 10s1 and 10s2, and a side 10s4 opposite the side 10s3. Region R1 is provided at a position closer to side 10s1 than side 10s2. In other words, region R1 is positioned closer to the semiconductor chip 20.

When multiple semiconductor chips are arranged adjacent to each other, such as the semiconductor chips 10 and 20, the locations on the lower surface 10b that are likely to become hot change compared to when one semiconductor chip 10 is arranged alone. The outer peripheral region of the semiconductor chip 10 is still more likely to dissipate heat than the central region. However, the central region closer to the side 10s1 (in other words, closer to the semiconductor chip 20) is more likely to become hot than the region closer to the side 10s2 (in other words, farther from the semiconductor chip 20). This is thought to be due to the presence of the semiconductor chip 20, which is another heat source, on the side 10s1 side, which reduces the heat dissipation characteristics. When the region R1 is provided at a position closer to the side 10s1 than the side 10s2, as in this embodiment, the region R1 is provided at a location where the crack CR2 described with reference to FIG. 8 is likely to occur. In this way, in the case of a semiconductor device having multiple semiconductor chips, it is preferable to specify the layout of the region R1 in consideration of the heat distribution associated with the positional relationship of the multiple semiconductor chips. This makes it possible to efficiently suppress the expansion of the location where the crack CR2 occurs.

However, from the viewpoint of suppressing the growth of the crack CR1 (see FIG. 8) caused by the first failure mode described above, it is preferable that the range of region R1 is not extremely close to side 10s1. Ideally, when a perpendicular line (imaginary line) is drawn from the center of the lower surface 10b to each side of the lower surface 10b (sides 10s1, 10s2, 10s3, and 10s4), region R1 is preferably positioned inside a circle or ellipse that passes through a position 80% of the total length of the perpendicular line toward the center.

5 shows an example in which the number of semiconductor chips is two, but the number of semiconductor chips is not limited to two. For example, the semiconductor device 200 shown in FIG. 6 has six semiconductor chips (semiconductor chips 10, 20, 10A, 20A, 10B, and 20B). FIG. 6 is a plan view of the conductor pattern on which the semiconductor chips shown in FIG. 1 are mounted. FIG. 6 is a plan view seen from the top side of the semiconductor chip, showing the range of regions R1 and R2 on the bottom surface. Alternatively, although not shown, four semiconductor chips may be mounted adjacent to each other in one semiconductor device. In this way, when multiple semiconductor chips are mounted adjacent to each other, it is preferable that the position of region R1 is positioned closer to the adjacent semiconductor chip. In addition, when semiconductor chips 10 and 10B are arranged on both sides, as in the semiconductor chip 10A shown in FIG. 6, the area of region R1 of semiconductor chip 10A may be larger than the area of region R1 of semiconductor chip 10. Although semiconductor chip 10A is mounted in a position where heat dissipation is more difficult than for semiconductor chips 10 and 10B, by increasing the area of the central region (region R1), the occurrence of the second failure mode described above can be suppressed.

<Modification 2>
Fig. 7 is an enlarged cross-sectional view of the periphery of a semiconductor chip provided in a semiconductor device which is a modification of Fig. 2. In this modification, an embodiment in which solder alloy layers are connected to the upper and lower surfaces of one semiconductor chip will be described.

The semiconductor device 300 differs from the semiconductor device 100 shown in FIG. 2 in that the conductor pattern 80 is connected to the electrode pad 12 on the upper surface 10t side via the solder alloy layer 70 in the structure of the semiconductor device 100 described using FIG. 2. The other points are the same as those of the semiconductor device 100 shown in FIG. 2, so duplicated explanations will be omitted.

The semiconductor device 300 has a conductor pattern (second chip connection portion) 80 made of metal and connected to the upper surface 10t of the semiconductor chip 10 via a solder alloy layer 70, and the solder alloy layer 70 disposed between the upper surface 10t of the semiconductor chip 10 and the conductor pattern 80.

The semiconductor device 300 also has an intermetallic compound layer 55 formed at the boundary between the upper surface 10t of the semiconductor chip 10 and the solder alloy layer 70, and having an uneven surface extending from the upper surface 10t side toward the conductor pattern 80 side. The thickness of the intermetallic compound layer 55 is such that the average thickness of a portion 55R1 overlapping with region R1 (see FIG. 3) of the lower surface 10b is greater than the average thickness of a portion 55R2 overlapping with region R2 (see FIG. 3).

The structure of the intermetallic compound layer 55 can also be expressed as follows. That is, the intermetallic compound layer 55 has a portion 55R1 that overlaps with region R1 (see FIG. 3) of the lower surface 10b, and a portion 55R2 that overlaps with region R2 (see FIG. 3). The height difference of the uneven surface of the intermetallic compound layer 55 is greater in portion 55R1 of the lower surface 10b than in portion 55R2. When the solder alloy layer 70 is connected to the upper surface 10t side of the semiconductor chip 10, the configuration of this modified example can improve the connection reliability of the connection interface between the solder alloy layer 70 and the electrode pad 12 of the semiconductor chip 10.

Similarly, the semiconductor device 300 has an intermetallic compound layer 65 formed at the boundary between the lower surface 80b of the conductor pattern 80 and the solder alloy layer 70, and having an uneven surface from the lower surface 80b side toward the upper surface 10t side of the semiconductor chip 10. The intermetallic compound layer 65 also has a portion 65R1 that overlaps with the region R1 (see FIG. 3) of the lower surface 10b, and a portion 65R2 that overlaps with the region R2 (see FIG. 3). The height difference of the uneven surface of the intermetallic compound layer 65 is greater in the portion 65R1 of the lower surface 10b than in the portion 65R2. The configuration of the modified example can improve the connection reliability of the connection interface between the solder alloy layer 70 and the conductor pattern 80.

Although the conductor pattern 80 has been taken up as an example of a chip connection portion connected to the semiconductor chip 10 via the solder alloy layer 70, it is also effective when attaching a component such as a heat sink. In the case of a heat sink, the occurrence and progression of the cracks CR1 and CR2 described in FIG. 8 cuts off the thermal path, resulting in a decrease in heat dissipation characteristics. By applying the above-mentioned structure, the decrease in heat dissipation characteristics can be suppressed. Although not shown, there are also cases where conductor patterns are connected to the upper and lower surfaces of each of the multiple semiconductor chips shown in FIG. 6, for example.

Although various modified examples have been described above, each modified example can be applied in combination as appropriate.

The above describes typical variations of this embodiment, but the present invention is not limited to the above examples and typical variations, and various variations can be applied within the scope of the spirit of the invention.

This invention can be used in optical devices.

2 solder alloy layer 3 base plate 4 cover 5 sealing material 6 wire 7 leads 10, 10A, 10B, 20, 20A, 20B semiconductor chip (semiconductor element)
10b Lower surface (reverse surface)
10s1, 10s2, 10s3, 10s4 Side 10t Top surface (surface)
11 Metallized film 12 Electrode pad 30 Substrate 31 Insulating substrate 31b Lower surface 31t, 32t Upper surface 32, 32A, 32B, 32C, 33 Conductive pattern 40, 70 Solder alloy layer 40R1, 40R2 Portion 50, 55, 60, 65 Intermetallic compound layer 50R1, 50R2, 55R1, 55R2, 60R1, 60R2, 65R1, 65R2 Portion 80 Conductive pattern (second chip connection portion)
80b Lower surface 100, 100C, 200, 300 Semiconductor device CR1, CR2 Crack R1 Region (central region)
R2 area (outer peripheral area)

Claims (10)

a first semiconductor chip having a first side and a second side opposite the first side;
a first chip connection portion made of metal and connected to the second surface of the first semiconductor chip via a first solder alloy layer;
the first solder alloy layer disposed between the second surface of the first semiconductor chip and the first chip connection portion;
a first intermetallic compound layer formed at a boundary between the second surface of the first semiconductor chip and the first solder alloy layer, the first intermetallic compound layer having an uneven surface extending from the second surface side toward the first chip connection portion side;
having
the second surface includes a first region including a center of the second surface and a second region including an outer periphery of the second surface;
A semiconductor device, wherein the first intermetallic compound layer has a thickness such that an average thickness of a first portion overlapping with a first region of the second surface is greater than an average thickness of a second portion overlapping with the second region. 2. The semiconductor device according to claim 1,
the first chip connection portion includes a third surface that faces the entire second surface in a plan view of the first semiconductor chip seen from the first surface side,
a second intermetallic compound layer having an uneven surface extending from the third surface side toward the first semiconductor chip side is formed at a boundary between the third surface of the first chip connection portion and the first solder alloy layer,
A semiconductor device, wherein the second intermetallic compound layer has a thickness such that an average thickness of a third portion overlapping with the first region of the second surface is greater than an average thickness of a fourth portion overlapping with the second region. 3. The semiconductor device according to claim 2,
A semiconductor device, wherein the thickness of the first solder alloy layer is greater in a fifth portion overlapping the second region of the second surface than in a sixth portion overlapping the first region. 4. The semiconductor device according to claim 3,
A semiconductor device, wherein the area of the second region is larger than the area of the first region. 5. The semiconductor device according to claim 4,
The first region and the second region are adjacent to each other,
A semiconductor device, wherein a diameter of the first region when converted into a circle is 1/3 or more of a length of one side of the second surface when converted into a square. 2. The semiconductor device according to claim 1,
A semiconductor device, wherein an average thickness of a first portion of the second surface overlapping with the first region is at least three times thicker than an average thickness of a second portion of the second surface overlapping with the second region. 2. The semiconductor device according to claim 1,
The semiconductor device, wherein the first solder alloy layer contains copper (Cu) and antimony (Sb) in addition to tin (Sn), and contains 0.7 wt % or more of copper. 2. The semiconductor device according to claim 1,
a second semiconductor chip mounted adjacent to the first semiconductor chip in a plan view;
the second surface of the first semiconductor chip forms a quadrangle having a first side facing the second semiconductor chip, a second side opposite the first side, a third side intersecting the first side and the second side, and a fourth side opposite the third side;
The first region is provided at a position closer to the first side than to the second side. 2. The semiconductor device according to claim 1,
a second chip connection portion made of metal and connected to the first surface of the first semiconductor chip via a second solder alloy layer;
the second solder alloy layer disposed between the first surface of the first semiconductor chip and the second chip connection portion;
a third intermetallic compound layer formed at a boundary between the first surface of the first semiconductor chip and the second solder alloy layer, the third intermetallic compound layer having an uneven surface extending from the first surface side toward the second chip connection portion side;
and
A semiconductor device, wherein the third intermetallic compound layer has a thickness such that an average thickness of a third portion overlapping with the first region of the first surface is greater than an average thickness of a fourth portion overlapping with the second region. a first semiconductor chip having a first side and a second side opposite the first side;
a first chip connection portion made of metal and connected to the second surface of the first semiconductor chip via a first solder alloy layer;
the first solder alloy layer disposed between the second surface of the first semiconductor chip and the first chip connection portion;
a first intermetallic compound layer formed at a boundary between the second surface of the first semiconductor chip and the first solder alloy layer, the first intermetallic compound layer having an uneven surface extending from the second surface side toward the first chip connection portion side;
having
the second surface includes a first region including a center of the second surface and a second region including an outer periphery of the second surface;
the first intermetallic compound layer has a first portion overlapping a first region of the second surface and a second portion overlapping the second region;
A semiconductor device, wherein the height difference of the uneven surface in the first portion is greater than the height difference of the uneven surface in the second portion.

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