CN116627665A

CN116627665A - Bus deadlock recovery method, device, equipment and storage medium

Info

Publication number: CN116627665A
Application number: CN202310616751.5A
Authority: CN
Inventors: 程竹晴; 张晓谦; 孙忠刚; 于鑫
Original assignee: FAW Group Corp
Current assignee: FAW Group Corp
Priority date: 2023-05-29
Filing date: 2023-05-29
Publication date: 2023-08-22

Abstract

The invention discloses a bus deadlock recovery method, a device, equipment and a storage medium. The method comprises the following steps: detecting an abnormal reset event of a target host connected with a target bus; under the condition that the target host computer generates an abnormal reset event, determining whether the target bus generates a bus deadlock event or not; under the condition that the target bus is subjected to a bus deadlock event, a slave restarting operation is executed on each target slave connected with the target bus, so that the target bus deadlock is recovered, the aim of recovering the bus deadlock without additional hardware cost is achieved, and meanwhile, the efficiency and the accuracy of recovering the bus deadlock can be improved.

Description

Bus deadlock recovery method, device, equipment and storage medium

Technical Field

The present invention relates to the field of communication recovery technologies, and in particular, to a method, an apparatus, a device, and a storage medium for recovering a bus deadlock.

Background

Data buses are an important theoretical basis for application system integration. The data bus is a bidirectional tri-state bus, namely, the data bus can transmit data of a host to other components or slaves such as a memory or an input/output interface, and can also transmit data of other components or slaves to the host, so that development time is greatly reduced.

The data bus is often composed of a serial data line SDA and a serial time line SCL. In the actual use process, the data bus is more prone to deadlock faults. In automotive electronic control systems, data bus deadlocks typically occur because of an abnormal reset of the host. The data bus deadlock caused by abnormal reset of the host cannot be avoided from the root, and the device or the method for recovering the data bus deadlock can be increased only through hardware or software to remedy the data bus deadlock timely.

The existing method for solving the deadlock of the data bus is that a bus buffer is connected in series between the slaves of the master on the bus, when the buffer detects that the deadlock occurs, the buffer automatically disconnects the connection with the master, and a clock signal is generated on the slave side to recover the bus. However, this approach requires additional hardware costs, which are not in line with the actual production requirements.

Disclosure of Invention

The invention provides a bus deadlock recovery method, a device, equipment and a storage medium, which do not need to increase hardware cost additionally, and can improve the efficiency and accuracy of bus deadlock recovery.

According to one aspect of the invention, a bus deadlock recovery method is provided. The method comprises the following steps: detecting an abnormal reset event of a target host connected with a target bus; under the condition that the target host computer generates an abnormal reset event, determining whether the target bus generates a bus deadlock event or not; and under the condition that the target bus is subjected to a bus deadlock event, executing a slave restarting operation on each target slave connected with the target bus so as to recover the target bus deadlock.

According to another aspect of the invention, a bus deadlock recovery device is provided. The device comprises:

the abnormal reset detection module is used for detecting an abnormal reset event of a target host connected with the target bus;

the bus deadlock determining module is used for determining whether the target bus has a bus deadlock event or not under the condition that the target host has an abnormal reset event;

and the slave restarting execution module is used for executing the slave restarting operation on each target slave connected with the target bus under the condition that the target bus is subjected to a bus deadlock event so as to recover the target bus deadlock.

According to another aspect of the present invention, there is provided an electronic apparatus including:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,,

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the bus deadlock recovery method according to any of the embodiments of the invention.

According to another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to implement the bus deadlock recovery method according to any of the embodiments of the present invention when executed.

According to the technical scheme, an abnormal reset event of a target host connected with a target bus is detected; under the condition that the target host computer generates an abnormal reset event, determining whether the target bus generates a bus deadlock event or not; under the condition that the target bus is subjected to a bus deadlock event, a slave restarting operation is executed on each target slave connected with the target bus, so that the target bus deadlock is recovered, the hardware cost is not required to be additionally increased, the hardware development cost is reduced, and meanwhile, the accuracy of the bus deadlock recovery can be improved.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of a method for recovering a bus deadlock according to a first embodiment of the invention;

fig. 2 is a flowchart of a bus deadlock recovery method according to a second embodiment of the present invention;

fig. 3 is a block diagram of a bus deadlock recovery device according to a third embodiment of the present invention;

fig. 4 is a schematic structural diagram of an electronic device implementing a bus deadlock recovery method according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Example 1

Fig. 1 is a flowchart of a bus deadlock recovery method according to an embodiment of the present invention, where the embodiment is applicable to a case of recovering a data bus deadlock, and in particular, to a case of recovering an I2C bus deadlock. The method may be performed by a bus deadlock recovery device, which may be implemented in hardware and/or software, which may be configured in an electronic device. As shown in fig. 1, the method includes:

s101, detecting an abnormal reset event of a target host connected with a target bus.

In the technical scheme of the invention, the target bus can be an I2C bus. The target host may refer to a host connected to the target bus. For example, at a certain moment, a certain task of the target host operates abnormally, a timeout error occurs, namely, a dog is not fed correctly, at the moment, the watchdog loses a dog feeding signal, a reset signal is sent to a reset pin of the target host, and at the moment, an abnormal reset event of the target host can be detected through the fault detection unit.

S102, under the condition that the target host computer generates an abnormal reset event, determining whether the target bus generates a bus deadlock event.

Specifically, in the case of determining that the target host has an abnormal reset event, it is necessary to further detect whether the target bus has a deadlock event. When the target bus is in a deadlock event, the target host and all external devices cannot normally communicate.

Illustratively, the determining whether the target bus has a bus deadlock event includes: respectively detecting the serial data line and the level information corresponding to the serial time line; and determining whether the target bus is subjected to a bus deadlock event according to the level information corresponding to the serial data line and the level information corresponding to the serial time line.

Specifically, determining whether the target bus has a bus deadlock event may be performed by determining from level information corresponding to each serial line in the target bus.

It should be noted that the target bus includes a serial data line SDA and a serial time line SCL. The level signals of the serial data line SDA and the serial time line SCL are both high in the idle state. The serial timeline SCL may be controlled by the target host, sending time pulses. The serial data line SDA may be controlled by a target host or a target slave corresponding to the target host to perform data transmission. When the serial data line SDA is switched from the high level to the low level, the start signal is indicated. When serial data line SDA is switched from low to high, serial time line SCL indicates a stop signal. In the effective transmission process between the two signals, the serial time line SCL is a periodic time pulse, and the serial data line SDA represents the actually transmitted data through the high-low level, and only when the serial time line SCL is at the low level, the serial data line SDA can be switched between the high-low level, i.e. effective data transmission is performed.

Illustratively, the determining whether the target bus generates a bus deadlock event according to the level information corresponding to the serial data line and the level information corresponding to the serial time line includes: with the serial data line going low and the serial time line going high, a determination is made as to whether a bus deadlock event has occurred for the target bus.

It should be noted that the bus deadlock event appears as serial timeline SCL being always high and serial data line SDA being always low. The deadlock fault occurs because when the data transmission of the slave device is not finished, the clock signal of the target host disappears, at this time, the slave device keeps the serial data line SDA in a pulled-down state to wait for the clock period of the target host, so that the sending of the response signal can be completed, but the clock signal before the target host disappears, the serial time line SCL is released to a high level, at this time, the target host detects that the serial data line SDA is at a low level, considers that the target bus is occupied, waits for the slave device to send a stop signal, and thus, the slave device enters a deadlock state that the target host waits for the slave to release the serial data line SDA, and the slave device waits for the target host to pull down the serial time line SCL.

S103, under the condition that the target bus is subjected to a bus deadlock event, executing a slave restarting operation on each target slave connected with the target bus so as to recover the target bus deadlock.

The target slave may refer to an external device connected to and communicating with the target host, such as an external EEPROM, a display driving chip, a sensor, and the like. The slave reboot operation may refer to rebooting the target slave.

Specifically, when it is determined that the target bus has a bus deadlock event, the slave is re-operated for each target slave, so that the target bus deadlock phenomenon is recovered.

Illustratively, before the performing a slave restart operation on each target slave connected to the target bus, the method further includes: modifying the deadlock mark information in the target bus into deadlock occurrence mark information; and stopping communication between the target host and the target slave based on the deadlock occurrence identification information.

The deadlock mark information is used for indicating whether a deadlock event occurs to the target bus. The communication state between the target host and the target slave can be controlled based on the deadlock identification information. Illustratively, the deadlock identification information may include deadlock occurrence identification information and deadlock elimination identification information.

Specifically, after determining that the target bus has a deadlock event, or before performing a slave restart operation on the target slave, the deadlock flag information may be modified to deadlock occurrence identification information, and any communication between the target host and the target slave may be stopped based on the deadlock occurrence identification information.

It should be noted that, in the technical solution of the present invention, the target host must be built with a target bus module, such as an I2C module, and directly connected to the target slave through the serial data line SDA and the serial time line SCL, without other modules or units that can occupy or reset the bus;

before the target host computer is abnormally reset, the communication state of the target bus is normal, and the target slave computer communicated with the target host computer is not damaged. After the target host is abnormally reset and the target bus is deadlocked, unlocking can not be performed in a mode of resetting the host, and the target host and the target slave can not communicate;

the RST pin or the power supply pin of the target slave is directly or indirectly connected with the IO interface of the target host. The target host can control a certain target slave machine through the high-low level conversion of the interface, and hard reset or power-off restarting is carried out, so that the target slave machine is restored to an initial state, and the continuous pull-down state of the serial data line SDA is relieved;

the target host software is provided with a bus fault detection unit which is used for detecting the state of the target bus after the abnormal reset of the target host and reporting faults to the system. The target fault recovery unit is used for unlocking the target bus and notifying the system fault release;

the target host system has the read permission of the flag bit, and the fault detection and fault recovery unit has the read permission of the flag bit. The system can read the zone bit, control the on-off of system communication according to whether the fault occurs, and record the zone bit information for reporting the diagnosis information of the whole vehicle. The fault detection and recovery unit can modify the flag bit according to the detection or recovery of the fault, and indicates the deadlock fault state at the current moment.

Example two

Fig. 2 is a flowchart of a bus deadlock recovery method according to a second embodiment of the present invention, where the restart operation of each target slave connected to the target bus is further refined based on the foregoing embodiment. As shown in fig. 2, the method includes:

s201, detecting an abnormal reset event of a target host connected with a target bus.

S202, under the condition that the target host computer generates an abnormal reset event, determining whether the target bus generates a bus deadlock event.

S203, under the condition that the target bus is subjected to a bus deadlock event, determining the slave priority of all the target slaves.

Wherein the slave priority is determined based on a communication frequency between the target slave and the target master.

The communication frequency of the target slave is stored in the target master.

Since the occurrence of the fault is derived from abnormal reset of the host, the communication condition before the reset cannot be saved, and the target slave is not damaged, it cannot be confirmed which target slave hangs down the serial data line SDA bus. The target slave with higher communication frequency, which occupies the serial data line SDA for a longer time, is more likely to occur during communication with the peripheral at the time of abnormal reset of the master. And under the condition that the target bus is subjected to a bus deadlock event, determining the slave priorities of all target slaves according to the communication frequency of the target slaves, wherein the higher the frequency is, the higher the priority is. Illustratively, three target slaves are mounted on the target bus, an IMU sensor for detecting acceleration and angular velocity, a temperature sensor for monitoring temperature, and an EEPROM for data storage, respectively. The POST reset pin of the target host is connected with the reset signal pin of a watchdog of a certain target slave. Under the normal running state of the system, the communication periods of the target bus module of the target host, the IMU sensor, the temperature sensor and the EEPROM are respectively 1ms,5ms and 1s, and the priority of the slave is the IMU sensor, the temperature sensor and the EEPROM.

S204, based on the slave priority, sequencing all the target slaves according to a rule from high to low to obtain a slave priority sequence.

Specifically, according to the slave priority corresponding to the target slave, all target slaves are ordered according to a priority rule from high to low, and a slave priority sequence is obtained.

S205, sequentially acquiring the target slave machines based on the machine priority sequence, and executing slave machine restarting operation on the acquired target slave machines so as to enable the target bus deadlock to be recovered.

Specifically, the slave priority sequence sequentially acquires the target slave, and executes the slave restarting operation on the target slave, and after all the target slaves execute the slave restarting operation, the target bus deadlock can be recovered.

Illustratively, determining whether the target bus resumes normal communication; under the condition that the target bus resumes normal communication, modifying deadlock flag information in the target bus into deadlock elimination flag information; communication between the target host and the target slave is allowed based on the deadlock elimination identification information.

It should be noted that, according to the technical scheme of the invention, after each target slave machine executes the slave machine restarting operation, the communication detection on the target bus can be performed, and after the normal communication of the target bus is determined, the slave machine restarting operation on the other target slave machines is not required to be executed, so that the bus deadlock recovery efficiency is improved. The failure recovery unit in the target host may perform communication testing on a single target slave. When a deadlock fault exists, the target bus is locked, and any target slave cannot communicate with the target host.

Under the condition that the target bus resumes normal communication, the deadlock flag information in the target bus is modified to deadlock elimination identification information, and normal communication between the target host and the target slave is allowed according to the deadlock elimination identification information.

Illustratively, the determining whether the target bus resumes normal communication includes: respectively detecting the serial data line and the level information corresponding to the serial time line; and determining that the target bus resumes normal communication in the case where both the serial data line and the serial time line are continuously high.

Specifically, the test mode is to read the status register of the corresponding target slave machine through the bus frame. And judging whether the deadlock fault disappears according to a communication test result between the single target slave and the target host. When the target bus resumes an idle state in which both serial timeline SCL and serial data line SDA are high, indicating that the target bus is deadlocked, any peripheral device may communicate with the host.

For example, the priority order of the slaves is determined according to the priority order of the slaves, that is, the IMU sensor is the highest, the temperature sensor is the next lowest, and the EEPROM is the lowest. The slave priority sequence is stored in a list. The fault recovery unit starts from the IMU sensor with the highest priority, outputs a reset signal to the reset pin of the IMU sensor through the pin, and the IMU sensor can conduct hard reset. After the IMU sensor is reset, the fault recovery unit performs a single-piece communication test on the IMU sensor, tries to read the content of a state register of the IMU sensor, finds that the IMU sensor still cannot read the content, and the bus is still in a deadlock state, so that the serial data line SDA is proved not to be pulled down by the IMU sensor. And according to the priority sequence of the slave, the fault recovery unit controls the power supply pin of the temperature sensor to finish one-time power-off restarting. After the temperature sensor is restarted, the temperature sensor is subjected to communication test, the content of a status register is read, normal communication with the temperature sensor is found, frame data accords with the sensor definition, the serial data line SDA is proved to be pulled down by the temperature sensor, the serial data line SDA is released to be high level through power-off restarting, and the deadlock state of the bus is relieved.

According to the technical scheme, the slave priority of all the target slaves is determined, wherein the slave priority is determined based on the communication frequency between the target slaves and the target master. And based on the slave priority, ordering all the target slaves according to a rule from high to low to obtain a slave priority sequence. And sequentially acquiring the target slave machines based on the machine priority sequence, executing the slave machine restarting operation on the acquired target slave machines, and executing the slave machine restarting operation on the target slave machines according to the slave machine priority, so that the deadlock fault recovery efficiency can be improved.

Example III

Fig. 3 is a schematic structural diagram of a bus deadlock recovery device according to a third embodiment of the present invention.

As shown in fig. 3, the apparatus includes:

an abnormal reset detection module 301, configured to detect an abnormal reset event of a target host connected to the target bus;

a bus deadlock determination module 302, configured to determine, in a case where an abnormal reset event occurs in the target host, whether a bus deadlock event occurs in the target bus;

and the slave restarting execution module 303 is configured to execute a slave restarting operation on each target slave connected to the target bus, so that the target bus deadlock is recovered, in the case that the target bus has a bus deadlock event.

Optionally, the target bus includes a serial data line and a serial time line; the bus deadlock determination module 302 includes:

a level information determining unit for detecting the serial data line and the level information corresponding to the serial time line respectively;

and the bus deadlock determining unit is used for determining whether the target bus generates a bus deadlock event according to the level information corresponding to the serial data line and the level information corresponding to the serial time line.

Optionally, the bus deadlock determination unit is specifically configured to:

with the serial data line going low and the serial time line going high, a determination is made as to whether a bus deadlock event has occurred for the target bus.

Optionally, the apparatus further comprises:

the mark information modification module is used for modifying deadlock mark information in the target bus into deadlock occurrence identification information before the slave restarting operation is executed on each target slave connected with the target bus; and stopping communication between the target host and the target slave based on the deadlock occurrence identification information.

Optionally, the slave reboot execution module 303 includes:

a slave priority determining unit configured to determine slave priorities of all the target slaves, where the slave priorities are determined based on a communication frequency between the target slaves and the target master;

the slave priority ranking unit is used for ranking all target slaves according to a rule from high to low based on the slave priority to obtain a slave priority sequence;

and the slave restarting execution unit is used for sequentially acquiring the target slave based on the slave priority sequence and executing slave restarting operation on the acquired target slave.

Optionally, the flag information modification module may be further configured to:

after the slave restarting operation is performed on each target slave connected with the target bus, determining whether the target bus resumes normal communication;

under the condition that the target bus resumes normal communication, modifying deadlock flag information in the target bus into deadlock elimination flag information;

communication between the target host and the target slave is allowed based on the deadlock elimination identification information.

Optionally, the flag information modification module may be further specifically configured to:

respectively detecting the serial data line and the level information corresponding to the serial time line;

and determining that the target bus resumes normal communication in the case where both the serial data line and the serial time line are continuously high.

The bus deadlock recovery device provided by the embodiment of the invention can execute the bus deadlock recovery method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

Example IV

Fig. 4 shows a schematic diagram of the structure of an electronic device 10 that may be used to implement an embodiment of the invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Electronic equipment may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 4, the electronic device 10 includes at least one processor 11, and a memory, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, etc., communicatively connected to the at least one processor 11, in which the memory stores a computer program executable by the at least one processor, and the processor 11 may perform various appropriate actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from the storage unit 18 into the Random Access Memory (RAM) 13. In the RAM13, various programs and data required for the operation of the electronic device 10 may also be stored. The processor 11, the ROM12 and the RAM13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.

Various components in the electronic device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, etc.; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.

The processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as method bus deadlock recovery.

In some embodiments, the method bus deadlock recovery may be implemented as a computer program, tangibly embodied on a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 10 via the ROM12 and/or the communication unit 19. When a computer program is loaded into RAM13 and executed by processor 11, one or more of the steps of method bus deadlock recovery described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform method bus deadlock recovery by any other suitable means (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.

The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. A method for recovering a bus deadlock, comprising:

detecting an abnormal reset event of a target host connected with a target bus;

under the condition that the target host computer generates an abnormal reset event, determining whether the target bus generates a bus deadlock event or not;

and under the condition that the target bus is subjected to a bus deadlock event, executing a slave restarting operation on each target slave connected with the target bus so as to recover the target bus deadlock.

2. The method of claim 1, wherein the target bus comprises a serial data line and a serial time line; the determining whether the target bus has a bus deadlock event includes:

and determining whether the target bus is subjected to a bus deadlock event according to the level information corresponding to the serial data line and the level information corresponding to the serial time line.

3. The method according to claim 2, wherein determining whether the target bus has a bus deadlock event according to the level information corresponding to the serial data line and the level information corresponding to the serial time line comprises:

4. The method of claim 1, further comprising, prior to performing a slave reboot operation on each target slave connected to the target bus:

modifying the deadlock mark information in the target bus into deadlock occurrence mark information;

and stopping communication between the target host and the target slave based on the deadlock occurrence identification information.

5. The method of claim 1, wherein performing a slave reboot operation on each target slave connected to the target bus comprises:

determining the slave priorities of all the target slaves, wherein the slave priorities are determined based on the communication frequency between the target slaves and the target host;

based on the slave priority, sequencing all the target slaves according to a rule from high to low to obtain a slave priority sequence;

and sequentially acquiring the target slave machines based on the machine priority sequence, and executing slave machine restarting operation on the acquired target slave machines.

6. The method of claim 1, further comprising, after performing a slave reboot operation on each target slave connected to the target bus:

determining whether the target bus resumes normal communication;

7. The method of claim 6, wherein the determining whether the target bus resumes normal communication comprises:

8. A bus deadlock recovery apparatus, comprising:

9. An electronic device, the electronic device comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,,

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the bus deadlock recovery method of any of claims 1-7.

10. A computer readable storage medium storing computer instructions for causing a processor to implement the bus deadlock recovery method of any of claims 1-7 when executed.