CN204808188U - Mainboard restarts system - Google Patents
Mainboard restarts system Download PDFInfo
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- CN204808188U CN204808188U CN201520411330.XU CN201520411330U CN204808188U CN 204808188 U CN204808188 U CN 204808188U CN 201520411330 U CN201520411330 U CN 201520411330U CN 204808188 U CN204808188 U CN 204808188U
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Abstract
An embodiment of the utility model provides a mainboard restarts system, include: mainboard and setting are in detector on the mainboard, the mainboard includes that main CPU and mainboard restart the circuit, the detector respectively with main CPU with the mainboard restarts circuit connection, the detector is in the in -process that main CPU starts passes through the detector with connection between the main CPU detects after the mainboard appears unusually, through the detector with the mainboard restart between the circuit the connection to the mainboard restarts circuit output and restarts alarm signal, the mainboard restarts the circuit, through the mainboard restart the circuit with connection between the detector is received restart alarm signal, and according to it restarts to restart alarm signal the mainboard. Thereby solved that the trouble has appeared in CPU among the prior art in the start -up course, can't restart CPU's problem, avoided the CPU deadlock state to appear.
Description
Technical Field
The embodiment of the utility model provides a relate to integrated circuit technical field, especially relate to a mainboard system of restarting.
Background
The computer is composed of hardware and software, after the system power supply of the computer is stable, a Central Processing Unit (CPU) in the computer performs initialization setting and startup loading of the hardware according to a software program, and the computer can normally operate only after initialization and loading are completed. After the computer normally works, the CPU can normally communicate with the north-south bridge, if the CPU is abnormal in work, the CPU can send an abnormal signal to the north-south bridge, and the north-south bridge controls the restart circuit to restart the CPU according to the abnormal signal.
However, if the CPU fails during the startup process, and the CPU cannot communicate with the north bridge or the south bridge at this time, the CPU cannot be controlled to restart, so that the CPU is in a dead halt state.
SUMMERY OF THE UTILITY MODEL
An embodiment of the utility model provides a mainboard system of restarting for solve among the prior art CPU trouble, the unable problem that restarts CPU have appeared in the start-up process, avoided CPU to appear the crash state.
The embodiment of the utility model provides a mainboard restarts system, include:
the detector comprises a main board and a detector arranged on the main board; the mainboard comprises a main CPU and a mainboard restarting circuit; the detector is respectively connected with the main CPU and the mainboard restarting circuit;
the detector outputs a restart notification signal to the mainboard restart circuit through the connection between the detector and the mainboard restart circuit after detecting that the mainboard is abnormal through the connection between the detector and the main CPU in the process of starting the main CPU;
the mainboard restarting circuit receives the restarting notification signal through the connection between the mainboard restarting circuit and the detector, and restarts the mainboard according to the restarting notification signal.
In an embodiment of the present invention, the main CPU is connected to the detector through a general purpose input/output (GPIO) port.
In an embodiment of the present invention, the main CPU outputs a signal to the detector through the GPIO port;
after the detector does not receive the preset signal output by the GPIO port of the main CPU through the connection between the detector and the main CPU, the detector does not receive the preset signal output by the GPIO port of the main CPU through the connection between the detector and the main CPU within the preset time, and then the abnormity of the mainboard is detected.
In an embodiment of the present invention, the detector is a timer;
specifically, the timer starts counting down from the preset time when the preset signal output by the GPIO port of the main CPU is not received through the connection between the timer and the main CPU, and if the preset signal is not received through the connection between the timer and the main CPU when the counting down time is zero, the abnormality of the main board is detected.
In an embodiment of the present invention, the detector passes through the detector and the connection between the main CPU does not receive the preset signal output by the GPIO port of the main CPU is: the detector does not receive a signal output by a GPIO port of the main CPU through the connection between the detector and the main CPU; or,
the detector receives a signal output by a GPIO port of the main CPU through the connection between the detector and the main CPU, and the signal output by the GPIO port of the main CPU is not the preset signal.
The embodiment of the utility model provides a mainboard restarting system, through set up a detector outside main CPU, this detector can communicate with main CPU at the in-process that main CPU starts, and then whether the detector detects the mainboard through being connected between this detector and this main CPU and appears unusually, when detecting the mainboard and appearing unusually, this detector restarts the circuit through this detector and mainboard and is connected between restarting the circuit and send to the mainboard and restart the notice signal to the mainboard, make the mainboard restart the circuit restart this mainboard according to restarting the notice signal. Therefore, the problems that the CPU fails to restart in the starting process in the prior art are solved, and the CPU is prevented from being in a dead halt state.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a first embodiment of a motherboard restarting system according to the present invention;
fig. 2 is a schematic structural diagram of a second embodiment of the motherboard restarting system of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Fig. 1 is a schematic structural diagram of a first embodiment of a motherboard restarting system according to the present invention, as shown in fig. 1, the motherboard restarting system of this embodiment includes a motherboard 10 and a detector 20 disposed on the motherboard 10; the motherboard 10 includes a main CPU11 and a motherboard restart circuit 12, wherein the detector 20 is connected to the main CPU11 and the motherboard restart circuit 12, respectively. The detector 20 outputs a restart notification signal to the motherboard restart circuit 12 through the connection between the detector 20 and the motherboard restart circuit 12 after detecting that the motherboard 10 is abnormal through the connection between the main CPU11 and the detector 20 during the startup of the main CPU 11; the motherboard restart circuit 12 receives the restart notification signal through the connection between the motherboard restart circuit 12 and the detector 20, and restarts the motherboard 10 according to the restart notification signal.
In this embodiment, during the startup process of the main CPU11, the detector 20 may communicate with the main CPU11 through the connection between the detector 20 and the main CPU11, when an abnormality of the motherboard 10 is detected through the connection between the detector 20 and the main CPU11, since the detector 20 is connected to the motherboard restart circuit 12, the detector 20 may output a restart notification signal to the motherboard restart circuit 12 through the connection between the detector 20 and the motherboard restart circuit 12, and the motherboard restart circuit 12 restarts the motherboard 10 according to the restart notification signal, for example: the motherboard restart circuit 12 outputs a restart signal to the main CPU 11.
In this embodiment, a detector is disposed outside the main CPU, and the detector can communicate with the main CPU in the process of starting the main CPU, so as to detect whether the main board is abnormal through the connection between the detector and the main CPU, and when the main board is detected to be abnormal, the detector outputs a restart notification signal to the main board restart circuit through the connection between the detector and the main board restart circuit, so that the main board restart circuit restarts the main board according to the restart notification signal. Therefore, the problems that the CPU fails to restart in the starting process in the prior art are solved, and the CPU is prevented from being in a dead halt state.
Alternatively, during startup of the main CPU11, some of the devices in the main CPU11 may be operational while others are not yet operational (including devices communicating with north and south bridges), and during startup of the main CPU11, for example: the GPIO port in the main CPU11 is active, and therefore, the main CPU11 is connected to the detector 20 through the GPIO port; specifically, the GPIO port of the main CPU11 is connected to the detector 20, and the main CPU11 outputs a signal to the detector 20 through the GPIO port of the main CPU11, thereby achieving communication between the main CPU11 and the detector 20, so that the detector 20 can detect whether an abnormality occurs in the main board 10 through the connection between the detector 20 and the main CPU 11.
Optionally, during the startup of the main CPU11, the detector 20 detects whether the main board 10 is abnormal through the connection between the detector 20 and the main CPU11 specifically: the main CPU11 outputs a signal to the detector 20 through the GPIO port; after the detector 20 does not receive the preset signal output by the GPIO port of the main CPU11 through the connection between the detector 20 and the main CPU11, if the preset signal is not received within the preset time, it detects that the main board 10 is abnormal.
Specifically, the main CPU11 outputs a signal to the detector 20 through the GPIO port during the startup process, the detector 20 receives a signal output by the GPIO port of the main CPU11 through the connection between the detector 20 and the main CPU11, and when the detector 20 detects that the signal output by the GPIO of the main CPU11 is a preset signal, the detector 20 detects that the main board 10 is in a normal state; if the detector 20 does not receive the preset signal output from the GPIO port of the main CPU11 through the connection between the detector 20 and the main CPU11 and the preset signal output from the GPIO port of the main CPU11 is not received through the connection between the detector 20 and the main CPU11 after the preset time, the detector 20 detects that the main board 10 is abnormal, but if the detector 20 receives the preset signal output from the GPIO port of the main CPU11 through the connection between the detector 20 and the main CPU11 within the preset time, the detector 20 detects that the main board 10 is in a normal state.
Fig. 2 is a schematic structural diagram of a second embodiment of the motherboard restarting system of the present invention, as shown in fig. 2, in this embodiment, on the basis of the first embodiment of the present invention, the detector 20 is a timer 30; specifically, the timer 30 starts counting down from the preset time when the preset signal output from the GPIO port of the main CPU11 is not received through the connection between the timer 30 and the main CPU11, and detects that the motherboard 10 is abnormal if the preset signal is not received through the connection between the timer 30 and the main CPU11 when the count-down is zero, and outputs a restart notification signal to the motherboard restart circuit 12 through the connection between the timer 30 and the motherboard restart circuit 12.
Specifically, the main CPU11 outputs a signal to the timer 30 through the GPIO port during the start-up process; the timer 30 receives a signal output by the GPIO port of the main CPU11 through the connection between the timer 30 and the main CPU11, and when the timer 30 detects that the signal output by the GPIO port of the main CPU11 is a preset signal, the timer 30 detects that the main board 10 is in a normal state; if the timer 30 does not receive the preset signal output from the GPIO port of the main CPU11 through the connection between the timer 30 and the main CPU11, the timer 30 starts to count down from the preset time, and if the preset signal output from the GPIO port of the main CPU11 is not received through the connection between the timer 30 and the main CPU11 when the count down is zero, the timer 30 detects that the main board 10 is abnormal, but if the timer 30 starts to count down from the preset time, and if the preset signal output from the GPIO port of the main CPU11 is received through the connection between the timer 30 and the main CPU11 before the count down is zero, the timer 30 detects that the main board 10 is in a normal state.
In this embodiment, a timer 30 that can communicate with the main CPU11 during the start of the main CPU11 is provided outside the main CPU11, the timer 30 detects whether an abnormality occurs in the main board 10 through the connection with the main CPU11, and when an abnormality occurs, a restart notification signal is output to the main board restart circuit 12 through the connection between the timer 30 and the main board restart circuit 12, so that the main board restart circuit 12 restarts the main board 10 according to the restart notification signal. Therefore, the problems that the CPU fails to restart in the starting process in the prior art are solved, and the CPU is prevented from being in a dead halt state.
Alternatively, one possible implementation manner that the detector 20 does not receive the preset signal output by the GPIO port of the main CPU11 through the connection between the detector 20 and the main CPU11 is as follows: the detector 20 described above does not receive any signal output from the GPIO port of the main CPU11 through the connection between the detector 20 and the main CPU 11.
Alternatively, one possible implementation manner that the detector 20 does not receive the preset signal output by the GPIO port of the main CPU11 through the connection between the detector 20 and the main CPU11 is as follows: the above-described detector 20 receives a signal output from the GPIO port of the main CPU11 through the connection between the detector 20 and the main CPU11, but the signal output from the GPIO port of the main CPU11 is not a preset signal.
For example: the preset signal is a high level signal, and if the detector 20 receives a low level signal output by the GPIO port of the main CPU11 through the connection between the detector 20 and the main CPU11, it may be determined that the preset signal is not received; if the detector 20 does not receive the high level signal or the low level signal output from the GPIO port of the main CPU11 through the connection between the detector 20 and the main CPU11, it may be determined that the preset signal is not received.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.
Claims (5)
1. A motherboard reboot system, comprising: the detector comprises a main board and a detector arranged on the main board; the mainboard comprises a main CPU and a mainboard restarting circuit; the detector is respectively connected with the main CPU and the mainboard restarting circuit;
the detector outputs a restart notification signal to the mainboard restart circuit through the connection between the detector and the mainboard restart circuit after detecting that the mainboard is abnormal through the connection between the detector and the main CPU in the process of starting the main CPU;
the mainboard restarting circuit receives the restarting notice signal through the connection between the mainboard restarting circuit and the detector, and restarts the mainboard according to the restarting notice signal.
2. The system of claim 1, wherein the main CPU is connected to the detector through a general purpose input output GPIO port.
3. The system of claim 2, wherein the main CPU outputs a signal to the detector through the GPIO port;
after the detector does not receive the preset signal output by the GPIO port of the main CPU through the connection between the detector and the main CPU, the detector still does not receive the preset signal output by the GPIO port of the main CPU through the connection between the detector and the main CPU within the preset time, and then the abnormity of the mainboard is detected.
4. The system of claim 3, wherein the detector is a timer;
specifically, the timer starts counting down from the preset time when the preset signal output by the GPIO port of the main CPU is not received through the connection between the timer and the main CPU, and if the preset signal is not received through the connection between the timer and the main CPU when the counting down time is zero, the abnormality of the main board is detected.
5. The system according to claim 3 or 4, wherein the detector does not receive the preset signal output by the GPIO port of the main CPU through the connection between the detector and the main CPU, and the preset signal is: the detector does not receive a signal output by a GPIO port of the main CPU through the connection between the detector and the main CPU; or,
the detector receives a signal output by a GPIO port of the main CPU through the connection between the detector and the main CPU, and the signal output by the GPIO port of the main CPU is not the preset signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520411330.XU CN204808188U (en) | 2015-06-15 | 2015-06-15 | Mainboard restarts system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520411330.XU CN204808188U (en) | 2015-06-15 | 2015-06-15 | Mainboard restarts system |
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| CN204808188U true CN204808188U (en) | 2015-11-25 |
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| CN201520411330.XU Active CN204808188U (en) | 2015-06-15 | 2015-06-15 | Mainboard restarts system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111830889A (en) * | 2019-04-16 | 2020-10-27 | 中车大连电力牵引研发中心有限公司 | Power supply control device and power supply |
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2015
- 2015-06-15 CN CN201520411330.XU patent/CN204808188U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111830889A (en) * | 2019-04-16 | 2020-10-27 | 中车大连电力牵引研发中心有限公司 | Power supply control device and power supply |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee after: Loongson Zhongke Technology Co.,Ltd. Address before: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee before: LOONGSON TECHNOLOGY Corp.,Ltd. |
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| CP01 | Change in the name or title of a patent holder |