CN116243742A - Temperature monitoring system, method, equipment and storage medium of domain controller - Google Patents
Temperature monitoring system, method, equipment and storage medium of domain controller Download PDFInfo
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- CN116243742A CN116243742A CN202310319548.1A CN202310319548A CN116243742A CN 116243742 A CN116243742 A CN 116243742A CN 202310319548 A CN202310319548 A CN 202310319548A CN 116243742 A CN116243742 A CN 116243742A
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- G05—CONTROLLING; REGULATING
- G05D—SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES
- G05D23/00—Control of temperature
- G05D23/19—Control of temperature characterised by the use of electric means
- G05D23/20—Control of temperature characterised by the use of electric means with sensing elements having variation of electric or magnetic properties with change of temperature
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a temperature monitoring system, a method, equipment and a storage medium of a domain controller, wherein the system comprises the following components: the device comprises a micro control unit, a first board end temperature monitoring node, a second board end temperature monitoring node and a chip core junction temperature monitoring node, wherein the micro control unit comprises the micro control unit core junction temperature monitoring node. The temperature monitoring system of the domain controller disclosed by the invention monitors the junction temperature of the core of the micro control unit, the junction temperature of the core of the system-level chip, the temperature of the board end of the micro control unit and the temperature of the board end of the system-level chip through the micro control unit, so that the micro control unit executes the domain controller temperature judgment logic, a high-reliability temperature monitoring method of the domain controller system level is formed, and the system is more suitable for a driving auxiliary system with high calculation power.
Description
Technical Field
The present invention relates to the field of intelligent automobiles, and in particular, to a temperature monitoring system, method, device and storage medium for a domain controller.
Background
Because a single SOC of the row-parking integrated ADAS domain controller has entered a 250TOPS powerful age, the corresponding SOC is high power of 105W in a full power operation script, so that a sharp temperature rise effect is brought to an SOC power chip and surrounding multi-core MCU circuits.
For an ADAS domain controller with low calculation power, the junction temperature of an SOC (state of charge) inner core of the domain controller generally cannot reach the upper limit junction temperature of 125 ℃ of a vehicle-mounted chip, so that the prior art generally only uses traditional vehicle body air cooling to make a cooling strategy.
The existing method is not suitable for the use scene of the high-power ADAS domain controller, and if the domain controller system is abnormal in operation or the air cooling equipment is in fault, the problem of untimely cooling is easy to generate, and the ADAS function level can be possibly lowered. In addition, the prior art only depends on a hardware over-temperature protection mechanism of the SOC chip, but a set of temperature monitoring method of a domain controller level does not exist, and if the hardware over-temperature mechanism of the chip fails, the safety risk of the vehicle function can be directly caused.
Disclosure of Invention
The invention provides a temperature monitoring system, a temperature monitoring method, temperature monitoring equipment and a storage medium of a domain controller, so as to monitor the temperatures of a plurality of nodes in the domain controller.
According to an aspect of the present invention, there is provided a temperature monitoring system of a domain controller, including: the device comprises a micro control unit, a first board end temperature monitoring node, a second board end temperature monitoring node and a chip core junction temperature monitoring node, wherein the micro control unit comprises the micro control unit core junction temperature monitoring node;
The first board end temperature monitoring node is used for acquiring the first board end temperature of a first printed circuit board corresponding to the micro control unit and responding to a first query instruction sent by the micro control unit, and sending the first board end temperature to the micro control unit;
the second board end temperature monitoring node is used for acquiring the second board end temperature of a second printed circuit board corresponding to the system-level chip and responding to a second query instruction sent by the micro control unit, and sending the second board end temperature to the micro control unit;
the chip core junction temperature monitoring node is used for collecting a second core junction temperature of the system-level chip and responding to a third query instruction sent by the micro control unit to send the second core junction temperature to the micro control unit;
the micro control unit is used for respectively sending the first query instruction, the second query instruction and the third query instruction to the first board end temperature monitoring node, the second board end temperature monitoring node and the chip core junction temperature monitoring node, respectively judging rationality according to the received first board end temperature, the second core junction temperature and the first core junction temperature of the micro control unit acquired by the micro control unit core junction temperature monitoring node, and executing corresponding response actions according to judgment results.
Optionally, the micro control unit is specifically configured to:
monitoring interrupt pins of the first board end temperature monitoring node and the second board end temperature monitoring node;
when the potential of the interrupt pin of the first board-end temperature monitoring node is reduced, sending the first query instruction to the first board-end temperature monitoring node through a serial bus;
and when the potential of the interrupt pin of the second board-end temperature monitoring node is reduced, sending the second query instruction to the second board-end temperature monitoring node through a serial bus.
Optionally, the micro control unit is specifically configured to:
setting temperature thresholds corresponding to the first plate end temperature and the second plate end temperature respectively;
and when the temperature of the first board end and/or the temperature of the second board end does not accord with the corresponding temperature threshold value, reporting a fault pin to the power management chip.
Optionally, after reporting the fault pin to the power management chip, the micro control unit is further configured to:
when the potential of the interrupt pin of the first board end temperature monitoring node is normal, a fourth query instruction is sent to the first board end temperature monitoring node through a serial bus;
when the potential of the interrupt pin of the second board end temperature monitoring node is normal, a fifth query instruction is sent to the second board end temperature monitoring node through a serial bus;
If the temperature of the first board end and the temperature of the second board end meet the corresponding temperature threshold values, fault recovery information is reported to the power management chip;
correspondingly, the first board end temperature monitoring node is further used for responding to the fourth query instruction and sending the first board end temperature to the micro control unit; the second board end temperature monitoring node is further configured to respond to the fifth query instruction, and send the second board end temperature to the micro control unit.
Optionally, the micro control unit communicates with the junction temperature monitoring node of the chip core through an ethernet.
Optionally, the micro control unit is specifically configured to:
receiving the second core junction temperature, and if the second core junction temperature does not accord with a preset temperature interval, adding one to the value of the counting zone bit;
if the value of the counting zone bit is larger than a first set value, reporting temperature acquisition failure information to a client application layer, and zeroing the counting zone bit; and if the value of the counting zone bit is smaller than or equal to the first set value and the junction temperature of the second core is larger than the early warning threshold value, reporting the abnormal information of the junction temperature of the core to a power management chip.
Optionally, the micro control unit is further configured to:
if the second core junction temperature accords with the preset temperature interval and the difference between the second core junction temperature and the last received second core junction temperature is larger than a second set value, adding one to the value of the counting zone bit;
if the second core junction temperature accords with a preset temperature interval and the difference between the second core junction temperature and the last received second core junction temperature is smaller than or equal to the second set value, reporting chip core junction temperature abnormality information to the power management chip when the second core junction temperature is larger than the early warning threshold value.
Optionally, the micro control unit is specifically configured to:
reading a temperature upper limit value and a temperature lower limit value corresponding to the first kernel junction temperature preset in a thermal state register, and sending the temperature upper limit value and the temperature lower limit value to a power management chip;
if the first core junction temperature is greater than the upper temperature limit value or less than the lower temperature limit value, reporting abnormal core junction temperature information of the micro control unit to the power management chip.
According to another aspect of the present invention, there is provided a temperature monitoring method for a domain controller, the method being used for a temperature monitoring system of the domain controller, the system including a micro control unit, a first board end temperature monitoring node, a second board end temperature monitoring node, and a chip core junction temperature monitoring node, wherein the micro control unit includes a micro control unit core junction temperature monitoring node, the method including:
Collecting the first board end temperature of a first printed circuit board corresponding to the micro control unit through the first board end temperature monitoring node, and responding to a first query instruction sent by the micro control unit to send the first board end temperature to the micro control unit;
acquiring the temperature of a second board end of a second printed circuit board corresponding to a system-level chip through the temperature monitoring node of the second board end, and responding to a second query instruction sent by the micro control unit to send the temperature of the second board end to the micro control unit;
collecting a second core junction temperature of the system-level chip through the core junction temperature monitoring node of the chip, and responding to a third query instruction sent by the micro control unit, and sending the second core junction temperature to the micro control unit;
and sending the first query instruction, the second query instruction and the third query instruction to the first board end temperature monitoring node, the second board end temperature monitoring node and the chip core junction temperature monitoring node through the micro control unit respectively, carrying out rationality judgment according to the received first board end temperature, the second core junction temperature and the first core junction temperature of the micro control unit acquired by the micro control unit core junction temperature monitoring node, and executing corresponding response actions according to judgment results.
Further, the sending, by the micro control unit, the first query instruction and the second query instruction to the first board end temperature monitoring node and the second board end temperature monitoring node, respectively, includes:
the micro control unit is used for respectively monitoring interrupt pins of the first board end temperature monitoring node and the second board end temperature monitoring node;
when the potential of the interrupt pin of the first board-end temperature monitoring node is reduced, sending the first query instruction to the first board-end temperature monitoring node through a serial bus;
and when the potential of the interrupt pin of the second board-end temperature monitoring node is reduced, sending the second query instruction to the second board-end temperature monitoring node through a serial bus.
Further, the micro control unit is used for performing rationality judgment according to the received first board end temperature and the received second board end temperature respectively, and executing corresponding response actions according to the judgment result, and the method comprises the following steps:
setting temperature thresholds corresponding to the first plate end temperature and the second plate end temperature respectively;
and when the temperature of the first board end and/or the temperature of the second board end does not accord with the corresponding temperature threshold value, reporting a fault pin to the power management chip.
Further, after reporting the fault pin to the power management chip, the method further includes:
when the potential of the interrupt pin of the first board end temperature monitoring node is normal, a fourth query instruction is sent to the first board end temperature monitoring node through a serial bus;
when the potential of the interrupt pin of the second board end temperature monitoring node is normal, a fifth query instruction is sent to the second board end temperature monitoring node through a serial bus;
if the temperature of the first board end and the temperature of the second board end meet the corresponding temperature threshold values, fault recovery information is reported to the power management chip;
correspondingly, the method further comprises the step of responding to the fourth query instruction through the first board end temperature monitoring node and sending the first board end temperature to the micro control unit; and responding to the fifth query instruction through the second board end temperature monitoring node, and sending the second board end temperature to the micro control unit.
Further, the micro control unit is communicated with the junction temperature monitoring node of the chip core through Ethernet.
Further, the micro control unit performs rationality judgment according to the received junction temperature of the second core, and performs corresponding response actions according to the judgment result, including:
Receiving the second core junction temperature, and if the second core junction temperature does not accord with a preset temperature interval, adding one to the value of the counting zone bit;
if the value of the counting zone bit is larger than a first set value, reporting temperature acquisition failure information to a client application layer, and zeroing the counting zone bit; and if the value of the counting zone bit is smaller than or equal to the first set value and the junction temperature of the second core is larger than the early warning threshold value, reporting the abnormal information of the junction temperature of the core to a power management chip.
Further, the method further comprises:
if the second core junction temperature accords with the preset temperature interval and the difference between the second core junction temperature and the last received second core junction temperature is larger than a second set value, adding one to the value of the counting zone bit;
if the second core junction temperature accords with a preset temperature interval and the difference between the second core junction temperature and the last received second core junction temperature is smaller than or equal to the second set value, reporting chip core junction temperature abnormality information to the power management chip when the second core junction temperature is larger than the early warning threshold value.
Further, the rationality judgment is performed by the micro control unit according to the received first core junction temperature of the micro control unit, which is collected by the core junction temperature monitoring node of the micro control unit, and corresponding response actions are executed according to the judgment result, including:
Reading a temperature upper limit value and a temperature lower limit value corresponding to the first kernel junction temperature preset in a thermal state register, and sending the temperature upper limit value and the temperature lower limit value to a power management chip;
if the first core junction temperature is greater than the upper temperature limit value or less than the lower temperature limit value, reporting abnormal core junction temperature information of the micro control unit to the power management chip.
According to another aspect of the present invention, there is provided an electronic apparatus including:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,,
the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the method of monitoring the temperature of the domain controller according to any one of the embodiments of the present invention.
According to another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to implement the temperature monitoring method of the domain controller according to any one of the embodiments of the present invention when executed.
The temperature monitoring system of the domain controller disclosed by the invention monitors the junction temperature of the core of the micro-control unit, the junction temperature of the core of the system-level chip, the temperature of the board end of the micro-control unit and the temperature of the board end of the system-level chip through the micro-control unit, so that the micro-control unit executes the domain controller temperature judgment logic, a high-reliability temperature monitoring method of the domain controller system level is formed, and the system is more suitable for an ADAS driving auxiliary system with high calculation power.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a temperature monitoring system of a domain controller according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram showing internal connection of a temperature monitoring system of a domain controller according to a first embodiment of the present invention;
FIG. 3 is a schematic diagram of a temperature monitoring process of a domain controller according to a first embodiment of the present invention;
FIG. 4 is a flow chart of a method for monitoring the temperature of a domain controller according to a second embodiment of the present invention;
fig. 5 is a schematic structural diagram of an electronic device implementing a temperature monitoring method of a domain controller according to a third embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
Fig. 1 is a schematic structural diagram of a temperature monitoring system of a domain controller according to a first embodiment of the present invention, where the present embodiment is applicable to controlling a temperature of a domain controller of an ADAS driving assistance system of a vehicle, the temperature monitoring system of the domain controller may be implemented in a hardware and/or software manner, and the temperature monitoring system of the domain controller may be configured in an electronic device. As shown in fig. 1, the system includes: the micro control unit 110, the first board end temperature monitoring node 120, the second board end temperature monitoring node 130 and the chip core junction temperature monitoring node 140, wherein the micro control unit 110 comprises a micro control unit core junction temperature monitoring node 111.
The first board end temperature monitoring node 120 is configured to collect a first board end temperature of a first printed circuit board corresponding to the micro control unit 110, and send the first board end temperature to the micro control unit 110 in response to a first query command sent by the micro control unit 110.
The second board end temperature monitoring node 130 is configured to collect a second board end temperature of a second printed circuit board corresponding to the system-on-chip, and send the second board end temperature to the micro control unit 110 in response to a second query command sent by the micro control unit 110.
The core junction temperature monitoring node 140 is configured to collect a second core junction temperature of the system-on-chip, and send the second core junction temperature to the micro control unit 110 in response to a third query instruction sent by the micro control unit 110.
The micro control unit 110 is configured to send a first query instruction, a second query instruction, and a third query instruction to the first board end temperature monitoring node 120, the second board end temperature monitoring node 130, and the chip core junction temperature monitoring node 140, respectively, and perform a rationality judgment according to the received first board end temperature, the second core junction temperature, and the first core junction temperature of the micro control unit 110 acquired by the micro control unit core junction temperature monitoring node 111, and execute a corresponding response action according to a judgment result.
Wherein the printed circuit board (Printed Circuit Board, PCB) is a carrier for electrical interconnection of electronic components fabricated by electronic printing. A System On Chip (SOC) is an integrated circuit with a dedicated target that contains the complete System and has the entire contents of embedded software. The micro control unit (Microcontroller Unit, MCU) is a chip-level computer formed by properly reducing the frequency and specification of the CPU (Central Process Unit), and integrating peripheral interfaces such as memory (Timer), USB, A/D conversion, UART, PLC, DMA, and the like, and even LCD driving circuits on a single chip, so that different combination control can be performed for different application occasions. The working temperature range of the PCB is generally between 0 ℃ and 125 ℃, the failure of the PCB can be caused by the too high or too low temperature, the core junction temperature is the highest temperature of an actual semiconductor chip (wafer and bare chip) in the electronic equipment, and in order to ensure the running reliability of the chip, the SOC core junction temperature and the MCU core junction temperature also have corresponding reasonable temperature ranges, so that the temperature of each board end and the core junction temperature need to be monitored, and the protection treatment is timely carried out when the temperature is abnormal.
In this embodiment, the first printed circuit board is a PCB board connected to the micro control unit 110, the second printed circuit board is a PCB board connected to the system-on-chip, the first board end temperature (MCU-PCB board end temperature) and the second board end temperature (SOC-PCB board end temperature) are respectively collected through the first board end temperature monitoring node 120 and the second board end temperature monitoring node 130, the first core junction temperature (MCU core junction temperature) is collected through the micro control unit core junction temperature monitoring node 111 inside the micro control unit 110, and the second core junction temperature (SOC core junction temperature) is collected through the chip core junction temperature monitoring node 140 inside the SOC. Each temperature monitoring node may be a chip node with a temperature sensor that may collect temperature and communicate with the micro-control unit 110. The micro control unit 110 includes a micro control unit core junction temperature monitoring node 111, which can monitor temperatures of temperature acquisition nodes including MCU-PCB board end temperature, SOC-PCB board end temperature, MCU core junction temperature and SOC core junction temperature, and determine whether the temperatures of the nodes are in a reasonable range, so as to execute corresponding response actions.
Optionally, the micro control unit 110 is specifically configured to:
Monitoring interrupt pins of the first board end temperature monitoring node 120 and the second board end temperature monitoring node 130; when the potential of the interrupt pin of the first board end temperature monitoring node 120 is reduced, a first query command is sent to the first board end temperature monitoring node 120 through the serial bus; when the interrupt pin potential of the second board temperature monitoring node 130 decreases, a second query command is sent to the second board temperature monitoring node 130 through the serial bus.
In this embodiment, for the first board temperature monitoring node 120 and the second board temperature monitoring node 130, the micro control unit 110 may monitor their interrupt pins (SHDN), and when detecting that the interrupt pin potential is pulled down, the micro control unit 110 issues a query instruction, where the first query instruction corresponds to the first board temperature monitoring node 120 and the second query instruction corresponds to the second board temperature monitoring node 130. Further, the micro control unit 110 and the first and second board side temperature monitoring nodes 120 and 130 may communicate through a serial bus.
Preferably, the serial bus may be an IIC bus, IIC (Inter-Integrated Circuit) being an integrated circuit bus, which is a serial communication bus using a multi-master-slave architecture. The micro control unit 110 sends a query instruction to the first board end temperature monitoring node 120 and the second board end temperature monitoring node 130 through the IIC bus, so that after receiving the query instruction, the micro control unit can respond to the board end temperature at the time through the IIC bus to the built-in SMU (safety management unit, security management unit) of the micro control unit 110.
Optionally, the micro control unit 110 is specifically configured to:
setting temperature thresholds corresponding to the first plate end temperature and the second plate end temperature respectively; and when the temperature of the first board end and/or the temperature of the second board end do not accord with the corresponding temperature threshold value, reporting a fault pin to the power management chip.
In this embodiment, reasonable temperature thresholds corresponding to the first board end temperature (MCU-PCB board end temperature) and the second board end temperature (SOC-PCB board end temperature) may be set by the micro control unit 110. After the ADAS ECU (advanced driving assistance system electronic control unit) is powered on, according to the temperature information fed back by the first board end temperature monitoring node 120 and the second board end temperature monitoring node 130, if the first board end temperature and/or the second board end temperature do not meet the corresponding temperature threshold, an SMU in the micro control unit 110 may send a signal to a Power-Management-IC (PMIC) through a fault pin (Error pin).
Further, the PMIC may enter an Abnormal mode of power management according to the received fault information, so that the SOC is powered down normally and maintained not to be started. The PMIC may also control the ADAS ECU domain controller to restart via a Reset signal.
Preferably, after the PMIC controls the ADAS ECU to power up, the micro control unit 110 may configure the registers of the first board end temperature monitoring node 120 and the second board end temperature monitoring node 130 through the IIC bus, write reasonable temperature thresholds corresponding to the first board end temperature (MCU-PCB board end temperature) and the second board end temperature (SOC-PCB board end temperature) into the first board end temperature monitoring node 120 and the second board end temperature monitoring node 130, respectively, and write status codes corresponding to different temperatures at the same time. When the first board end temperature monitoring node 120 and the second board end temperature monitoring node 130 respond to the query instruction of the micro control unit 110 to send the board end temperature to the first board end temperature monitoring node, the status code corresponding to the currently acquired temperature can be responded to the built-in SMU of the micro control unit 110 through the IIC bus. For example, if the first board end temperature exceeds the preset temperature threshold, the micro control unit 110 detects that the electric potential of the interrupt pin of the first board end temperature monitoring node 120 is reduced, and then sends a first query command to the interrupt pin, the first board end temperature monitoring node 120 responds to the micro control unit 110 through the IIC bus by a status code representing that the temperature is too high, and meanwhile, the status code may also correspond to a fault identifier (Error ID), and reports the Error ID representing the over-temperature fault to the micro control unit 110.
Optionally, after reporting the fault pin to the power management chip, the micro control unit 110 is further configured to:
when the potential of the interrupt pin of the first board end temperature monitoring node 120 is normal, a fourth query instruction is sent to the first board end temperature monitoring node 120 through the serial bus; when the interrupt pin potential of the second board end temperature monitoring node 130 is normal, a fifth query instruction is sent to the second board end temperature monitoring node 130 through the serial bus; if the temperature of the first board end and the temperature of the second board end meet the corresponding temperature threshold values, fault recovery information is reported to the power management chip;
correspondingly, the first board-end temperature monitoring node 120 is further configured to respond to a fourth query instruction, and send the first board-end temperature to the micro control unit 110; the second board end temperature monitoring node 130 is further configured to send the second board end temperature to the micro control unit 110 in response to the fifth query command.
In this embodiment, the micro control unit 110 may also control the fault recovery of the first board end temperature monitoring node 120 and the second board end temperature monitoring node 130. Taking the temperature monitoring of the second board end temperature as an example, when the second board end temperature monitoring node 130 detects that the board end temperature is recovered to be normal, the SHDN potential of the interrupt pin is pulled up again, and at this time, the micro control unit 110 sends a query instruction to the second board end temperature monitoring node 130, so that the micro control unit responds to the currently acquired second board end temperature information. After the micro control unit 110 confirms that the temperature is recovered, the Error ID is reset, and the built-in SMU of the micro control unit 110 sends an SOC start-up instruction to the power management chip PMIC through the fault pin Error pin to start up the SOC. Similarly, when the first board-side temperature is recovered to be normal, the first board-side temperature monitoring node 120 also transmits temperature recovery information to the micro control unit 110 in the same manner.
Optionally, the micro control unit 110 communicates with the chip core junction temperature monitoring node 140 via ethernet.
In this embodiment, the micro control unit 110 and the core junction temperature monitoring node 140 may communicate with each other by using 1000M ethernet or 100M vehicle-mounted ethernet. Alternatively, IIC buses may be used, as well as other communication lines within the ADAS domain controller, including, but not limited to PCIE (peripheral component interconnect express), UART (Universal Asynchronous Receiver/Transmitter), SPI (Serial Peripheral Interface), and the like.
Optionally, the micro control unit 110 is specifically configured to:
receiving the second core junction temperature, and if the second core junction temperature does not accord with a preset temperature interval, adding one to the value of the counting zone bit; if the value of the counting zone bit is larger than the first set value, reporting temperature acquisition failure information to a client application layer, and zeroing the counting zone bit; if the value of the counting zone bit is smaller than or equal to the first set value and the junction temperature of the second core is larger than the early warning threshold value, reporting abnormal information of the junction temperature of the core to the power management chip.
In this embodiment, when the micro control unit 110 monitors the second core junction temperature (SOC core junction temperature), after the SOC is started and the micro control unit 110 is successfully handshaked, the micro control unit 110 may send a third query instruction to the SOC through ethernet to request the second core junction temperature, and initialize the count flag Error Counter. The chip core junction temperature monitoring node 140 inside the SOC collects the second core junction temperature and sends it to the micro control unit 110. According to a preset temperature interval (for example, the temperature may be-45-135 ℃) corresponding to the junction temperature of the second core, the microcontrol unit 110 performs a rationality check on the junction temperature of the second core, and if the junction temperature does not conform to the preset temperature interval, discards the temperature acquired in the present period and makes Error counter+1. Setting the first set value as 5, when the Error Counter is more than 5, namely, the junction temperature of the second core received for more than 5 times does not accord with a preset temperature interval, reporting the temperature acquisition failure information to a client application layer, and zeroing the Error Counter; if the Error Counter is less than or equal to 5, the junction temperature of the second core is further judged, and if the junction temperature of the second core is greater than an early warning threshold (for example, 110 ℃) the abnormal information of the junction temperature of the core is reported to a PMIC (power management chip) and is reported to a client application layer.
Further, when the junction temperature of the second core is greater than the early warning threshold, the micro control unit 110 may also send a shutdown signal to the PMIC through an error pin, so that the PMIC turns off the SOC high-power rail.
Optionally, the micro control unit 110 is further configured to:
if the junction temperature of the second core accords with the preset temperature interval and the difference between the junction temperature of the second core and the junction temperature of the second core received last time is larger than a second set value, the value of the counting zone bit is increased by one; if the second core junction temperature accords with the preset temperature interval and the difference between the second core junction temperature and the last received second core junction temperature is smaller than or equal to a second set value, reporting the abnormal information of the core junction temperature to the power management chip when the second core junction temperature is larger than the early warning threshold value.
In this embodiment, in order to accurately determine the junction temperature of the second core, the micro control unit 110 may perform anti-shake elimination processing on the received temperature value, that is, compare the junction temperature of the second core currently received with the junction temperature of the second core received last time, and if the difference between the two is greater than the second set value, make Error counter+1. For example, let the second Core junction temperature currently received be SOC-Core (a), the second Core junction temperature last received be SOC-Core (b), if the second set value is 20, then Error counter+1 when SOC-Core (a) -SOC-Core (b) > 20 (°c). Further, if the second core junction temperature accords with the preset temperature interval and the difference between the second core junction temperature and the last received second core junction temperature is smaller than or equal to a second set value, reporting the abnormal information of the core junction temperature of the chip to the power management chip when the second core junction temperature is larger than the early warning threshold value.
Further, if the micro control unit 110 does not receive the second core junction temperature after sending the third query instruction to the SOC, if the second core junction temperature exceeds a set time (for example, 5S), the abnormal temperature acquisition fault is reported to the client application layer. If the micro control unit 110 cannot obtain the second core junction temperature through the ethernet due to the ethernet communication failure or the failure of the chip core junction temperature monitoring node 140, the micro control unit 110 sends a request for the maximum water cooling signal to the whole vehicle through the CAN specific frame message.
Optionally, the micro control unit 110 is specifically configured to:
reading a temperature upper limit value and a temperature lower limit value corresponding to a preset first kernel junction temperature in a thermal state register, and sending the temperature upper limit value and the temperature lower limit value to a power management chip; if the first core junction temperature is greater than the upper temperature limit value or less than the lower temperature limit value, reporting abnormal core junction temperature information of the micro control unit to the power management chip.
In this embodiment, the micro control unit 110 may obtain the temperature upper limit value and the temperature lower limit value corresponding to the preset first core junction temperature (MCU core junction temperature) by reading the thermal status register of the micro control unit core junction temperature monitoring node 111, and send the temperature upper limit value and the temperature lower limit value to the power management chip PMIC synchronously. When the first core junction temperature is greater than the upper temperature limit value or less than the lower temperature limit value, triggering an alarm alert, and reporting the core junction temperature abnormality information of the micro control unit to the PMIC by the micro control unit 110, and stopping feeding dogs to the watch dog of the PMIC. Further, the PMIC may control the ADAS ECU domain controller to restart through a Reset signal.
Preferably, the upper temperature limit value and the lower temperature limit value in the thermal state register can be combined with the temperature environment condition of the whole vehicle selling area to customize a proper lower junction temperature limit value and an upper junction temperature limit value of the MCU core.
Further, after the micro control unit 110 obtains the first core junction temperature, it may determine whether the first core junction temperature is greater than 95 ℃, if yes, report to the client application layer software.
Fig. 2 is a schematic diagram of internal connection of a temperature monitoring system of a domain controller according to an embodiment of the present invention, where a micro control unit core junction temperature monitoring node 111 and a Security Management Unit (SMU) are built in a micro control unit 110, and an interrupt pin (SHDN) of a first board side temperature monitoring node 120 and a second board side temperature monitoring node 130 can be monitored and can be communicated with them through a serial bus. The micro control unit 110 may also communicate with a System On Chip (SOC) via ethernet to obtain the core junction temperature of the SOC collected by the core junction temperature monitoring node 140. When a temperature abnormality fault occurs, the SMU may report the power management chip PMIC through a fault pin (error pin), and when the fault is recovered, the power management chip PMIC may control the ADAS ECU domain controller to restart through a reset signal (reset).
Fig. 3 is a schematic diagram of a temperature monitoring process of a domain controller according to an embodiment of the present invention, where the ECU is powered on, and after the micro control unit 110 is started, the first board end temperature, the second board end temperature, the first core junction temperature, and the second core junction temperature are monitored simultaneously. For the first board end temperature and the second board end temperature, the micro control unit 110 sets a corresponding temperature threshold, monitors interrupt pins of all monitoring nodes in a polling mode, and if the interrupt pin point is monitored to be pulled down, sends a query instruction to the corresponding monitoring nodes to acquire the board end temperature, and if the temperature is abnormal, reports error pin to the PMIC. For the first core junction temperature, the micro control unit 110 reads a preset upper limit value and a preset lower limit value of the temperature from the thermal state register, sends the upper limit value and the lower limit value of the temperature to the PMIC, judges the actual first core junction temperature according to the upper limit value and the lower limit value, and reports abnormal information to the PMIC if the temperature exceeds the upper limit value or is lower than the lower limit value, so that the PMIC control domain controller is restarted. If the first core junction temperature is within the preset temperature upper limit value and lower limit value, the micro control unit 110 may handshake with the SOC and send a query instruction to the SOC to obtain the second core junction temperature. If the junction temperature of the second core accords with the corresponding temperature interval, in order to eliminate temperature jitter, judging whether the difference between the junction temperature of the second core obtained currently and the junction temperature of the second core obtained last time is larger than a set value, if so, reporting abnormal information to the PMIC when the junction temperature of the second core is larger than an early warning threshold value, and enabling the PMIC to control the SOC to be powered down. If the junction temperature of the second kernel does not accord with the corresponding temperature interval, reporting temperature acquisition failure information to the client application layer when the Error Counter is greater than a set value, and restarting counting.
According to the temperature monitoring system of the domain controller disclosed by the embodiment of the invention, the micro-control unit is used for monitoring the junction temperature of the core of the micro-control unit, the junction temperature of the core of the system-level chip, the board end temperature of the micro-control unit and the board end temperature of the system-level chip, so that the micro-control unit executes the domain controller temperature judgment logic, a high-reliability temperature monitoring method of the domain controller system level is formed, and the system is more suitable for an ADAS driving auxiliary system with high calculation power.
Example two
Fig. 4 is a flowchart of a temperature monitoring method of a domain controller according to a second embodiment of the present invention, where the method may be performed by a temperature monitoring system of the domain controller, the system includes a micro control unit, a first board end temperature monitoring node, a second board end temperature monitoring node, and a chip core junction temperature monitoring node, where the micro control unit includes a micro control unit core junction temperature monitoring node, the temperature monitoring system of the domain controller may be implemented in a hardware and/or software form, and the temperature monitoring system of the domain controller may be configured in an electronic device. As shown in fig. 4, the method includes:
s210, acquiring the first board end temperature of the first printed circuit board corresponding to the micro control unit through the first board end temperature monitoring node, and responding to a first query instruction sent by the micro control unit and sending the first board end temperature to the micro control unit.
S220, acquiring the second board end temperature of the second printed circuit board corresponding to the system-in-chip through the second board end temperature monitoring node, and responding to a second query instruction sent by the micro control unit and sending the second board end temperature to the micro control unit.
S230, collecting the second core junction temperature of the system-in-chip through a core junction temperature monitoring node of the chip, and responding to a third query instruction sent by the micro control unit and sending the second core junction temperature to the micro control unit.
S240, respectively sending a first query instruction, a second query instruction and a third query instruction to the first board end temperature monitoring node, the second board end temperature monitoring node and the chip core junction temperature monitoring node through the micro control unit, respectively judging rationality according to the received first board end temperature, the second core junction temperature and the first core junction temperature of the micro control unit acquired by the micro control unit core junction temperature monitoring node, and executing corresponding response actions according to the judging result.
Further, the manner of sending the first query instruction and the second query instruction to the first board end temperature monitoring node and the second board end temperature monitoring node respectively through the micro control unit may be:
The method comprises the steps of respectively monitoring interrupt pins of a first board end temperature monitoring node and a second board end temperature monitoring node through a micro control unit; when the potential of an interrupt pin of the first board end temperature monitoring node is reduced, a first query instruction is sent to the first board end temperature monitoring node through a serial bus; and when the potential of the interrupt pin of the second board-end temperature monitoring node is reduced, sending a second query instruction to the second board-end temperature monitoring node through the serial bus.
Further, the manner of performing the rationality judgment by the micro-control unit according to the received first board end temperature and the second board end temperature, and performing the corresponding response action according to the judgment result may be:
setting temperature thresholds corresponding to the first plate end temperature and the second plate end temperature respectively; and when the temperature of the first board end and/or the temperature of the second board end do not accord with the corresponding temperature threshold value, reporting a fault pin to the power management chip.
Further, after reporting the fault pin to the power management chip, the method further includes:
when the potential of the interrupt pin of the first board end temperature monitoring node is normal, a fourth query instruction is sent to the first board end temperature monitoring node through a serial bus; when the potential of the interrupt pin of the second board end temperature monitoring node is normal, a fifth query instruction is sent to the second board end temperature monitoring node through the serial bus; if the temperature of the first board end and the temperature of the second board end meet the corresponding temperature threshold values, fault recovery information is reported to the power management chip;
Correspondingly, the method further comprises the steps of: responding to a fourth query instruction through the first board end temperature monitoring node, and sending the first board end temperature to the micro control unit; and responding to a fifth query instruction through the second board end temperature monitoring node, and sending the second board end temperature to the micro control unit.
Further, the micro control unit communicates with the junction temperature monitoring node of the chip core through the Ethernet.
Further, the manner of performing the rationality judgment by the micro-control unit according to the received junction temperature of the second core and performing the corresponding response action according to the judgment result may be:
receiving the second core junction temperature, and if the second core junction temperature does not accord with a preset temperature interval, adding one to the value of the counting zone bit; if the value of the counting zone bit is larger than the first set value, reporting temperature acquisition failure information to a client application layer, and zeroing the counting zone bit; if the value of the counting zone bit is smaller than or equal to the first set value and the junction temperature of the second core is larger than the early warning threshold value, reporting abnormal information of the junction temperature of the core to the power management chip.
Further, the method further comprises:
if the junction temperature of the second core accords with the preset temperature interval and the difference between the junction temperature of the second core and the junction temperature of the second core received last time is larger than a second set value, the value of the counting zone bit is increased by one; if the second core junction temperature accords with the preset temperature interval and the difference between the second core junction temperature and the last received second core junction temperature is smaller than or equal to a second set value, reporting the abnormal information of the core junction temperature to the power management chip when the second core junction temperature is larger than the early warning threshold value.
Further, the manner of performing the rationality judgment by the micro control unit according to the received first core junction temperature of the micro control unit collected by the core junction temperature monitoring node of the micro control unit and performing the corresponding response action according to the judgment result may be:
reading a temperature upper limit value and a temperature lower limit value corresponding to a preset first kernel junction temperature in a thermal state register, and sending the temperature upper limit value and the temperature lower limit value to a power management chip; if the first core junction temperature is greater than the upper temperature limit value or less than the lower temperature limit value, reporting abnormal core junction temperature information of the micro control unit to the power management chip.
The temperature monitoring method of the domain controller disclosed by the embodiment of the invention can be executed by the temperature monitoring system of the domain controller provided by any embodiment, and has the corresponding functional modules and beneficial effects of the executing system.
Example III
Fig. 5 shows a schematic diagram of the structure of an electronic device 10 that may be used to implement an embodiment of the invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Electronic equipment may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.
As shown in fig. 5, the electronic device 10 includes at least one processor 11, and a memory, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, etc., communicatively connected to the at least one processor 11, in which the memory stores a computer program executable by the at least one processor, and the processor 11 may perform various appropriate actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from the storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 may also be stored. The processor 11, the ROM 12 and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.
Various components in the electronic device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, etc.; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.
The processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as the temperature monitoring method of the domain controller.
In some embodiments, the temperature monitoring method of the domain controller may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 10 via the ROM 12 and/or the communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more of the steps of temperature monitoring of the domain controller described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the temperature monitoring method of the domain controller in any other suitable way (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.
The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (11)
1. A temperature monitoring system for a domain controller, comprising: the device comprises a micro control unit, a first board end temperature monitoring node, a second board end temperature monitoring node and a chip core junction temperature monitoring node, wherein the micro control unit comprises the micro control unit core junction temperature monitoring node;
the first board end temperature monitoring node is used for acquiring the first board end temperature of a first printed circuit board corresponding to the micro control unit and responding to a first query instruction sent by the micro control unit, and sending the first board end temperature to the micro control unit;
The second board end temperature monitoring node is used for acquiring the second board end temperature of a second printed circuit board corresponding to the system-level chip and responding to a second query instruction sent by the micro control unit, and sending the second board end temperature to the micro control unit;
the chip core junction temperature monitoring node is used for collecting a second core junction temperature of the system-level chip and responding to a third query instruction sent by the micro control unit to send the second core junction temperature to the micro control unit;
the micro control unit is used for respectively sending the first query instruction, the second query instruction and the third query instruction to the first board end temperature monitoring node, the second board end temperature monitoring node and the chip core junction temperature monitoring node, respectively judging rationality according to the received first board end temperature, the second core junction temperature and the first core junction temperature of the micro control unit acquired by the micro control unit core junction temperature monitoring node, and executing corresponding response actions according to judgment results.
2. The system according to claim 1, wherein the micro-control unit is specifically configured to:
Monitoring interrupt pins of the first board end temperature monitoring node and the second board end temperature monitoring node;
when the potential of the interrupt pin of the first board-end temperature monitoring node is reduced, sending the first query instruction to the first board-end temperature monitoring node through a serial bus;
and when the potential of the interrupt pin of the second board-end temperature monitoring node is reduced, sending the second query instruction to the second board-end temperature monitoring node through a serial bus.
3. The system according to claim 2, characterized in that said micro-control unit is specifically adapted to:
setting temperature thresholds corresponding to the first plate end temperature and the second plate end temperature respectively;
and when the temperature of the first board end and/or the temperature of the second board end does not accord with the corresponding temperature threshold value, reporting a fault pin to the power management chip.
4. The system of claim 3, wherein after reporting the fault pin to the power management chip, the micro-control unit is further configured to:
when the potential of the interrupt pin of the first board end temperature monitoring node is normal, a fourth query instruction is sent to the first board end temperature monitoring node through a serial bus;
When the potential of the interrupt pin of the second board end temperature monitoring node is normal, a fifth query instruction is sent to the second board end temperature monitoring node through a serial bus;
if the temperature of the first board end and the temperature of the second board end meet the corresponding temperature threshold values, fault recovery information is reported to the power management chip;
correspondingly, the first board end temperature monitoring node is further used for responding to the fourth query instruction and sending the first board end temperature to the micro control unit; the second board end temperature monitoring node is further configured to respond to the fifth query instruction, and send the second board end temperature to the micro control unit.
5. The system of claim 1, wherein the micro-control unit communicates with the core junction temperature monitoring node via ethernet.
6. The system according to claim 1, wherein the micro-control unit is specifically configured to:
receiving the second core junction temperature, and if the second core junction temperature does not accord with a preset temperature interval, adding one to the value of the counting zone bit;
if the value of the counting zone bit is larger than a first set value, reporting temperature acquisition failure information to a client application layer, and zeroing the counting zone bit; and if the value of the counting zone bit is smaller than or equal to the first set value and the junction temperature of the second core is larger than the early warning threshold value, reporting the abnormal information of the junction temperature of the core to a power management chip.
7. The system of claim 6, wherein the micro-control unit is further configured to:
if the second core junction temperature accords with the preset temperature interval and the difference between the second core junction temperature and the last received second core junction temperature is larger than a second set value, adding one to the value of the counting zone bit;
if the second core junction temperature accords with a preset temperature interval and the difference between the second core junction temperature and the last received second core junction temperature is smaller than or equal to the second set value, reporting chip core junction temperature abnormality information to the power management chip when the second core junction temperature is larger than the early warning threshold value.
8. The system according to claim 1, wherein the micro-control unit is specifically configured to:
reading a temperature upper limit value and a temperature lower limit value corresponding to the first kernel junction temperature preset in a thermal state register, and sending the temperature upper limit value and the temperature lower limit value to a power management chip;
if the first core junction temperature is greater than the upper temperature limit value or less than the lower temperature limit value, reporting abnormal core junction temperature information of the micro control unit to the power management chip.
9. The method is used for a temperature monitoring system of a domain controller, and the system comprises a micro control unit, a first board end temperature monitoring node, a second board end temperature monitoring node and a chip core junction temperature monitoring node, wherein the micro control unit comprises the micro control unit core junction temperature monitoring node, and the method comprises the following steps:
collecting the first board end temperature of a first printed circuit board corresponding to the micro control unit through the first board end temperature monitoring node, and responding to a first query instruction sent by the micro control unit to send the first board end temperature to the micro control unit;
acquiring the temperature of a second board end of a second printed circuit board corresponding to a system-level chip through the temperature monitoring node of the second board end, and responding to a second query instruction sent by the micro control unit to send the temperature of the second board end to the micro control unit;
collecting a second core junction temperature of the system-level chip through the core junction temperature monitoring node of the chip, and responding to a third query instruction sent by the micro control unit, and sending the second core junction temperature to the micro control unit;
And sending the first query instruction, the second query instruction and the third query instruction to the first board end temperature monitoring node, the second board end temperature monitoring node and the chip core junction temperature monitoring node through the micro control unit respectively, carrying out rationality judgment according to the received first board end temperature, the second core junction temperature and the first core junction temperature of the micro control unit acquired by the micro control unit core junction temperature monitoring node, and executing corresponding response actions according to judgment results.
10. An electronic device, the electronic device comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,,
the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the method of temperature monitoring of a domain controller according to claim 9.
11. A computer readable storage medium storing computer instructions for causing a processor to execute the method of temperature monitoring of a domain controller according to claim 9.
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