CN116598313B - Three-dimensional integrated circuit - Google Patents

Abstract

The embodiment of the application provides a three-dimensional integrated circuit, which comprises: a bottom device layer; the bottom device layer comprises a bottom substrate, a bottom functional device layer and a bottom insulating layer which are arranged from bottom to top; wherein, the bottom insulating layer is provided with an electric connection structure connected with a functional device of the bottom functional device layer; an upper first device layer formed above the bottom device layer, the upper first device layer comprising a first semiconductor layer, a first functional device layer, a first insulating layer disposed from bottom to top; wherein the first insulating layer is provided with an electric connection structure connected with the functional devices of the first functional device layer; the first interlayer through hole and the conductive substance filled in the first interlayer through hole are used for connecting the electric connection structure of the bottom insulating layer and the electric connection structure of the first insulating layer. The embodiment of the application solves the technical problem that the traditional 3D packaging chip cannot adapt to the development direction of the chip.

Description

A three-dimensional integrated circuit

Technical Field

The present application relates to the technical field of semiconductor devices, and in particular, to a three-dimensional integrated circuit.

Background technique

Electronic products are currently developing towards miniaturization, high density, high reliability and low power consumption, which makes the development direction of chips also towards miniaturization, high density, high reliability and low power consumption. In order to reduce the chip size, the industry has invented multi-layer chip stacking packaging technology.

Initially, stacked packaging involves stacking multiple bare chips together, connecting the signals between the chips through bonding technology to form a complete internal system, and then connecting the external signals through the package pins, and finally packaging them into a complete chip.

Later, the industry invented the through silicon via (TSV) technology, and the signals between the stacked chip dies were connected through TSV, forming a more compact multi-chip stacked package chip. This 3D packaged chip is formed by stacking multiple layers of chip dies in the packaging stage. From the perspective of chip manufacturing, this 3D packaged chip can only be regarded as a pseudo 3D chip.

3D packaged chips have the following defects:

1. The main challenge facing thinning technology is the thinning capability of <50um required by the ultra-thinning process. Unsupported thinned silicon wafers will experience severe warping after assembly, and large residual stress will be generated on the interconnection (micro-bumps) between the substrate, leading to reliability problems in the device structure.

2. Because Cu is easily oxidized and easily forms various oxides (CuO and Cu2O) at high temperatures, a Cu-Cu mixed bonding process with high vacuum and high cleanliness is required.

3. The alignment accuracy of different chip bare crystals during the packaging process is low. During the packaging process, the bare crystal may be displaced, resulting in misalignment of drilling or pin positions. The wiring and interconnection spacing is limited to a few microns due to the coverage accuracy. The pitch of Intel's most advanced QMC process is 3um, so the number of bonded I/Os is limited by the pitch and the integration cannot be improved.

4. 3D packaging is composed of a large number of different materials with different material properties, such as coefficient of thermal expansion (CTE), thermal conductivity, electrical conductivity and elastic modulus, which will generate huge thermal-mechanical forces on the chip and cause chip-package interaction (CPI), resulting in cracking of low-K dielectric materials and shedding of metal structures. In addition, the package itself may also be severely warped, adding additional stress, especially for packages with larger areas.

Therefore, traditional 3D packaged chips cannot adapt to the development direction of chips, and real 3D chips are urgently needed. This is a technical problem that technical personnel in this field urgently need to solve.

The above information disclosed in the background section is only for enhancing understanding of the background of the present application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art.

Summary of the invention

The embodiment of the present application provides a three-dimensional integrated circuit to solve the technical problem that traditional 3D packaged chips cannot adapt to the development direction of chips.

The embodiment of the present application provides a three-dimensional integrated circuit, including:

A bottom device layer; the bottom device layer comprises a bottom substrate, a bottom functional device layer, and a bottom insulating layer arranged from bottom to top; wherein the bottom insulating layer has an electrical connection structure connected to the functional device of the bottom functional device layer;

An upper first device layer is formed above the bottom device layer, the upper first device layer comprising a first semiconductor layer, a first functional device layer, and a first insulating layer arranged from bottom to top; wherein the first insulating layer has an electrical connection structure connected to the functional device of the first functional device layer;

The first interlayer through hole and the conductive material filled therein connect the electrical connection structure of the bottom insulating layer and the electrical connection structure of the first insulating layer.

The embodiment of the present application adopts the above technical solution, which has the following technical effects:

The three-dimensional integrated circuit of the embodiment of the present application is essentially a chip, and has only one substrate, which is the bottom substrate. The thickness of the first semiconductor layer is not only less than the thickness of the bottom substrate, but also much less than the thickness of the bottom substrate. The bottom device layer is only a layer structure in a three-dimensional integrated circuit, and the upper first device layer is a layer structure above the bottom device layer, that is, the bottom device layer and the upper first device layer are arranged vertically during manufacturing. The first interlayer through hole and the conductive material therein realize the electrical connection between the electrical connection structure of the lower insulating layer and the electrical connection structure of the first insulating layer, and realize the connection between the functional device of the bottom functional device layer and the functional device of the first functional device layer. That is, the electrical connection of the three-dimensional integrated circuit in the vertical direction is realized. The three-dimensional integrated circuit of the embodiment of the present application is not a 3D packaged chip, but a real 3D chip, that is, a three-dimensional integrated circuit. The entire three-dimensional integrated circuit has only one bottom substrate, so that the vertical height of the entire three-dimensional integrated circuit can be smaller, and thus the size of the entire three-dimensional integrated circuit is smaller; at the same time, it also makes the substrate cost of the three-dimensional integrated circuit lower.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

FIG1 is a schematic diagram of a three-dimensional integrated circuit according to an embodiment of the present application;

FIG2 is a flow chart of a method for preparing the three-dimensional integrated circuit shown in FIG1 ;

FIG3 is a cross-sectional view of the method for preparing the three-dimensional integrated circuit shown in FIG1 after completing step S1-2;

FIG4 is a cross-sectional view of the method for preparing the three-dimensional integrated circuit shown in FIG1 after completing step S1-3;

FIG5 is a cross-sectional view of the method for preparing the three-dimensional integrated circuit shown in FIG1 after completing step S1-4;

FIG6 is a cross-sectional view of the method for manufacturing the three-dimensional integrated circuit shown in FIG1 after completing step S2-1;

FIG7 is a cross-sectional view of the method for manufacturing the three-dimensional integrated circuit shown in FIG1 after completing step S2-3;

FIG8 is a cross-sectional view of the method for manufacturing the three-dimensional integrated circuit shown in FIG1 after completing step S3-2;

FIG9 is a cross-sectional view of the method for manufacturing the three-dimensional integrated circuit shown in FIG1 after completing step S3-6;

FIG10 is a cross-sectional view of the method for manufacturing the three-dimensional integrated circuit shown in FIG1 after completing step S3-7;

FIG11 is a cross-sectional view of the method for manufacturing the three-dimensional integrated circuit shown in FIG1 after completing step S4;

FIG. 12 is a schematic diagram of a three-dimensional integrated circuit with an annealing barrier layer according to an embodiment of the present application.

Reference numerals:

Bottom substrate epitaxial layer 1, functional device of bottom functional device layer 2, oxide insulating layer 3, tungsten through hole 4, metal interconnection line 5 in oxide insulating layer, low dielectric constant insulating layer 6, metal interconnection line 7 in low dielectric constant insulating layer, silicon dioxide island isolation layer 8, first thin silicon layer 9, device isolation 10, functional device of first functional device layer 11, first interlayer TSV through hole 12, aluminum pad layer 13, passivation layer 14, H+ ion implantation layer 15, annealing barrier layer 16.

Detailed ways

In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

Traditional 3D packaged chips are essentially multi-layer chip packages, that is, each chip is independent before packaging, and there is always a certain gap between the two layers of chips. In this way, 3D packaging itself cannot achieve close fit between the two layers of chips and cannot adapt to the development direction of chip miniaturization. In each individual chip, there is a substrate, and the substrate needs to maintain a certain thickness, resulting in a certain thickness for each chip; in addition, the substrate accounts for 40% to 50% of the chip, which also makes the cost of 3D packaged chips high.

The inventor of this application did not consider how to achieve chip miniaturization based on the traditional 3D packaged chip, but opened up another new development direction, creating a real 3D chip to adapt to the development direction of chip miniaturization, high density, high reliability and low power consumption.

Embodiment 1

As shown in FIG1 , a three-dimensional integrated circuit according to an embodiment of the present application includes:

A bottom device layer; the bottom device layer comprises a bottom substrate, a bottom functional device layer, and a bottom insulating layer arranged from bottom to top; wherein the bottom insulating layer has an electrical connection structure connected to the functional device of the bottom functional device layer;

An upper first device layer is formed on the island isolation layer, the upper first device layer comprising a first semiconductor layer, a first functional device layer, and a first insulating layer arranged from bottom to top; wherein the first insulating layer has an electrical connection structure connected to a functional device of the first functional device layer;

The first interlayer through hole and the conductive material filled therein connect the electrical connection structure of the bottom insulating layer and the electrical connection structure of the first insulating layer.

The three-dimensional integrated circuit of the embodiment of the present application is essentially a chip, and only one substrate is the bottom substrate. The thickness of the first semiconductor layer is not only less than the thickness of the bottom substrate, but also much less than the thickness of the bottom substrate. The bottom device layer is only a layer structure in a three-dimensional integrated circuit, and the upper first device layer is a layer structure above the bottom device layer, that is, the bottom device layer and the upper first device layer are arranged vertically during manufacturing. The first interlayer through hole and the conductive material therein realize the electrical connection between the electrical connection structure of the lower insulating layer and the electrical connection structure of the first insulating layer, and realize the connection between the functional device of the bottom functional device layer and the functional device of the first functional device layer. That is, the path of the electrical connection of the three-dimensional integrated circuit in the vertical direction is shorter, so it is an important link to realize the electrical connection of the bottom device layer and the upper first device layer in the vertical direction. The three-dimensional integrated circuit of the embodiment of the present application is not a 3D packaged chip, but a real 3D chip, that is, a three-dimensional integrated circuit. The entire three-dimensional integrated circuit has only one bottom substrate, so that the vertical height of the entire three-dimensional integrated circuit can be smaller, and the first interlayer through hole and the conductive material filled therein connect the bottom device layer and the upper first device layer, so that the vertical size of the entire three-dimensional integrated circuit is smaller; at the same time, the substrate cost of the three-dimensional integrated circuit is low, which also reduces the cost of the entire three-dimensional integrated circuit.

In implementation, the three-dimensional integrated circuit is characterized by further comprising:

An island isolation layer is formed on the bottom insulating layer and between the upper first device layer.

That is, the bottom device layer and the first device layer above are arranged vertically during manufacturing, and the two are bonded through the island isolation layer. The connection method of the island isolation layer bonding, on the one hand, conveniently realizes the connection between the bottom device layer and the first device layer above, and on the other hand, effectively isolates the bottom device layer and the first device layer above, avoiding leakage and heat transfer from the first device layer above to the bottom device layer. Therefore, the island isolation layer is an important link in realizing the vertical integration of the bottom device layer and the first device layer above.

In implementation, the three-dimensional integrated circuit further includes an upper second device layer, ..., an upper nth device layer arranged in sequence from above the upper first device layer; wherein the value range of n is greater than or equal to 2 and less than or equal to 50; correspondingly:

There is an island isolation layer between adjacent layers of the upper first device layer, the upper second device layer, ..., and the upper nth device layer;

The upper first device layer, the upper second device layer, ..., the upper nth device layer are connected to each other through the second interlayer via hole and the conductive material therein, ..., the nth interlayer via hole and the conductive material therein.

Specifically, the island isolation layer is a silicon dioxide island isolation layer, and the first interlayer through hole and the conductive material filled therein are the first interlayer TSV through hole.

The present application adopts a multi-layer cyclic structure of a bottom device layer, a silicon dioxide island isolation layer, a first device layer above, a silicon dioxide island isolation layer, a second device layer above, a silicon dioxide island isolation layer, ..., and an nth device layer above. Compared with the 3D packaged chips of the prior art, on the one hand, the three-dimensional integrated circuit of the present application efficiently utilizes the vertical space, so that the integration density of the prepared three-dimensional integrated circuit is higher; on the other hand, the three-dimensional integrated circuit of the present application avoids the ultra-thinning process, so that the stress warping of the three-dimensional integrated circuit is smaller.

The structure of the bottom device layer is described in detail below.

In implementation, as shown in FIG1 , the bottom device layer further includes:

The bottom substrate epitaxial layer 1 is formed on the bottom substrate (not shown in the figure), and the functional device 2 of the bottom functional device layer is located on the bottom substrate epitaxial layer 1 .

In implementation, as shown in FIG1 , the bottom insulating layer includes an oxide insulating layer 3 and a low dielectric constant insulating layer 6 arranged from bottom to top;

As shown in FIG1 , the electrical connection structure of the bottom insulating layer includes:

A tungsten through hole 4 disposed in the oxide insulating layer 3 and located above the functional device of the first functional device layer;

A metal interconnection line 5 is provided in the oxide insulating layer 3 and connected to the tungsten through hole;

A metal interconnection line 7 is provided in the low dielectric constant insulating layer 6, and the metal interconnection line 7 in the low dielectric constant insulating layer 6 is connected to the metal interconnection line 5 in the oxide insulating layer 3;

The metal interconnection lines in the low dielectric constant insulating layer of the bottom insulating layer are completely wrapped by the low dielectric constant insulating layer in the lateral direction, and the metal interconnection lines in the oxide insulating layer of the bottom insulating layer are completely wrapped by the oxide insulating layer in the lateral direction.

Specifically, by controlling the exposure area of the three-dimensional integrated circuit to be located within the side edge of the three-dimensional integrated circuit, the metal interconnect line 7 in the low dielectric constant insulating layer close to the side edge of the three-dimensional integrated circuit is completely wrapped by the low dielectric constant insulating layer 6, and the metal interconnect line 5 in the oxide insulating layer of the bottom insulating layer is completely wrapped by the oxide insulating layer 3 in the lateral direction.

The beneficial effect of the metal interconnection line 7 in the low dielectric constant insulating layer near the side edge of the three-dimensional integrated circuit being completely wrapped by the low dielectric constant insulating layer 6 is to prevent the metal ions of the metal interconnection line 7 in the low dielectric constant insulating layer of the bottom device layer near the side edge of the three-dimensional integrated circuit from being exposed from the side edge of the three-dimensional integrated circuit, causing contamination when forming the structure above the bottom functional device layer. Specifically, when the three-dimensional integrated circuit is a cylinder, its side edge is the side of the cylinder. The position of the exposure area within the side of the cylinder is controlled so that the outer edge of the pattern of the three-dimensional integrated circuit and the side of the cylinder maintain a preset distance, so that the metal interconnection line 7 in the low dielectric constant insulating layer of the bottom device layer is wrapped by the low dielectric constant insulating layer. Similarly, the metal interconnection line 5 in the oxide insulating layer of the bottom device layer is completely wrapped by the oxide insulating layer 3 in the lateral direction.

It should be noted that in the bottom functional device layer, multiple layers of low dielectric constant insulating layers 6 and metal interconnects 7 in the low dielectric constant insulating layers may be required. According to actual needs, as many layers as needed, the low dielectric constant insulating layers 6 and metal interconnects 7 in the low dielectric constant insulating layers can be prepared. For example, in the bottom functional device layer, seven or more layers of low dielectric constant insulating layers 6 and metal interconnects 7 in the low dielectric constant insulating layers are provided.

The structure of the upper first device layer is described in detail below.

In implementation, as shown in FIG1 , the first semiconductor layer has a device isolation 10 penetrating the first semiconductor layer, and the device isolation 10 surrounds the outside of the functional device 11 of the first functional device layer;

The device isolation is formed by STI, or the device isolation is formed by oxygen implantation.

The steps for shallow trench isolation (STI) formation are as follows:

A shallow trench is formed from the upper surface of the first semiconductor layer downwardly through the first semiconductor layer, and oxide is deposited in the shallow trench to form a shallow trench isolation (STI). That is, the shallow trench isolation extends downward to the upper surface of the silicon dioxide island isolation layer 8; the process of forming the shallow trench isolation itself does not require high temperature annealing, and high temperature annealing is not required after the shallow trench isolation process.

Specifically, shallow trench isolation, or STI for short, is usually used in processes below 0.25um. A trench is formed by depositing, patterning, and etching silicon using a silicon nitride mask, and then filling the trench with deposited oxide for isolation from silicon.

In the absence of a silicon dioxide island isolation layer 8, etching during the process of forming shallow trench isolation will cause ion damage to the lattice of the first semiconductor layer, and then the source and drain of the functional device 11 of the first functional device layer of the integrated circuit finally formed will have ion damage, causing the source and drain of the upper first device layer to leak through the silicon layer to the bottom device layer. In order to solve the leakage problem, the general solution is to perform high temperature annealing after forming shallow trench isolation to repair the ion damage. This solution is not adopted in this application.

Oxygen implantation destroys the silicon lattice and cannot be repaired, so the oxygen atoms cannot provide carriers and cannot conduct electricity, thus forming an isolation effect between devices.

Similarly, when device isolation is formed by oxygen injection, without setting the silicon dioxide island isolation layer 8, etching during the process of forming device isolation will cause ion damage to the lattice of the first semiconductor layer, and then the source and drain of the functional device 11 of the first functional device layer of the integrated circuit finally formed will have ion damage, causing the source and drain of the upper first device layer to leak through the silicon layer to the bottom device layer. In order to solve the leakage problem, the general solution is to perform high-temperature annealing after forming the device isolation to repair the ion damage. This application does not adopt this solution.

The present application sets a silicon dioxide island isolation layer 8. Since the silicon dioxide island isolation layer 8 is set between the first thin silicon layer 9 and the bottom device layer, the source and drain of the functional device 11 of the first functional device layer of the integrated circuit finally formed are formed in the first thin silicon layer 9. The silicon dioxide island isolation layer 8 between the source and drain of the functional device 11 of the first functional device layer and the bottom device layer cuts off the leakage path and does not generate leakage. In this way, it is achieved that after the shallow trench isolation is formed, high temperature annealing is no longer required. Moreover, the use of high temperature annealing will damage the functional devices of the bottom functional device layer. High temperature annealing is no longer required here, which avoids damage to the functional devices of the bottom functional device layer when preparing the upper first device layer, and is a very important link in the preparation method of three-dimensional integrated circuits.

The present application adopts a wafer bonding method to form a silicon dioxide island isolation layer 8, thereby avoiding leakage between the upper first device layer and the bottom device layer of the three-dimensional integrated circuit, and realizing the vertical arrangement of the bottom device layer and the upper first device layer, so that the metal interconnection path between the bottom device layer and the upper first device layer is shorter, and the corresponding signal transmission path is shorter, so that the metal interconnection delay and power consumption can be better managed and controlled, which helps to improve the overall performance and speed of the three-dimensional integrated circuit.

During implementation, the functional devices of the first functional device layer use a low thermal budget flash millisecond annealing process in the annealing process after ion implantation and the stress relief annealing process in the process of forming the functional devices 11 of the first functional device layer. The annealing temperature range of the low thermal budget flash millisecond annealing process is greater than or equal to 750°C and less than or equal to 1200°C.

The bottom device layer and the first device layer above are isolated by a silicon dioxide island isolation layer 8. The heat from the low thermal budget flash millisecond annealing cannot be transferred to the metal interconnection line 7 in the low dielectric constant insulating layer of the bottom device layer, thus solving the problem of the heat from the manufacturing process of the first device layer above affecting the metal interconnection line 7 in the low dielectric constant insulating layer of the bottom device layer. This is a very important step in the preparation method of three-dimensional integrated circuits.

In practice, as shown in FIG. 1 , ohmic contacts are formed in the source and drain (ie, doped regions) of the functional device 11 of the first functional device layer at locations where vertical tungsten vias 4 need to be provided.

The steps for forming an ohmic contact are as follows:

Ge ion implantation is performed on the K nano-surface at the location where the vertical tungsten through hole 4 is required to be set in the source and drain (i.e., doping area) of the functional device 11 of the first functional device layer to achieve amorphization to form an amorphized area; wherein the value range of K is greater than or equal to 3 and less than or equal to 20;

A titanium (Ti) film and a titanium nitride (TiN) film are sequentially deposited from bottom to top in the amorphized region using ALD technology;

A titanium nitride (TiN) film is subjected to low temperature rapid annealing at an annealing temperature in the range of greater than or equal to 500° C. and less than or equal to 580° C. to form an ohmic contact with ultra-low contact resistivity.

That is, the preparation process for forming ohmic contact is a method of doping amorphous low-temperature and low-resistance contact.

In implementation, as shown in FIG1 , the first insulating layer includes an oxide insulating layer 3 and a low dielectric constant insulating layer 6 arranged from bottom to top;

The electrical connection structure of the first insulating layer comprises:

a tungsten via disposed above the ohmic contact location of the oxide insulating layer;

a metal interconnection line disposed in the oxide insulating layer and located above the tungsten through hole;

A metal interconnection line is disposed in the low dielectric constant insulating layer, and the metal interconnection line in the low dielectric constant insulating layer is connected to the metal interconnection line in the oxide insulating layer;

The metal interconnection lines in the low dielectric constant insulating layer of the first insulating layer are completely wrapped by the low dielectric constant insulating layer in the lateral direction, and the metal interconnection lines in the oxide insulating layer of the first insulating layer are completely wrapped by the oxide insulating layer in the lateral direction;

The first interlayer via connects the metal interconnection line of the low dielectric constant insulating layer in the bottom device layer and the metal interconnection line in the oxide insulating layer in the upper first device layer.

Specifically, by controlling the exposure area of the three-dimensional integrated circuit to be located within the side edge of the three-dimensional integrated circuit, the metal interconnect line 7 in the low dielectric constant insulating layer close to the side edge of the three-dimensional integrated circuit is completely wrapped by the low dielectric constant insulating layer 6 in the lateral direction, and the metal interconnect line 5 in the oxide insulating layer of the first insulating layer is completely wrapped by the oxide insulating layer 3 in the lateral direction.

The beneficial effect of the metal interconnection line 7 in the low dielectric constant insulating layer near the side edge of the three-dimensional integrated circuit being completely wrapped by the low dielectric constant insulating layer 6 is to prevent the metal ions of the metal interconnection line 7 in the low dielectric constant insulating layer of the bottom device layer near the side edge of the three-dimensional integrated circuit from being exposed from the side edge of the three-dimensional integrated circuit, causing contamination when forming the structure above the first functional device layer. Specifically, when the three-dimensional integrated circuit is a cylinder, its side edge is the side of the cylinder. The position of the exposure area within the side of the cylinder is controlled so that the outer edge of the pattern of the three-dimensional integrated circuit and the side of the cylinder maintain a preset distance, so that the metal interconnection line 7 in the low dielectric constant insulating layer of the first device layer above is wrapped by the low dielectric constant insulating layer. Similarly, the metal interconnection line 7 in the oxide insulating layer of the first device layer above is wrapped by the oxide insulating layer.

It should be noted that in the upper first device layer, multiple layers of low dielectric constant insulating layers 6 and metal interconnection lines 7 in the low dielectric constant insulating layers may be required. According to actual needs, as many layers as needed, the low dielectric constant insulating layers 6 and metal interconnection lines 7 in the low dielectric constant insulating layers can be prepared. For example, in the upper first device layer, seven or more layers of low dielectric constant insulating layers 6 and metal interconnection lines 7 in the low dielectric constant insulating layers are provided.

The integration density of the three-dimensional integrated circuit of the present application is higher, and the problem brought about is that the power consumption density and heat density are higher. The vertical connection vertical heat dissipation channel (composed of tungsten through hole 4, metal interconnection line 5 in oxide insulating layer, metal interconnection line 7 in low dielectric constant insulating layer, and first interlayer via 12) of the three-dimensional integrated circuit prepared by the preparation method of the three-dimensional integrated circuit of the present application adopts high temperature resistant material to improve the stability of the three-dimensional integrated circuit. The integration density of tungsten through hole 4, metal interconnection line 5 in oxide insulating layer, metal interconnection line 7 in low dielectric constant insulating layer, and first interlayer via 12 is higher, so the area of the bottom substrate, the first thin silicon layer, the second thin silicon layer, ..., the nth thin silicon layer is smaller, which reduces the cost of the three-dimensional integrated circuit, and at the same time, also reduces the parasitic capacitance.

In addition, the manufacturing method of the three-dimensional integrated circuit of the present application does not involve any packaging factory for processing the back redistribution layer and micro-bumps. Therefore, multi-layer manufacturing can be directly realized at the three-dimensional integrated circuit manufacturer, and stricter process control can be achieved. Once the technology matures, high-density interconnection can be achieved, which greatly improves the computing power of the three-dimensional integrated circuit and realizes high-speed storage and computing integration.

In addition, the manufacturing method of the three-dimensional integrated circuit of the present application does not involve any packaging factory for processing the back redistribution layer and micro-bumps. Therefore, multi-layer manufacturing can be directly realized at the three-dimensional integrated circuit manufacturer, and stricter process control can be achieved. Once the technology matures, high-density interconnection can be achieved, which greatly improves the computing power of the three-dimensional integrated circuit and realizes high-speed storage and computing integration.

As an optional method, the functional devices of the bottom functional device layer, the first functional device layer, the second functional device layer, ..., the functional devices of the nth functional device layer can each realize the same function, that is, the three-dimensional integrated circuit is homogeneously integrated.

As another optional method, the functional devices of the bottom functional device layer, the first functional device layer, the second functional device layer, ..., the functional devices of the nth functional device layer can also realize different functions respectively, forming a three-dimensional integrated circuit with diversified functions. That is, the three-dimensional integrated circuit is heterogeneous integrated. For example, the multiple processing units, storage units, sensors and other functional components of the diversified three-dimensional integrated circuit can be arranged in multiple layers, making the functions of the three-dimensional integrated circuit more diversified and flexible.

The first semiconductor layer has the following characteristics:

In the field of semiconductor technology, silicon is considered to be black or grayish black. The inventors of the present application discovered during the process of technology development that when the thickness of the thin silicon layer is less than or equal to 1 micron (1 micron = 1000 nanometers), the thin silicon layer is a transparent thin silicon layer through the process of actually forming silicon into a thin silicon layer.

As an optional manner, the first semiconductor layer is a first thin silicon layer;

The thickness of the first thin silicon layer ranges from greater than or equal to 2 nanometers to less than or equal to 220 nanometers.

As another optional manner, the first semiconductor layer includes a first thin silicon layer and a first thin silicon epitaxial layer arranged from bottom to top;

The thickness of the first thin silicon layer ranges from 2 nanometers to 220 nanometers.

The thickness of the first thin silicon epitaxial layer ranges from greater than or equal to 40 nanometers to less than or equal to 70 nanometers.

The thickness of the first thin silicon layer is much smaller than the thickness of the substrate, but the first thin silicon layer needs to play a role similar to that of the substrate in the first device layer above, so the thickness of the first thin silicon layer cannot be too thin. In the actual manufacturing process, the smaller the thickness of the first thin silicon layer, the more difficult it is to prepare. Therefore, the value range of the thickness of the first thin silicon layer is not a simple range found at random, but is determined by the inventor after considering various factors, paying a lot of creative labor and conducting a large number of simulation experiments and product tests.

Specifically, the thickness of the low dielectric constant insulating layer 6 ranges from greater than or equal to 100 nanometers to less than or equal to 200 nanometers.

Embodiment 2

A method for preparing a three-dimensional integrated circuit according to an embodiment of the present application is used to manufacture the three-dimensional integrated circuit of Embodiment 1, as shown in FIG. 1 and FIG. 2 , and includes the following steps:

Step S1: forming a bottom device layer, wherein the bottom device layer comprises a bottom substrate, a bottom functional device layer, and a bottom insulating layer arranged from bottom to top; wherein the bottom insulating layer has an electrical connection structure connected to the functional device of the bottom functional device layer;

Step S2: forming a silicon dioxide island isolation layer 8 and a first semiconductor layer of the first device layer above by a crystal bonding method, wherein the silicon dioxide island isolation layer 8 is located on the bottom insulating layer, and the first semiconductor layer is located on the silicon dioxide island isolation layer 8;

Step S3: Use a low thermal budget manufacturing process to prepare the structure of the upper first device layer except the first semiconductor layer, and form a first interlayer TSV through hole 12; wherein the upper first device layer includes the first semiconductor layer, the first functional device layer, and the first insulating layer arranged from bottom to top; the first insulating layer has an electrical connection structure connected to the functional device of the first functional device layer, and the first interlayer TSV through hole 12 connects the electrical connection structure of the bottom insulating layer and the electrical connection structure of the first insulating layer.

The method for preparing a three-dimensional integrated circuit of the embodiment of the present application essentially prepares a real 3D chip, and only one substrate is the bottom substrate. The thickness of the first semiconductor layer is not only less than the thickness of the bottom substrate, but also much less than the thickness of the bottom substrate. The bottom device layer is only a layer structure in a three-dimensional integrated circuit, and the upper first device layer is a layer structure above the bottom device layer, that is, the bottom device layer and the upper first device layer are arranged vertically during manufacturing, and the two are bonded by a silicon dioxide island isolation layer. The connection method of the silicon dioxide island isolation layer bonding, on the one hand, conveniently realizes the connection between the bottom device layer and the upper first device layer, on the other hand, also effectively isolates the bottom device layer and the upper first device layer, avoiding leakage from the upper first device layer to the bottom device layer. Therefore, the silicon dioxide island isolation layer is an important link in realizing the integration of the bottom device layer and the upper first device layer in the vertical direction. The first interlayer TSV through hole electrically connects the electrical connection structure of the lower insulating layer and the electrical connection structure of the first insulating layer, realizing the connection of the functional device of the bottom functional device layer and the functional device of the first functional device layer. That is, the electrical connection of the three-dimensional integrated circuit in the vertical direction is realized. The method for preparing a three-dimensional integrated circuit in the embodiment of the present application is not to form a 3D packaged chip, but to prepare a real 3D chip, that is, a three-dimensional integrated circuit. The entire three-dimensional integrated circuit has only one bottom substrate, so that the vertical height of the entire three-dimensional integrated circuit can be small, and thus the size of the entire three-dimensional integrated circuit is small; at the same time, the substrate cost of the three-dimensional integrated circuit is also low.

The step S1 of forming the bottom device layer is described in detail below.

Step S1 specifically includes the following steps:

Step S1-1: forming a bottom substrate epitaxial layer 1 on a bottom substrate (not shown in the figure);

As shown in FIG. 3 , step S1 - 2 : forming a functional device 2 of a bottom functional device layer on the substrate epitaxial layer 1 ;

As shown in FIG. 4 , step S1-3: forming an oxide insulating layer 3 and an electrical connection structure in the oxide insulating layer (i.e., a tungsten via 4 in the oxide insulating layer and a metal interconnection line 5 in the oxide insulating layer) on the functional device 2 of the bottom functional device layer;

As shown in Figure 5, step S1-4: a low dielectric constant insulating layer 6 and an electrical connection structure in the low dielectric constant insulating layer (i.e., a metal interconnection line 7 in the low dielectric constant insulating layer) are formed on the oxide insulating layer 3; wherein the electrical connection structure in the low dielectric constant insulating layer is completely wrapped by the low dielectric constant insulating layer 6, and the bottom insulating layer includes the oxide insulating layer 3 and the low dielectric constant insulating layer 6.

During implementation, in step S1-4, by controlling the exposure area of the three-dimensional integrated circuit to be located within the side edge of the three-dimensional integrated circuit, the metal interconnection line 7 in the low dielectric constant insulating layer close to the side edge of the three-dimensional integrated circuit is completely wrapped by the low dielectric constant insulating layer 6.

The beneficial effect of the metal interconnection line 7 in the low dielectric constant insulating layer near the side edge of the three-dimensional integrated circuit being completely wrapped by the low dielectric constant insulating layer 6 is to prevent the metal ions of the metal interconnection line 7 in the low dielectric constant insulating layer of the bottom device layer near the side edge of the three-dimensional integrated circuit from being exposed from the side edge of the three-dimensional integrated circuit, causing contamination when forming the structure above the bottom functional device layer. Specifically, when the three-dimensional integrated circuit is a cylinder, its side edge is the side of the cylinder. The position of the exposure area within the side of the cylinder is controlled so that the outer edge of the pattern of the three-dimensional integrated circuit and the side of the cylinder maintain a preset distance, so that the metal interconnection line 7 in the low dielectric constant insulating layer of the bottom device layer is wrapped by the low dielectric constant insulating layer.

It should be noted that in the bottom functional device layer, multiple layers of low dielectric constant insulating layers 6 and metal interconnects 7 in the low dielectric constant insulating layers may be required. According to actual needs, as many layers as needed, the low dielectric constant insulating layers 6 and metal interconnects 7 in the low dielectric constant insulating layers can be prepared. For example, in the bottom functional device layer, seven or more layers of low dielectric constant insulating layers 6 and metal interconnects 7 in the low dielectric constant insulating layers are provided.

The step S2 of forming the silicon dioxide island isolation layer 8 and the first semiconductor layer of the first device layer thereon will be described in detail below.

Step S2 specifically includes the following steps:

As shown in FIG. 6 , step S2-1: a donor silicon wafer is oxidized to form a silicon dioxide island isolation layer 8, and a high-dose H+ ion implantation is performed in the donor silicon wafer to form an H+ ion implantation layer 15;

Step S2-2: Invert the donor silicon wafer, bond the silicon dioxide island isolation layer 8 to the low dielectric constant insulating layer 6 of the bottom device layer, and separate the bonded donor silicon wafer near the H+ ion implantation range by heat treatment at a temperature of 400° C. or higher and 600° C.;

As shown in FIG. 7 , step S2-3: performing a planarization (CMP) process on the silicon layer above the silicon dioxide island isolation layer 8 to form a first thin silicon layer 9 with a relatively flat upper surface, and the first thin silicon layer 9 serves as a first semiconductor layer;

Step S2-3 can also be: performing a planarization (CMP) process on the silicon layer above the silicon dioxide island isolation layer 8 to form a first thin silicon layer 9 with a relatively flat upper surface, and forming a first thin silicon epitaxial layer (not shown in the figure) on the first thin silicon layer 9 using a low-temperature epitaxial method. In this case, the first semiconductor layer includes a first thin silicon layer and a first thin silicon epitaxial layer.

Specifically, the epitaxial growth process temperature of the low-temperature epitaxial growth method is below 1000°C.

It should be noted that the silicon dioxide island isolation layer 8 is not a part of the upper first device layer, but a structure between the bottom device layer and the upper first device layer. At this point, the silicon dioxide island isolation layer 8 and the first thin silicon layer 9 of the upper first device layer are formed, and the preparation of the upper first device layer has begun.

As another optional method, the step of forming the island isolation layer specifically includes:

A silicon-germanium (Si-Ge) peeling layer is made on a donor silicon wafer, a thin silicon layer is epitaxially grown on the Si-Ge peeling layer, and a silicon dioxide island isolation layer is made on the thin silicon layer;

The donor silicon wafer is inverted and bonded to the device layer, i.e. the handle wafer, to form an insulating silicon wafer (SO Iwafer), which is then peeled off at the silicon germanium peeling layer using high-pressure nitrogen to form a silicon dioxide island isolation layer and a thin silicon layer on top of the device layer.

It can be carried out at room temperature, the surface of the thin silicon layer can be very thin (the thickness of the thin silicon layer ranges from greater than or equal to 2 nanometers to less than or equal to 220 nanometers), and the uniformity of the silicon dioxide island isolation layer is also relatively good, which can improve the quality of the thin silicon layer and reduce the manufacturing cost.

As another optional method, the step of forming the island isolation layer specifically includes:

A porous silicon layer is made on a donor silicon wafer, a high-quality thin silicon layer is epitaxially grown on the porous silicon layer, and a silicon dioxide island isolation layer is formed on the thin silicon layer;

The donor silicon wafer is inverted and bonded to the device layer, i.e., the handle wafer. The donor silicon wafer is then peeled off with a high-pressure water jet. The porous silicon layer is then etched away with hydrogen fluoride (HF) and hydrogen peroxide (H ₂ O ₂ ). The surface is then flattened by high-temperature hydrogen annealing at 1150°C. A silicon dioxide island isolation layer and a thin silicon layer are formed on the device layer. This can improve the quality of the thin silicon layer and reduce manufacturing costs.

The following describes in detail the step S3 of preparing the structure of the upper first device layer except the first semiconductor layer by using a low thermal budget manufacturing process and forming the first inter-layer TSV through hole.

Step S3 specifically includes the following steps:

Step S3-1: forming a device isolation 10, wherein the device isolation 10 penetrates the first semiconductor layer, and the device isolation 10 surrounds the outside of a preset position of a functional device 11 of the first functional device layer;

The device isolation is formed by STI, or the device isolation is formed by oxygen implantation.

The specific steps and technical effects of forming the shallow trench isolation (STI) step S3-1 have been recorded in the first embodiment and will not be described in detail here.

Step S3 specifically also includes the following steps:

As shown in Figure 8, step S3-2: a functional device 11 of a first functional device layer is formed on the first semiconductor layer. In the annealing process after ion implantation and the stress relief annealing process in the process of forming the functional device 11 of the first functional device layer, a low thermal budget flash millisecond annealing process is adopted. The annealing temperature range of the low thermal budget flash millisecond annealing process is greater than or equal to 750°C and less than or equal to 1200°C.

The bottom device layer and the first device layer above are isolated by a silicon dioxide island isolation layer 8. The heat from the low thermal budget flash millisecond annealing cannot be transferred to the metal interconnection line 7 in the low dielectric constant insulating layer of the bottom device layer, thus solving the problem of the heat in the manufacturing process of the first device layer above affecting the metal interconnection line 7 in the low dielectric constant insulating layer of the bottom device layer. This is a very important link in the preparation method of three-dimensional integrated circuits.

Step S3 specifically also includes the following steps:

Step S3-3: The specific steps of forming ohmic contact have been described in the first embodiment and will not be described in detail here.

Step S3 specifically also includes the following steps:

Step S3-4: forming an oxide insulating layer 3 on the device isolation 10, the functional device 11 of the first functional device layer, and the first semiconductor layer;

Step S3-5: forming a tungsten through hole 4 on the ohmic contact position of the oxide insulating layer 3, and forming a first interlayer TSV through hole 12 penetrating upward on the metal interconnection line 7 in the low dielectric constant insulating layer 6 in the bottom device layer;

As shown in FIG. 9 , step S3-6: forming a metal interconnection line 5 in the oxide insulating layer 3, wherein the first interlayer TSV via 12 is connected to at least one of the metal interconnections 5 in the oxide insulating layer 3 in the bottom device layer;

As shown in Figure 10, step S3-7: a low dielectric constant insulating layer 6 and a metal interconnection line 7 in the low dielectric constant insulating layer are formed on the oxide insulating layer 3, and the metal interconnection line 7 in the low dielectric constant insulating layer is wrapped by the dielectric constant edge layer so that the metal interconnection line 7 in the low dielectric constant insulating layer will not be exposed from the edge of the three-dimensional integrated circuit; wherein the first insulating layer includes the oxide insulating layer 3 and the low dielectric constant insulating layer 6, and the electrical connection structure of the first insulating layer includes the tungsten through hole 4 and the metal interconnection line 5 in the oxide insulating layer 3, and the metal interconnection line 5 in the low dielectric constant insulating layer 6.

The beneficial effect of the metal interconnection line 7 in the low dielectric constant insulating layer near the side edge of the three-dimensional integrated circuit being completely wrapped by the low dielectric constant insulating layer 6 is to prevent the metal ions of the metal interconnection line 7 in the low dielectric constant insulating layer of the bottom device layer near the side edge of the three-dimensional integrated circuit from being exposed from the side edge of the three-dimensional integrated circuit, causing contamination when forming the structure above the bottom functional device layer. Specifically, when the three-dimensional integrated circuit is a cylinder, its side edge is the side of the cylinder. The position of the exposure area within the side of the cylinder is controlled so that the outer edge of the pattern of the three-dimensional integrated circuit and the side of the cylinder maintain a preset distance, so that the metal interconnection line 7 in the low dielectric constant insulating layer of the bottom device layer is wrapped by the low dielectric constant insulating layer.

It should be noted that in the upper first device layer, multiple layers of low dielectric constant insulating layers 6 and metal interconnection lines 7 in the low dielectric constant insulating layers may be required. According to actual needs, as many layers as needed, the low dielectric constant insulating layers 6 and metal interconnection lines 7 in the low dielectric constant insulating layers can be prepared. For example, in the upper first device layer, seven or more layers of low dielectric constant insulating layers 6 and metal interconnection lines 7 in the low dielectric constant insulating layers are provided.

The step of forming the first interlayer TSV via 12 in step S3-5 specifically includes:

Step S3-5-1: forming a first interlayer via hole penetrating upward on the metal interconnection line 7 in the low dielectric constant insulating layer;

Step S3-5-2: depositing a titanium (Ti) film or a titanium nitride (TiN) film at the bottom of the first interlayer via hole;

Step S3 - 5 - 3 : Filling tungsten metal on the titanium (Ti) film or the titanium nitride (TiN) film to form a first interlayer TSV through hole 12 .

The three-dimensional integrated circuit further includes an upper second device layer, ..., an upper nth device layer arranged in sequence from above the upper first device layer; wherein the value range of n is greater than or equal to 2 and less than or equal to 50; correspondingly:

A silicon dioxide island isolation layer is respectively provided between adjacent layers of the upper first device layer, the upper second device layer, ..., and the upper nth device layer;

The upper first device layer, the upper second device layer, ..., the upper nth device layer and adjacent layers are connected through the second inter-layer TSV vias, ..., the nth inter-layer TSV vias.

The preparation of the second upper device layer, ..., and the nth upper device layer corresponds to that of the first upper device layer, the preparation of the second interlayer TSV vias, ..., and the nth interlayer TSV vias corresponds to that of the first interlayer TSV vias, and the preparation of the silicon dioxide island isolation layer is the same.

The method for preparing the three-dimensional integrated circuit of the embodiment of the present application further includes the following steps:

As shown in FIG. 11 , step S4 : preparing the top aluminum pad layer 13 and the passivation layer 14 .

The present application adopts a multi-layer cycle preparation method of a bottom device layer, a silicon dioxide island isolation layer, a first device layer above, a silicon dioxide island isolation layer, a second device layer above, a silicon dioxide island isolation layer, ..., and an nth device layer above. Compared with the preparation method of a 3D packaged chip in the prior art, on the one hand, the preparation method of the three-dimensional integrated circuit of the present application efficiently utilizes the vertical space, so that the integration density of the prepared three-dimensional integrated circuit is higher; on the other hand, the preparation method of the three-dimensional integrated circuit of the present application avoids the ultra-thinning process, so that the stress warping of the three-dimensional integrated circuit is smaller.

The three-dimensional integrated circuit prepared by the preparation method of the three-dimensional integrated circuit of the present application has a higher integration density, which brings about the problem of high power consumption density and heat density. The vertical connection vertical heat dissipation channel (composed of tungsten through-hole 4, metal interconnection line 5 in oxide insulating layer, metal interconnection line 7 in low dielectric constant insulating layer, and first interlayer TSV through-hole 12) of the three-dimensional integrated circuit prepared by the preparation method of the three-dimensional integrated circuit of the present application adopts high temperature resistant material to improve the stability of the three-dimensional integrated circuit. The integration density of tungsten through-hole 4, metal interconnection line 5 in oxide insulating layer, metal interconnection line 7 in low dielectric constant insulating layer, and first interlayer TSV through-hole 12 is high, so the bottom substrate, the first thin silicon layer, the second thin silicon layer, ..., the area of the nth thin silicon layer is small, which reduces the cost of the three-dimensional integrated circuit, and at the same time, also reduces the parasitic capacitance.

In addition, the manufacturing method of the three-dimensional integrated circuit of the present application does not involve any packaging factory for processing the back redistribution layer and micro-bumps. Therefore, multi-layer manufacturing can be directly realized at the three-dimensional integrated circuit manufacturer, and stricter process control can be achieved. Once the technology matures, high-density interconnection can be achieved, which greatly improves the computing power of the three-dimensional integrated circuit and realizes high-speed storage and computing integration.

As an optional method, the functional devices of the bottom functional device layer, the first functional device layer, the second functional device layer, ..., the functional devices of the nth functional device layer can each realize the same function, that is, the three-dimensional integrated circuit is homogeneously integrated.

As another optional method, the functional devices of the bottom functional device layer, the first functional device layer, the second functional device layer, ..., the functional devices of the nth functional device layer can also realize different functions respectively, forming a three-dimensional integrated circuit with diversified functions. That is, the three-dimensional integrated circuit is heterogeneous integrated. For example, the multiple processing units, storage units, sensors and other functional components of the diversified three-dimensional integrated circuit can be arranged in multiple layers, making the functions of the three-dimensional integrated circuit more diversified and flexible.

Specifically, the bottom substrate is a P-type silicon substrate.

Specifically, the functional devices of the bottom functional device layer, the first functional device layer, the second functional device layer, ..., the functional devices of the nth functional device layer include but are not limited to planar structured CMOS transistors, all-around gate (GAA) nanosheet field effect transistors, and fin field effect (FinFET) transistors. GAAFET stands for Gate-All-Around Effect Transistor, and its Chinese name is all-around gate field effect transistor. FinFET stands for Fin Field-Effect Transistor, and its Chinese name is Fin Field Effect Transistor, which is a complementary metal oxide semiconductor transistor. FinFET is named according to the similarity of the shape of the transistor to a fish fin.

Atomic layer deposition (ALD), also known as atomic layer deposition or atomic layer epitaxy, is a chemical vapor thin film deposition technology based on ordered, surface self-saturation reactions.

The annealing process is combined with other processes (such as ion implantation, thin film deposition, formation of metal silicide, etc.), and the most common is thermal annealing after ion implantation.

Embodiment 3

The three-dimensional integrated circuit of the embodiment of the present application, based on the first embodiment, further has the following characteristics.

As shown in Figure 12, the three-dimensional integrated circuit of the embodiment of the present application also includes an annealing barrier layer 16 of a metal material, and the annealing barrier layer 16 is used to cover the structure of the device layer of this layer to prevent the annealing light of the annealing process in the preparation process of the device layer located above from heating the structure under the annealing barrier layer of the device layer of this layer.

The characteristic of the annealing barrier layer is that it does not transmit the annealing light. Whether the annealing barrier layer can transmit the annealing light is related to the wavelength of the annealing light. Commonly used equipment for laser annealing includes _CO2 lasers in the 10.6um band and KrF short-wave lasers in the 248nm band. Short-wave lasers are easier to block.

As an optional method, both an island isolation layer and an annealing barrier layer are provided. In this way, the lower device layer (the device layer corresponding to the current layer) is prepared first, then the island isolation layer is prepared, and then the upper device layer is prepared. Due to the existence of the island isolation layer, a large amount of heat generated by the light of the annealing process during the preparation of the upper device layer will be blocked by the island isolation layer, and part of the heat will be limited to the position of the island isolation layer, so that the heat that can enter the lower device layer is greatly reduced. Since the annealing barrier layer 16 has a certain shading effect on the annealing light (shading is related to the wavelength of the annealing light), the heat entering the lower device layer is blocked again by the annealing barrier layer of the lower device layer, so that the annealing light that passes through the annealing barrier layer 16 becomes very small, so that the heat will not heat the structure under the annealing barrier layer of the lower device layer that has been prepared, thereby avoiding the burning of the lower device layer.

As another optional method, only an annealing barrier layer may be provided. The annealing barrier layer is located in the device layer below. When preparing a three-dimensional integrated circuit, the device layer below is prepared first, and then the device layer above is prepared. Due to the presence of the annealing barrier layer in the body of the device layer below, a large amount of heat generated by the light of the annealing process during the preparation of the device layer above will be blocked by the annealing barrier layer of the device layer below, and the heat will be limited to the position of the annealing barrier layer of the device layer below, so that the heat will not heat the structure below the annealing barrier layer of the device layer below that has been prepared, thereby avoiding burning of the device layer below.

The annealing barrier layer of the device layer below can cover all structures of the device layer body below that may need to be covered.

As an optional manner, the annealing barrier layer of the device layer of this layer covers the metal silicide region and the low-melting-point metal region of the functional device of the device layer of this layer; wherein the melting point of the low-melting-point metal region is lower than the annealing temperature of the annealing process during the preparation of the device layer located above; the metal silicide region includes but is not limited to the source region, the drain region, and the gate metal silicide, and the low-melting-point metal region includes a metal via, a metal layer, a metal gate region, and a metal interconnection line.

The metal silicide region and low melting point metal region of the functional devices in the functional device layer below are the areas in the functional devices in the functional device layer below that need to block heat. Therefore, the annealing barrier layer of the device layer below (corresponding to the interval layer of this layer) needs to cover the metal silicide region and low melting point metal region of the functional devices in the functional device layer below.

The high melting point metal region in the functional device of the functional device layer below may not be covered or may be selected to be not covered. Considering that the high melting point metal region may be arranged alternately with the metal silicide region and the low melting point metal region, avoiding the high melting point metal region alone may make the shape of the annealing barrier layer too complicated, and it may be considered to cover the functional device of the functional device layer below as a whole. Therefore, another optional method is generated, that is, the annealing barrier layer of the device layer below covers the functional device of the functional device layer below.

The annealing barrier layer protects the functional devices of the underlying functional device layer (the device layer of this layer) as a whole. The annealing barrier layer has a relatively simple shape and is easy to process and manufacture.

The specific location of the annealing barrier layer is as follows:

As shown in FIG. 12 , the annealing barrier layer 16 of the bottom device layer is located in the low dielectric constant insulating layer 6 of the bottom insulating layer and is located above the height of the metal interconnection line 7 of the low dielectric constant insulating layer in the bottom insulating layer.

The annealing barrier layer 16 of the upper first device layer is located in the low dielectric constant insulating layer 6 of the first insulating layer, and is located above the height of the metal interconnection line 6 of the low dielectric constant insulating layer in the first insulating layer;

The annealing barrier layer of the second upper device layer is located in the low dielectric constant insulating layer 6 of the second insulating layer, and is located above the height of the metal interconnection line of the low dielectric constant insulating layer in the second insulating layer;

……;

The annealing barrier layer of the upper nth device layer is located in the low dielectric constant insulating layer 6 of the nth insulating layer, and is located above the height of the metal interconnection line of the low dielectric constant insulating layer in the nth insulating layer.

In this way, each device layer is provided with an annealing barrier layer within the low dielectric constant insulating layer of the current insulating layer, and the position is located above the height of the metal interconnection line of the low dielectric constant insulating layer of the current device layer, which can effectively protect the device layer of the current layer during the preparation process of the previous device layer.

Embodiment 4

The three-dimensional integrated circuit of the embodiment of the present application has the following features based on the first and third embodiments.

The three-dimensional integrated circuit of the embodiment of the present application is specifically a distributed integrated storage and computing chip, corresponding to:

The bottom device layer is a logic layer, and the bottom functional device layer is a logic circuit layer having multiple computing units;

The upper first device layer is an upper first storage layer, and the first functional device layer is a first storage circuit layer having a plurality of storage units;

The upper second device layer is an upper second storage layer, and the second functional device layer is a second storage circuit layer having a plurality of storage units;

……;

The upper nth device layer is the upper nth storage layer, and the nth functional device layer is the nth storage circuit layer having a plurality of storage units.

The three-dimensional integrated circuit of the present application is specifically a distributed integrated storage and computing chip, which is essentially a real 3D chip that integrates computing and storage on one chip, greatly increasing the degree of integration.

The computing unit of the logic layer, the storage unit of the second storage layer above, ..., the storage unit of the nth storage layer above are connected to each other through the first interlayer via hole and the conductive material therein, the second interlayer via hole and the conductive material therein, ..., the nth interlayer via hole and the conductive material therein. The aperture of each interlayer via hole and the diameter of the conductive material filled therein can be made very small, so that the loss and delay of the interconnection are reduced.

At the same time, the number of interlayer vias and the conductive materials in each layer is large, which can be close to the number of transistors, making the bandwidth of the three-dimensional integrated circuit larger.

The logic layer generates more heat, so placing it at the bottom of the integrated circuit is closest to the heat dissipation path, which provides better heat dissipation.

Specifically, the diameter of the interlayer via holes of each layer and the diameter of the conductive material therein are less than or equal to 1 μm. The diameter of each interlayer via hole and the diameter of the conductive material filled therein can be made very small, so that the loss and delay of the interconnection are very small.

In implementation, the plurality of computing units of the logic circuit layer are evenly distributed and arranged; the storage units of the first storage circuit layer, the second storage circuit layer, ..., the nth storage circuit layer are evenly distributed and arranged.

The distributed and uniform arrangement of the computing units makes the calculation amount of a single computing unit smaller and the computing power of a single logic circuit layer stronger.

In implementation, the storage unit of any storage circuit layer of the first storage circuit layer, the second storage circuit layer, ..., and the nth storage circuit layer is SRAM or DRAM, or part is SRAM and part is DRAM.

In the description of the present application and its embodiments, it should be understood that the orientation or positional relationship indicated by the terms "top", "bottom", "height", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

In the present application and its embodiments, unless otherwise clearly specified and limited, the terms "set", "install", "connect", "connect", "fix" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

In the present application and its embodiments, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

The disclosure above provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numerals and/or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and/or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can be aware of the application of other processes and/or the use of other materials.

Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims (16)

1. A three-dimensional integrated circuit, comprising:

A bottom device layer; the bottom device layer comprises a bottom substrate, a bottom functional device layer and a bottom insulating layer which are arranged from bottom to top; wherein, the bottom insulating layer is provided with an electric connection structure connected with a functional device of the bottom functional device layer;

an upper first device layer formed above the bottom device layer, the upper first device layer comprising a first semiconductor layer, a first functional device layer, a first insulating layer disposed from bottom to top; wherein the first insulating layer is provided with an electric connection structure connected with the functional devices of the first functional device layer;

A first interlayer via hole and a conductive material filled therein, connecting the electrical connection structure of the bottom insulating layer and the electrical connection structure of the first insulating layer; the first interlayer through hole is a TSV tungsten through hole or a TSV copper through hole;

the first semiconductor layer includes a transparent thin silicon layer;

The device layer further comprises an annealing barrier layer made of a metal material, the annealing barrier layer is used for covering the structure of the device layer of the layer, and the annealing barrier layer avoids the vertical through holes so as not to be connected with the vertical through holes, so that annealing light of an annealing process in the preparation process of the device layer above is prevented from heating the structure below the annealing barrier layer of the device layer of the layer;

the annealing barrier layer is positioned in the insulating layer of the device layer of the layer;

the bottom insulating layer comprises an oxide insulating layer and a low dielectric constant insulating layer which are arranged from bottom to top;

the electrical connection structure of the bottom insulating layer includes:

tungsten vias disposed within the oxide insulating layer and over the functional devices of the first functional device layer;

a metal interconnect line disposed within the oxide insulating layer connected over the tungsten via;

A metal interconnect line disposed in the low dielectric constant insulating layer, and the metal interconnect line in the low dielectric constant insulating layer is connected with the metal interconnect line in the oxide insulating layer;

The metal interconnection lines in the low-dielectric-constant insulating layer of the bottom insulating layer are completely wrapped by the low-dielectric-constant insulating layer in the transverse direction, and the metal interconnection lines in the oxide insulating layer of the bottom insulating layer are completely wrapped by the oxide insulating layer in the transverse direction.

2. The three-dimensional integrated circuit of claim 1, further comprising:

an island isolation layer formed over the bottom insulating layer and between the upper first device layers.

3. The three-dimensional integrated circuit of claim 2, further comprising an upper second device layer, … …, an upper nth device layer arranged in sequence from above the upper first device layer; wherein, the value range of n is more than or equal to 2 and less than or equal to 50; corresponding to:

island isolation layers are respectively arranged between adjacent layers of the upper first device layer, the upper second device layer, … … and the upper n device layer;

the upper first device layer, the upper second device layer, … … and the upper n device layer are connected through the second interlayer through hole and the conductive substance therein, … … and the n device layer through hole and the conductive substance therein.

4. The three-dimensional integrated circuit of claim 3, wherein the first semiconductor layer has device isolation extending through the first semiconductor layer, the device isolation surrounding an outside of the functional devices of the first functional device layer;

wherein the device isolation is formed by STI, or the device isolation is formed by oxygen implantation.

5. The three-dimensional integrated circuit of claim 4, wherein the h semiconductor layer is an h thin silicon layer; the thickness of the h thin silicon layer is larger than or equal to 2 nanometers and smaller than or equal to 220 nanometers, and h times are from 1 to n;

Or the h semiconductor layer comprises an h thin silicon layer and an h thin silicon epitaxial layer which are arranged from bottom to top; the thickness of the h thin silicon layer is more than or equal to 2 nanometers and less than or equal to 220 nanometers; the thickness of the h thin silicon epitaxial layer is larger than or equal to 40 nanometers and smaller than or equal to 70 nanometers, and the h times are from 1 to n.

6. The three-dimensional integrated circuit according to claim 4, wherein a low thermal budget flash millisecond anneal process is employed in the post-ion implantation anneal process and the stress relief anneal process during formation of the functional devices of the first functional device layer, the low thermal budget flash millisecond anneal process having an anneal temperature ranging from 750 ℃ to 1200 ℃;

The conductive material in the first interlayer via has a melting point higher than an annealing temperature of a low thermal budget flash millisecond annealing process.

7. The three-dimensional integrated circuit of claim 4, wherein the bottom device layer further comprises:

And the bottom substrate epitaxial layer is formed on the bottom substrate, and the functional devices of the bottom functional device layer are positioned on the bottom substrate epitaxial layer.

8. The three-dimensional integrated circuit of claim 7, wherein ohmic contacts are formed in the source and drain of the functional devices of the first functional device layer at locations where vertical tungsten vias are desired.

9. The three-dimensional integrated circuit of claim 8, wherein the first insulating layer comprises a bottom-up disposed oxide insulating layer and a low dielectric constant insulating layer;

the electrical connection structure of the first insulating layer includes:

tungsten vias disposed over ohmic contact locations of the oxide insulating layer;

A metal interconnect line disposed within the oxide insulating layer and over the tungsten via;

A metal interconnect line disposed in the low dielectric constant insulating layer, and the metal interconnect line in the low dielectric constant insulating layer is connected with the metal interconnect line in the oxide insulating layer;

The metal interconnection lines in the low-dielectric-constant insulating layer of the first insulating layer are completely wrapped by the low-dielectric-constant insulating layer in the transverse direction, and the metal interconnection lines in the oxide insulating layer of the first insulating layer are completely wrapped by the oxide insulating layer in the transverse direction;

the first interlayer through hole is connected with the metal interconnection line of the low dielectric constant insulating layer in the bottom device layer and the metal interconnection line of the oxide insulating layer in the upper first device layer.

10. The three-dimensional integrated circuit of claim 9, wherein the vertical vias comprise interlayer vias, tungsten vias.

11. The three-dimensional integrated circuit of claim 10, wherein the anneal-blocking layer of the device layer of the present layer masks functional devices of the device layer of the present layer;

Or the annealing barrier layer of the device layer of the layer covers the metal silicide region and the low-melting-point metal region of the functional device of the device layer of the layer; wherein the melting point of the low-melting-point metal area is lower than the annealing temperature of an annealing process in the preparation process of the device layer positioned above; the metal silicide region comprises, but is not limited to, a source region, a drain region and a gate metal silicide, and the low-melting-point metal region comprises a metal through hole, a metal layer, a metal gate region and a metal interconnection line.

12. The three-dimensional integrated circuit of claim 11, wherein the anneal-blocking layer of the bottom device layer is located within the low-k insulating layer of the bottom insulating layer and above a level of metal interconnect lines of the low-k insulating layer in the bottom insulating layer.

13. The three-dimensional integrated circuit of claim 12, wherein the anneal-blocking layer of the upper first device layer is located within the low-k insulating layer of the first insulating layer and above the level of the metal interconnect lines of the low-k insulating layer in the first insulating layer;

The annealing barrier layer of the upper second device layer is positioned in the low dielectric constant insulating layer of the second insulating layer and is positioned above the height of the metal interconnection line of the low dielectric constant insulating layer in the second insulating layer;

……；

the annealing barrier layer of the upper n-th device layer is positioned in the low dielectric constant insulating layer of the n-th insulating layer and is positioned above the height of the metal interconnection line of the low dielectric constant insulating layer in the n-th insulating layer.

14. The three-dimensional integrated circuit of claim 13, wherein the three-dimensional integrated circuit is a distributed integrated memory chip, corresponding to:

The bottom device layer is a logic layer, and the bottom functional device layer is a logic circuit layer with a plurality of computing units;

the upper first device layer is an upper first storage layer, and the first functional device layer is a first storage circuit layer with a plurality of storage units;

the upper second device layer is an upper second storage layer, and the second functional device layer is a second storage circuit layer with a plurality of storage units;

……；

the upper n-th device layer is an upper n-th memory layer, and the n-th functional device layer is an n-th memory circuit layer having a plurality of memory cells.

15. The three-dimensional integrated circuit of claim 14, wherein the plurality of computing units of the logic circuit layer are uniformly distributed; the memory cells of the first memory circuit layer, the second memory circuit layer, … … and the nth memory circuit layer are distributed and uniformly arranged.

16. The three-dimensional integrated circuit of claim 15, wherein the memory cells of any one of the first, second, … …, and nth memory circuit layers are SRAM or DRAM or are partially SRAM and partially DRAM.