CN100570846C - High Aspect Ratio 3D Vertical Interconnection and Implementation Method of 3D Integrated Circuit - Google Patents

Abstract

The invention discloses a method for realizing a three-dimensional vertical interconnection with a high aspect ratio and a three-dimensional integrated circuit, which belong to the technical fields of semiconductor manufacturing technology and micro sensor manufacturing technology. The method includes: performing deep reactive ion etching on the front surface of a semiconductor wafer with a planar integrated circuit or a micro sensor to obtain a deep hole; depositing an insulating layer, a diffusion barrier layer and an electroplating seed layer on the front surface; The electroplating surface is temporarily bonded to the auxiliary wafer, and the back of the semiconductor wafer is thinned so that the DRIE deep hole is exposed from the back; an insulating layer, a diffusion barrier layer, and an electroplating seed layer are deposited on the back; a bottom-up electroplating process is performed, and the The DRIE deep hole is filled to form a high aspect ratio three-dimensional vertical interconnection; the auxiliary wafer is removed to realize the vertical integration of two-layer wafers; the above steps are repeated to realize more layers of three-dimensional integrated circuits. The invention reduces the process difficulty of filling through holes with high aspect ratio. The manufacturing process is simplified and the yield rate is guaranteed.

Description

High Aspect Ratio 3D Vertical Interconnection and Implementation Method of 3D Integrated Circuit

technical field

The invention belongs to the technical field of semiconductor and micro-sensor manufacturing, and in particular relates to a high-aspect-ratio three-dimensional vertical interconnect and a method for realizing a three-dimensional integrated circuit using the three-dimensional integrated circuit manufacturing technology.

Background technique

The continuous shrinking of integrated circuit devices has continuously improved the integration level. At present, more than 1 billion transistors can be integrated on a chip area per square centimeter, and the total length of metal interconnection lines reaches tens of kilometers. This not only makes the wiring extremely complicated, but more importantly, the delay, power consumption, and noise of the metal interconnection increase with the reduction of the feature size, especially the RC delay of the global interconnection, which seriously affects the integrated circuit. performance. In addition, the dynamic power consumption is directly proportional to the load capacitance value of the circuit. More than half of the dynamic power consumption of mainstream high-performance microprocessors is caused by interconnection lines. The use of copper interconnects and low-K dielectrics, as well as the addition of a series of buffers on the global interconnect line reduce the series resistance and parasitic capacitance, making the integrated circuit develop to 90nm and improve the overall performance, but even with the introduction of ultra-low K The medium can only maintain the development of the process to the 65nm node, and greatly increases the power consumption of the circuit. Therefore, metal interconnection has replaced transistors as the main factor determining the performance of integrated circuits. The development limit of integrated circuits is not the failure of Moore's Law. Interconnection, cost and complexity are becoming the real bottlenecks that limit the development of integrated circuits in the future.

System-on-a-chip (SOC, System on a Chip) technology realizes all the functions of the system on a single chip, such as digital, analog, radio frequency, optoelectronics and MEMS. The biggest difficulty in the development of SOC is the compatibility of different processes. For example, different functional modules may require standard CMOS, SiGe RF, BiCMOS, Bipolar, GaAs, and MEMS processes. These manufacturing processes and substrate materials are different, and it is difficult to integrate them on a chip. Even for modules with the same substrate material, the manufacturing feasibility, cost, and yield of each circuit module must be considered during manufacture. Therefore, the chip of the multi-function module is still discrete at present.

Three-dimensional integration is based on planar circuits, using three-dimensional vertical interconnection through the substrate to integrate multi-layer chips, that is, to divide a large planar circuit into several logically related functional modules and distribute them on multiple adjacent chips. layer, and then achieve multi-layer chip integration through three-dimensional vertical interconnects penetrating the substrate. Three-dimensional interconnection can realize the vertical integration of multi-chips with different functions and different processes, and greatly reduce the length of global interconnection, thereby greatly reducing interconnection delay, increasing the speed of integrated circuits, and reducing power consumption of chips. Three-dimensional interconnection can integrate multi-layer integrated circuits with different processes or different substrate materials, which provides a good solution for SOC of heterogeneous chips. Three-dimensional interconnection is a physical interconnection, which can solve the problems of delay and noise caused by multi-chip heterogeneous integration, high-bandwidth communication and interconnection. These characteristics make it the most feasible means to solve the bottleneck problem faced by planar integrated circuits.

The realization of three-dimensional integrated circuits first requires the realization of three-dimensional interconnection lines penetrating the semiconductor wafer substrate, which is the core of three-dimensional integration technology. Currently, technologies for realizing three-dimensional interconnection mainly include through-hole-based and blind-via-based implementations.

The implementation method based on blind holes fills the holes with openings on one side, and then obtains interconnection lines that penetrate the semiconductor layer through operations such as thinning, and realizes interconnection by single-side etching and Damascene plating. The semiconductor wafer maintains the original thickness and has good operability. After the interconnection line is filled, it can be bonded with the auxiliary wafer and thinned to make the semiconductor wafer with vertical interconnection lines to obtain a three-dimensional penetration through the substrate. For interconnection, a very thin substrate layer can be obtained, generally in the range of tens of microns to tens of microns. However, since only Damascus plating can be used, it is easy to form holes and gaps inside the interconnection lines.

The implementation method based on the through hole first obtains the through hole penetrating the substrate before filling the vertical interconnection line, and can perform double-sided operation, that is, fill the copper by bottom-up electroplating after the opening of the through hole is sealed by single-sided electroplating. This method is easy to fill through holes, but in order to ensure the operability of the semiconductor wafer, the thickness of a single-layer semiconductor wafer is often more than 200 microns, even if the aspect ratio of the vertical interconnection line is as high as 20, the lateral dimension of the interconnection line is too large. Above 10 microns, the improvement of interconnect line density is limited.

One solution is to make an electroplating seed layer on the front side of the semiconductor wafer, and then conduct a thinning treatment on the semiconductor wafer through temporary bonding of the auxiliary wafer, and then perform deep reactive ion etching (DRIE) to obtain a deep hole, then deposit the insulating layer and selectively etch the insulating layer at the bottom of the hole to maintain the insulating effect of the side wall, and finally adopt the bottom-up electroplating method to obtain high-density vertical interconnection. This method corresponds to The problem is that during deep etching, lateral undercutting will occur at the position of the seed layer, which is difficult to control. In addition, the growth of the insulating layer on the side wall of the deep hole is very difficult, and in addition to the selective etching after one-step growth, it is difficult to ensure mutual The insulation effect of the wiring on the substrate.

Contents of the invention

The purpose of the present invention is to provide a high aspect ratio three-dimensional vertical interconnection and three-dimensional integrated circuit implementation method to solve the problems in the above various three-dimensional integrated circuit implementation methods. The technical solution includes:

Step A: Perform DRIE deep reactive ion etching on the front side of the first layer of semiconductor wafer that has fabricated ordinary integrated circuits or micro sensors to obtain DRIE deep holes;

Step B: Depositing an insulating layer, a diffusion barrier layer and an electroplating seed layer on the front surface of the first semiconductor wafer;

Step C: performing electroplating on the front side of the first layer of semiconductor wafer, and sealing the opening of the DRIE deep hole;

Step D: Temporarily bonding the first-layer semiconductor wafer to the auxiliary wafer, and thinning the back of the semiconductor wafer, so that the DRIE deep hole is exposed from the back to form a DRIE through hole;

Step E: Deposit an insulating layer, a diffusion barrier layer and an electroplating seed layer on the back of the first layer of semiconductor wafer, so that it enters the inside of the DRIE deep hole from the back of the semiconductor wafer;

Step F: using a bottom-up electroplating process to fill the DRIE through holes on the first layer of semiconductor wafer with conductive metal to form a three-dimensional vertical interconnection with a high aspect ratio;

Step G: Make metal bumps on the back of the first layer of semiconductor wafers by electroplating, and realize physical and electrical connection with the second layer of semiconductor wafers by means of bump bonding, and then etch the temporary bonding layer to remove the auxiliary Wafer, realizing vertical integration of two-layer wafers.

The semiconductor wafer uses silicon, silicon germanium, gallium arsenide or silicon on insulator (SOI) as the substrate material for making circuits.

The backside thinning operation in the step D adopts independent or combined methods such as mechanical grinding, chemical mechanical polishing (CMP), chemical etching, and plasma etching.

The bonding of the semiconductor wafer and the auxiliary wafer in the step D uses an organic polymer material as an intermediate layer.

In the step F, the metal material for the bottom-up electroplating to fill the through hole is copper, tungsten, or other metal materials that can be subjected to electroplating process.

The step G further includes: filling the gaps between the first-layer semiconductor wafer and the second-layer semiconductor wafer except for the bonding bumps with organic matter, and curing.

The step G further includes: the material of the bump is one or more of copper, tin, gold, indium or lead, or an alloy material composed of any two or more of them.

The method further includes: taking the three-dimensional integrated circuit formed by the first-layer semiconductor wafer and the second-layer semiconductor wafer as a new semiconductor wafer, and repeatedly performing the steps A to G to realize multiple A three-dimensional integrated circuit composed of layered semiconductor wafers.

The technical solution provided by the present invention has the following advantages: the method of DRIE etching before thinning avoids the lateral undercutting at the bottom of the deep hole in the conventional method, and eliminates the dependence of the etching speed on the size of the deep hole; Deposit insulating layer, diffusion barrier layer and electroplating seed layer, and then deposit insulating layer, diffusion barrier layer and electroplating seed layer from the back after thinning. This double-sided deposition does not require bottom selective etching and can Realize the coverage of the insulating layer and the diffusion barrier layer in the high aspect ratio via hole, and solve the problem of difficult deposition of the internal insulating layer, diffusion barrier layer and electroplating seed layer of the high aspect ratio via hole; and adopt the bottom-up electroplating process to fill the via hole Overcoming the problem of gaps easily appearing in single-sided Damascus plating high aspect ratio structures, it can reduce the difficulty of filling high aspect ratio through holes, realize high aspect ratio three-dimensional interconnection, effectively reduce the difficulty of the process, and avoid voids and gaps; The single-layer semiconductor wafer can be very thin and can realize high-density three-dimensional vertical interconnection.

Description of drawings

FIG. 1 is a flowchart of a method for realizing a three-dimensional interconnection and a three-dimensional integrated circuit corresponding to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a semiconductor wafer W1 corresponding to an embodiment of the present invention;

3 is a schematic diagram of depositing a protective layer 13 on the front side of the semiconductor wafer W1 in FIG. 2 according to an embodiment of the present invention, and then performing deep reactive ion etching (DRIE) to obtain deep holes 14;

FIG. 4 is a schematic diagram corresponding to the embodiment of the present invention after depositing an insulating layer, a diffusion barrier layer 15 and an electroplating seed layer 16 on the front side of the semiconductor wafer W1 in FIG. 3;

FIG. 5 is a schematic diagram of sealing the front opening of the DRIE deep hole 14 by electroplating the front of the semiconductor wafer W1 in FIG. 4 according to the embodiment of the present invention;

FIG. 6 is a schematic diagram after bonding the semiconductor wafer W1 and the auxiliary wafer C1 in FIG. 5 by using the temporary bonding material B1 corresponding to the embodiment of the present invention;

7 is a schematic diagram of thinning the back of the semiconductor wafer W1 in FIG. 6 to expose the DRIE deep hole 14 from the back to form a through hole, and then depositing an insulating layer and a diffusion barrier layer from the back of the embodiment of the present invention;

FIG. 8 is a schematic diagram of the embodiment of the present invention corresponding to the DRIE through hole 14 in FIG. 7, using bottom-up electroplating technology to fill the conductive metal 18 to form a schematic diagram of a high aspect ratio three-dimensional vertical interconnection;

FIG. 9 is a schematic diagram corresponding to the embodiment of the present invention after metal bumps 19 for bonding are fabricated on the back of the semiconductor wafer W1 in FIG. 8;

Fig. 10 is the embodiment of the present invention corresponding to combining the semiconductor wafer W1 shown in Fig. 9 with the second-layer semiconductor wafer W2 through bump bonding, and filling the area outside the bumps with organic material FL , and finally the schematic diagram after removing the auxiliary wafer;

FIG. 11 is a schematic diagram corresponding to the embodiment of the present invention after performing metal rewiring on the front side of the semiconductor wafer in FIG. 10 and making bonding bumps or packaging pads 10 for vertical integration of new semiconductor layers;

FIG. 12 is a schematic diagram of a three-dimensional integrated circuit obtained under the method corresponding to the embodiment of the present invention.

Detailed ways

The present invention provides a method for realizing high aspect ratio three-dimensional vertical interconnection and three-dimensional integrated circuit. Consistent etching of through holes with different aspect ratios and avoiding lateral etching, using double-sided deposition of insulating layer, diffusion barrier layer and electroplating seed layer to solve the internal insulating layer, diffusion barrier layer and electroplating seed layer of high aspect ratio through holes The problem of difficult deposition, and the bottom-up electroplating process to fill the through-holes overcomes the problem that the single-sided Damascus electroplating high aspect ratio structure is prone to gaps.

The embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings. Embodiments of the present invention provide a simple and feasible method for realizing a three-dimensional integrated circuit based on electroplating interconnection, which can effectively realize a very thin and very compact three-dimensional integrated circuit with a single layer.

Fig. 1 shows the implementation method of a kind of three-dimensional interconnection and three-dimensional integrated circuit provided by this embodiment; Fig. 2 shows the semiconductor wafer used in this embodiment, which includes the fabricated integrated circuit or micro sensor device The semiconductor substrate W1, the multilayer metal interconnection 12 on the semiconductor substrate W1, and the interlayer dielectric layer or surface passivation layer 11 of the interconnection line, wherein the semiconductor substrate material can be silicon, silicon germanium, gallium arsenide (GaAs) or silicon-on-insulator (SOI). Taking the vertical integration of two-layer circuits based on the semiconductor wafer provided in Figure 2 as an example, the implementation method of a three-dimensional integrated circuit includes the following steps:

Step 1-01: Deposit an etching protective layer 13 on the surface passivation layer 11 of the semiconductor substrate W1 of the integrated circuit or microsensor and MEMS, and then use the protective layer 13 as a hard mask to carry out the surface passivation layer The dry etching of 11 and the DRIE etching of the substrate material W1 obtain deep holes 14, as shown in FIG. 3 .

Wherein, the protection layer 13 may be but not limited to silicon dioxide, silicon nitride, photoresist or metal material. The deposition method of the protective layer may adopt methods such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or sputtering in the prior art.

Step 1-02: Deposit an insulating layer and a diffusion barrier layer 15 with excellent step coverage effect on the front surface of the aforementioned semiconductor wafer W1, and sputter a seed layer 16, as shown in FIG. 4 .

In this embodiment, it is hoped that the deposition of the insulating layer has a good step coverage effect to ensure the insulation performance of the final vertical interconnect and the substrate. The material of the insulating layer can be but not limited to silicon dioxide or silicon nitride. The layer can be but not limited to TaN, etc., and the method used can be but not limited to plasma enhanced chemical vapor deposition (PECVD). The fabrication method of the electroplating seed layer is not expected to have good step coverage performance, and the sputtering method is chosen here, but the actual implementation is not limited to this method.

Step 1-03: Perform an electroplating operation on the front side of the semiconductor substrate W1, using the characteristics of lateral electroplating of the seed layer at the opening of the deep hole 14 to form a copper layer 17 to seal the front opening of the deep hole 14, as shown in Figure 5 .

Step 1-04: Use the temporary bonding material B1 to bond the front side of the semiconductor wafer W1 shown in FIG. 5 to the auxiliary wafer C1, as shown in FIG. 6 .

The temporary bonding material B1 used may be, but not limited to, an organic polymer material or an ultraviolet denaturable organic material. The auxiliary wafer C1 may be, but not limited to, glass material. Before bonding, chemical mechanical polishing (CMP) may be performed on the front surface of the semiconductor wafer W1 to improve surface flatness.

Step 1-05: Thinning the back of the semiconductor substrate W1 to expose the DRIE deep hole 14 from the back, and deposit an insulating layer and a diffusion barrier layer from the back, as shown in FIG. 7 .

The back thinning operation of the semiconductor substrate W1 may be performed independently or in combination with mechanical grinding, chemical mechanical polishing (CMP), chemical etching, plasma etching, and the like. The material of the insulating layer can be but not limited to silicon dioxide or silicon nitride, the barrier layer can be but not limited to TaN, etc., and the method used can be but not limited to PECVD or sputtering.

Step 1-06: Use the copper layer 17 on the front side of the semiconductor substrate W1 as the seed layer, and use the bottom-up electroplating technology to electroplate the back side of W1. Since only the bottom of the deep hole 14 has a seed layer, the electroplating process makes the deep hole 14 covered with a metal conductor. Column 18 is filled, as shown in FIG. 8 .

The metal filling the through hole 14 needs to be prepared by electroplating, which can be but not limited to copper, tungsten and other metals.

Step 1-07: Fabricate metal bumps 19 for bonding on the back of the semiconductor substrate W1, as shown in FIG. 9 .

The metal material used to fill deep holes and make bumps here can be one or more of copper, tin, gold, indium or lead, or any two or more alloy materials of them, but not limited to These types are described in this embodiment by taking copper material as an example.

Step 1-08: The semiconductor substrate W1 is bonded to the approximate metal bump of the ordinary semiconductor substrate W2 through the metal bump 19, and the gap outside the bonding bump is filled with the polymer material FL, and finally removed The auxiliary wafer C1 realizes the physical and electrical vertical connection of the two layers of semiconductor wafers, as shown in FIG. 10 .

Step 1-09: Perform metal rewiring on the front side of the semiconductor substrate W1, and make metal bumps or packaging pads 10 for the vertical integration of the new semiconductor layer, to obtain a two-layer stacked three-dimensional integrated circuit or for a further step Prepare for the three-dimensional integration, as shown in Figure 11.

After the above steps are completed, the three-dimensional integration of the two-layer circuit is realized. By applying the method provided by the embodiment of the present invention and repeating the above steps, a three-dimensional integrated circuit in which multiple layers of circuits are stacked vertically can be realized. And there is no requirement on the type of substrate material and lattice orientation, and it has good versatility.

Fig. 12 shows the schematic diagram of the three-dimensional integrated circuit realized by using the above-mentioned method, wherein, W1 represents the semiconductor substrate on which the integrated circuit (or micro sensor, MEMS structure) is fabricated; A semiconductor substrate with an integrated circuit (or MEMS structure); W3 represents the semiconductor substrate at the highest level where the integrated circuit (or MEMS structure) has been fabricated; 10, 20, and 30 represent the front surfaces of the semiconductor substrates W1, W2, and W3, respectively 12, 22, 32 represent the multi-layer interconnection on the semiconductor substrate W1, W2, W3 respectively; 18, 38 respectively represent the semiconductor substrate W1 and The three-dimensional interconnected metal pillars fabricated on W3; 19 and 39 represent the bonding bumps fabricated on the backsides of semiconductor substrates W1 and W3 respectively; FL represents that after the bump bonding is completed, the bonding surface is filled except for the bump position of organic materials.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (8)

1. A method for realizing a high aspect ratio three-dimensional vertical interconnection and a three-dimensional integrated circuit, characterized in that the steps for realizing the method are as follows: Step A: Perform DRIE deep reactive ion etching on the front side of the first layer of semiconductor wafer that has fabricated ordinary integrated circuits or micro sensors to obtain DRIE deep holes; Step B: Depositing an insulating layer, a diffusion barrier layer and an electroplating seed layer on the front surface of the first semiconductor wafer; Step C: performing electroplating on the front side of the first layer of semiconductor wafer, and sealing the opening of the DRIE deep hole; Step D: Temporarily bonding the first-layer semiconductor wafer to the auxiliary wafer, and thinning the back of the semiconductor wafer, so that the DRIE deep hole is exposed from the back to form a DRIE through hole; Step E: Deposit an insulating layer, a diffusion barrier layer and an electroplating seed layer on the back of the first layer of semiconductor wafer, so that it enters the inside of the DRIE deep hole from the back of the semiconductor wafer; Step F: using a bottom-up electroplating process to fill the DRIE through holes on the first layer of semiconductor wafer with conductive metal to form a three-dimensional vertical interconnection with a high aspect ratio; Step G: Make metal bumps on the back of the first layer of semiconductor wafers by electroplating, and realize physical and electrical connection with the second layer of semiconductor wafers by means of bump bonding, and then etch the temporary bonding layer to remove the auxiliary Wafer, realizing vertical integration of two-layer wafers. 2. The realization method of high aspect ratio three-dimensional vertical interconnection and three-dimensional integrated circuit according to claim 1, characterized in that, the semiconductor wafer uses silicon, silicon germanium, gallium arsenide or silicon-on-insulator SOI as the substrate for making the circuit. Substrate material. 3. The method for realizing high aspect ratio three-dimensional vertical interconnection and three-dimensional integrated circuit according to claim 1, characterized in that, in the step D, the backside thinning operation adopts mechanical grinding, chemical mechanical polishing CMP, chemical etching and plasma etching Eclipses independently or in combination. 4. The method for realizing high-aspect-ratio three-dimensional vertical interconnection and three-dimensional integrated circuits according to claim 1, wherein the temporary bonding of the semiconductor wafer and the auxiliary wafer in the step D uses an organic polymer material as an intermediate layer. 5. The method for realizing high aspect ratio three-dimensional vertical interconnection and three-dimensional integrated circuit according to claim 1, characterized in that, in the step F, the metal material to be electroplated and filled through holes from bottom to top is copper, tungsten, or other possible Metal material for electroplating process. 6. The method for realizing high-aspect-ratio three-dimensional vertical interconnection and three-dimensional integrated circuit according to claim 1, characterized in that said step G further comprises: filling said first layer of semiconductor wafer with polymer material and the gaps other than the bonding bumps between the second layer of semiconductor wafers, and solidify. 7. The method for realizing high-aspect-ratio three-dimensional vertical interconnection and three-dimensional integrated circuit according to claim 1, characterized in that, said step G further comprises: the material of said bump is copper, tin, gold, indium or One or more materials in lead, or alloy materials composed of any two or more of them. 8. The method for realizing high-aspect-ratio three-dimensional vertical interconnection and three-dimensional integrated circuit according to claim 1, characterized in that the method further comprises: connecting the first layer semiconductor wafer and the second layer semiconductor wafer The formed three-dimensional integrated circuit is used as a new semiconductor wafer, and the steps A to G are repeated to realize a three-dimensional integrated circuit composed of multiple layers of semiconductor wafers.

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