CN103378028B - Semiconductor structure with stress protection structure and method of forming same - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
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- 238000004806 packaging method and process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 241000724291 Tobacco streak virus Species 0.000 description 2
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- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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Abstract
本发明公开了一种具有应力保护结构的半导体结构，包括有基底、应力产生元件以及应力保护装置。基底具有第一表面以及第二表面，两个相对设置。应力产生元件设置在基底中。应力保护结构，设置在基底第一表面的一侧，应力保护结构包围应力产生元件，且应力保护结构内部具有密封的空气空间。本发明还提供了一种形成具有应力保护结构的半导体结构的方法。
The present invention discloses a semiconductor structure with a stress protection structure, comprising a substrate, a stress generating element and a stress protection device. The substrate has a first surface and a second surface, which are arranged opposite to each other. The stress generating element is arranged in the substrate. The stress protection structure is arranged on one side of the first surface of the substrate, the stress protection structure surrounds the stress generating element, and a sealed air space is provided inside the stress protection structure. The present invention also provides a method for forming a semiconductor structure with a stress protection structure.
Description
技术领域 technical field
本发明涉及了一种具有应力保护结构的半导体结构与其形成方法，特别来说，此应力保护结构具有密闭的空气空间，能提供应力缓冲效果。The invention relates to a semiconductor structure with a stress protection structure and its forming method. In particular, the stress protection structure has a closed air space and can provide stress buffering effect.
背景技术 Background technique
在现代的资讯社会中，由集成电路(integratedcircuit，IC)所构成的微处理系统早已被普遍运用于生活的各个层面，例如自动控制的家电用品、行动通讯设备、个人计算机等，都有集成电路的使用。而随着科技的日益精进，以及人类社会对于电子产品的各种想象，使得集成电路也往更多元、更精密、更小型的方向发展。In the modern information society, micro-processing systems composed of integrated circuits (ICs) have long been widely used in all aspects of life, such as automatic control of household appliances, mobile communication equipment, personal computers, etc., all have integrated circuits usage of. With the advancement of technology and the various imaginations of electronic products in human society, integrated circuits are also developing in a more diverse, more sophisticated, and smaller direction.
一般所称集成电路，是通过现有半导体工艺中所生产的晶粒(die)而形成。制造晶粒的过程，是由生产一晶圆(wafer)开始：首先，在一片晶圆上区分出多个区域，并在每个区域上，通过各种半导体工艺如沉积、光刻、蚀刻或平坦化工艺，以形成各种所需的电路路线。然后，在进行一般的测试步骤以测试内部元件是否能顺利运作。接着，再对晶圆上的各个区域进行切割而成各个晶粒，并加以封装成芯片(chip)，最后再将芯片电连至一电路板，如一印刷电路板(printedcircuitboard，PCB)，使芯片与印刷电路板的接脚(pin)电性连结后，便可执行各种程式化的处理。Generally, integrated circuits are formed through dies produced in existing semiconductor processes. The process of manufacturing crystal grains begins with the production of a wafer: first, multiple regions are distinguished on a wafer, and on each region, various semiconductor processes such as deposition, photolithography, etching or Planarization process to form various desired circuit routes. Then, general test steps are carried out to test whether the internal components can operate smoothly. Then, each region on the wafer is cut into each crystal grain, and packaged into a chip (chip), and finally the chip is electrically connected to a circuit board, such as a printed circuit board (printed circuit board, PCB), so that the chip After being electrically connected with the pins of the printed circuit board, various programmed processes can be performed.
为了提高芯片功能与效能，增加集成度以便在有限空间下能容纳更多半导体元件，相关厂商开发出许多半导体晶片的堆叠技术，包括了覆晶封装(flip-chip)技术、多晶片封装(multi-chippackage，MCP)技术、封装堆叠(packageonpackage，PoP)技术、封装内藏封装体(packageinpackage，PiP)技术等，都可以通过晶片或封装体间彼此的堆叠来增加单位体积内半导体元件的集成度。近年来又发展一种称为穿硅通孔(throughsiliconvia，TSV)的技术，可促进在封装体中各芯片间的内部连结(interconnect)，以将堆叠效率进一步往上提升。In order to improve chip functions and performance, increase integration so that more semiconductor components can be accommodated in a limited space, related manufacturers have developed many stacking technologies for semiconductor chips, including flip-chip packaging (flip-chip) technology, multi-chip packaging (multi-chip packaging) -chippackage, MCP) technology, package-on-package (PoP) technology, package-in-package (PiP) technology, etc., can increase the integration of semiconductor elements per unit volume by stacking chips or packages. . In recent years, a technology called through-silicon via (TSV) has been developed, which can promote the interconnection between chips in the package, so as to further improve the stacking efficiency.
然而，在现有的封装技术中，利用穿硅通孔来堆迭封装的结构，仍面临着许多问题。请参考图1，所示为公知技术中穿硅通孔的顶面示意图。如图1所示，公知的穿硅通孔102设置在基底100中。然而，由于穿硅通孔102中的材质例如金属铜，和基底100的材质例如半导体硅，之间会存在着热膨胀系数(coefficientofthermalexpansion，CTE)的差异，例如铜的热膨胀系数约为17.5×10-6K-1而硅的热膨胀系数约为2.5×10-6K-1，这样的情况会使得基底300在不同温度时候会具有不同方向与强度的应力。在习知技艺中，有厂商提出了穿硅通孔102周围的外围区(keepoutregion)104是应力产生最严重且最复杂的地方。外围区104大概是离穿硅通孔102以外10毫米至20毫米的地方，在这个区域中的元件会在高温与低温时遭受复杂的应力，例如从穿硅通孔102的往外辐射方向上是伸张力(tensile)而在外围区104上的环状区域则是压缩力(compressive)。这样复杂的应力系统并不适合元件的设置，且容易导致元件的损坏。However, in the existing packaging technology, the structure of using TSVs to stack packages still faces many problems. Please refer to FIG. 1 , which is a schematic diagram of a top surface of a TSV in the prior art. As shown in FIG. 1 , a known TSV 102 is disposed in the substrate 100 . However, due to the difference in coefficient of thermal expansion (CTE) between the material of the TSV 102 such as metal copper and the material of the substrate 100 such as semiconductor silicon, for example, the coefficient of thermal expansion of copper is about 17.5×10 − 6 K -1 and the thermal expansion coefficient of silicon is about 2.5×10 -6 K -1 , which will cause the substrate 300 to have stresses of different directions and intensities at different temperatures. In the prior art, some manufacturers have proposed that the peripheral region (keepout region) 104 around the TSV 102 is the place where the stress is most serious and complicated. The peripheral region 104 is about 10 mm to 20 mm away from the TSV 102 , and the components in this region will suffer complex stresses at high and low temperatures, for example, the radiation direction from the TSV 102 is Tensile and the annular region on the peripheral region 104 is compressive. Such a complicated stress system is not suitable for the arrangement of the components and can easily lead to damage of the components.
然而，在目前尺寸日益缩小的集成电路中，外围区104的存在势必会限制了半导体元件的集成化，而不利于更先进工艺的设计。因此，还需要一种新颖的半导体工艺与结构，以解决上述问题。However, in the current integrated circuits with increasingly smaller dimensions, the existence of the peripheral region 104 will inevitably limit the integration of semiconductor elements, which is not conducive to the design of more advanced processes. Therefore, a novel semiconductor process and structure is also needed to solve the above problems.
发明内容 Contents of the invention
本发明于是提供了一种具有应力保护结构的半导体结构以及其制作方法，以解决现有技术中应力的问题。The present invention therefore provides a semiconductor structure with a stress protection structure and a manufacturing method thereof, so as to solve the stress problem in the prior art.
根据本发明的一个实施方式，本发明是提供一种具有应力保护结构的半导体结构，包括有基底、应力产生元件以及应力保护装置。基底具有第一表面以及第二表面，两个相对设置。应力产生元件设置在基底中。应力保护结构，设置在基底第一表面的一侧，应力保护结构包围应力产生元件，且应力保护结构内部具有密封的空气空间。According to an embodiment of the present invention, the present invention provides a semiconductor structure with a stress protection structure, including a substrate, a stress generating element and a stress protection device. The base has a first surface and a second surface, which are opposite to each other. The stress generating element is disposed in the base. The stress protection structure is arranged on one side of the first surface of the substrate, the stress protection structure surrounds the stress generating element, and there is a sealed air space inside the stress protection structure.
根据本发明的另外一个实施方式，本发明是提供了一种形成具有应力保护结构的半导体结构的方法。首先提供基底，其具有第一表面以及第二表面，两个相对设置。接着在基底的第一表面一侧上形成连续的沟渠，沟渠包围预定区域。然后在沟渠中依次形成介电层、第一金属层以及第二金属层，以在沟渠中形成空气空间。最后，去除沟渠以外的介电层、第一金属层以及第二金属层，以形成应力保护结构。According to another embodiment of the present invention, the present invention provides a method for forming a semiconductor structure with a stress protection structure. Firstly, a base is provided, which has a first surface and a second surface, which are opposite to each other. A continuous trench is then formed on the first surface side of the substrate, the trench surrounding a predetermined area. Then a dielectric layer, a first metal layer and a second metal layer are sequentially formed in the trench to form an air space in the trench. Finally, the dielectric layer outside the trench, the first metal layer and the second metal layer are removed to form the stress protection structure.
本发明所提供的应力保护结构，其内具有空气空间，故可以提供适当的应力缓冲，以达到保护应力产生元件，例如穿硅通孔的功效。The stress protection structure provided by the present invention has an air space therein, so it can provide proper stress buffering to achieve the effect of protecting stress-generating components, such as through-silicon vias.
附图说明 Description of drawings
图1所示为所示为公知技术中穿硅通孔的顶面示意图。FIG. 1 is a schematic diagram showing the top surface of a TSV in the prior art.
图2至图8所示为本发明形成具有应力保护结构的半导体结构的步骤示意图。2 to 8 are schematic diagrams of the steps of forming the semiconductor structure with the stress protection structure according to the present invention.
图9与图10所示为本发明应力保护结构的俯视图。9 and 10 are top views of the stress protection structure of the present invention.
其中，附图标记说明如下：Wherein, the reference signs are explained as follows:
100基底314预定区域100 substrates 314 scheduled areas
102穿硅通孔316介电层102 through silicon vias 316 dielectric layer
104外围区318阻障层104 peripheral area 318 barrier layer
300基底320第一金属层300 base 320 first metal layer
302第一表面322第二金属层302 first surface 322 second metal layer
304第二表面324空气空间304 second surface 324 air space
306半导体元件326应力保护结构306 Semiconductor components 326 Stress protection structure
308掺杂井328穿硅通孔308 doped wells 328 through silicon vias
310内层介电层330第三表面310 inner dielectric layer 330 third surface
312沟渠312 ditch
具体实施方式 detailed description
为使本发明所属技术领域的技术人员能进一步了解本发明，以下的说明举出了本发明几个优选实施方式，并配合附图与说明，以详细说明本发明的内容及所欲实现的效果。In order to enable those skilled in the art of the present invention to further understand the present invention, the following description lists several preferred embodiments of the present invention, together with the accompanying drawings and descriptions, to describe in detail the content of the present invention and the desired effect .
为了克服上述在穿硅通孔附近复杂应力的问题，本发明是在穿硅通孔的周围形成了一应力保护结构，其内具有密封的空气空间，并包围在穿硅通孔的周围。请参考图2至图8，所示为本发明形成具有应力保护结构的半导体结构的步骤示意图。如图2所示，首先提供一基底300，例如是硅基底(siliconsubstrate)、外延硅基底(epitaxialsiliconsubstrate)、硅锗半导体基底(silicongermaniumsubstrate)、碳化硅基底(siliconcarbidesubstrate)或硅覆绝缘(silicon-on-insulator，SOI)。基底300具有一第一表面302以及一第二表面304。于本发明优选实施例中，第一表面302例如是基底300的有源面(activesurface)，而第二表面304例如是基底300的背面(backsurface)。基底300厚度大体上为700至1000微米(micrometer)，但并不以此为限。接着，在基底300的第一表面302上通过各种半导体工艺来形成半导体元件306，其可以是金氧半导体晶体管(metaloxidesemiconductortransistor，MOStransistor)或是动态随机存储器(DRAM)等结构。优选来说，半导体元件306会具有一掺质井(dopingwell)308，例如是N型掺质井或是P型掺质井。接着，在完成了半导体元件306后，接着在基底300的第一表面302上形成一内层介电层(interlayerdielectric，ILD)310覆盖在半导体元件306上，其材料例如是二氧化硅。接着可以在内层介电层310中形成插拴与欧姆接触(Ohmcontact)(图未示)，以电性连接半导体元件306。In order to overcome the above-mentioned complex stress problem near the TSV, the present invention forms a stress protection structure around the TSV, which has a sealed air space and surrounds the TSV. Please refer to FIG. 2 to FIG. 8 , which are schematic diagrams showing steps of forming a semiconductor structure with a stress protection structure according to the present invention. As shown in FIG. 2, a substrate 300 is first provided, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium semiconductor substrate, a silicon carbide substrate, or a silicon-on-insulator substrate. insulator, SOI). The substrate 300 has a first surface 302 and a second surface 304 . In a preferred embodiment of the present invention, the first surface 302 is, for example, the active surface of the substrate 300 , and the second surface 304 is, for example, the back surface of the substrate 300 . The thickness of the substrate 300 is generally 700 to 1000 micrometers (micrometer), but not limited thereto. Next, a semiconductor element 306 is formed on the first surface 302 of the substrate 300 through various semiconductor processes, which may be a metal oxide semiconductor transistor (MOS transistor) or a dynamic random access memory (DRAM) structure. Preferably, the semiconductor device 306 has a doping well 308 , such as an N-type doping well or a P-type doping well. Next, after the semiconductor device 306 is completed, an interlayer dielectric layer (interlayer dielectric, ILD) 310 is formed on the first surface 302 of the substrate 300 to cover the semiconductor device 306 , and its material is, for example, silicon dioxide. Then, a plug and an Ohm contact (not shown) may be formed in the ILD layer 310 to electrically connect the semiconductor device 306 .
如图3所示，接着在内层介电层310以及基底300中形成一沟渠312，其中沟渠312会连续且包围一预定区域314。形成沟渠312的方法例如是通过光刻以及干蚀刻工艺来形成，且干蚀刻工艺会蚀刻内层介电层310并进一步蚀刻至基底300。于本发明的优选实施例中，沟渠312的宽度大体上是0.4微米至1微米，且深度会深于半导体元件306中掺杂井308的深度，例如比掺杂井308深(若有数据请发明人可以提供)微米。As shown in FIG. 3 , a trench 312 is then formed in the ILD layer 310 and the substrate 300 , wherein the trench 312 is continuous and surrounds a predetermined region 314 . The method of forming the trench 312 is, for example, formed by photolithography and dry etching process, and the dry etching process will etch the ILD layer 310 and further etch to the substrate 300 . In a preferred embodiment of the present invention, the width of the trench 312 is generally 0.4 micron to 1 micron, and the depth will be deeper than the depth of the doping well 308 in the semiconductor device 306, for example, deeper than the doping well 308 (if available, please refer to Inventors can provide) microns.
如图4所示，在沟渠312的表面上形成一介电层316，但介电层316并不会填满沟渠312。形成介电层316的方法可以通过化学气相沉积(chemicalvapordeposition，CVD)，例如是原子层沉积(AtomicLayerDeposition，ALD)工艺。所形成的介电层316的厚度大约在500埃至750埃之间。As shown in FIG. 4 , a dielectric layer 316 is formed on the surface of the trench 312 , but the dielectric layer 316 does not fill the trench 312 . The method of forming the dielectric layer 316 can be chemical vapor deposition (chemical vapor deposition, CVD), such as atomic layer deposition (Atomic Layer Deposition, ALD) process. The thickness of the formed dielectric layer 316 is approximately between 500 angstroms and 750 angstroms.
如图5所示，在沟渠312的表面上形成一选择性的阻障层320以及一第一金属层318，其中阻障层320以及第一金属层318并不会填满沟渠312。形成阻障层320以及第一金属层318的方法可以通过化学气相沉积工艺。阻障层320的材质例如是钛/氮化钛(Ti/TiN)，而第一金属层318的材质例如是金属钨(W)，且第一金属层318厚度大约在500埃至1000埃。As shown in FIG. 5 , a selective barrier layer 320 and a first metal layer 318 are formed on the surface of the trench 312 , wherein the barrier layer 320 and the first metal layer 318 do not fill the trench 312 . The method of forming the barrier layer 320 and the first metal layer 318 may be through a chemical vapor deposition process. The material of the barrier layer 320 is, for example, titanium/titanium nitride (Ti/TiN), and the material of the first metal layer 318 is, for example, tungsten (W), and the thickness of the first metal layer 318 is about 500 angstroms to 1000 angstroms.
如图6所示，利用另外一个沉积工艺在基底300上形成第二金属层322。于本发明优选实施例中，此沉积工艺是物理气相沉积工艺(physicalvapordeposition，PVD)，例如是溅射(sputtering)工艺。而第二金属层322优选的材质是和第一金属层318相同，例如都是金属钨。如此一来，若适当的调整第二金属层322形成的厚度，就可以使得沟渠312的上部被第二金属层322封住，但是会在沟渠312的内部形成一空气空间(void)324。于本发明优选的实施例中，空气空间324占据大部分沟渠316的位置，且其底部的深度也会深于掺杂井308的深度。As shown in FIG. 6 , another deposition process is used to form a second metal layer 322 on the substrate 300 . In a preferred embodiment of the present invention, the deposition process is a physical vapor deposition process (physical vapor deposition, PVD), such as a sputtering (sputtering) process. The preferred material of the second metal layer 322 is the same as that of the first metal layer 318 , such as tungsten. In this way, if the thickness of the second metal layer 322 is properly adjusted, the upper part of the trench 312 can be sealed by the second metal layer 322 , but a void 324 will be formed inside the trench 312 . In a preferred embodiment of the present invention, the air space 324 occupies most of the position of the trench 316 , and the depth of the bottom thereof is also deeper than that of the doping well 308 .
如图7所示，进行一平坦化工艺，例如是化学机械抛光(chemicalmechanicalpolish，CMP)工艺或是回蚀刻工艺，或是上述的组合，以移除沟渠312以外的第二金属层322、第一金属层318以及阻障层320。如此一来，即完成本发明的应力保护结构326，其中应力保护结构326会包围预定区域314。As shown in FIG. 7 , a planarization process, such as a chemical mechanical polish (CMP) process or an etch-back process, or a combination thereof, is performed to remove the second metal layer 322 outside the trench 312, the first Metal layer 318 and barrier layer 320 . In this way, the stress protection structure 326 of the present invention is completed, wherein the stress protection structure 326 surrounds the predetermined region 314 .
如图8所示，后续可在应力保护结构326所包围的预定区域314中形成一半导体结构例如是穿硅通孔328。形成穿硅通孔328的步骤例如是从基板300的第一表面302上行成一沟渠后，再将沟渠依次填入适当的绝缘材质以及导电材质，优选来说，还可以进一步从基底300的第二表面304进行一薄化工艺，使得第二表面304变成第三表面330，以暴露出导电材质，以形成所述的穿硅通孔328。As shown in FIG. 8 , a semiconductor structure such as a TSV 328 may be subsequently formed in the predetermined region 314 surrounded by the stress protection structure 326 . The step of forming the TSV 328 is, for example, to form a trench from the first surface 302 of the substrate 300, and then fill the trench with appropriate insulating material and conductive material in sequence. A thinning process is performed on the surface 304 so that the second surface 304 becomes the third surface 330 to expose the conductive material to form the TSV 328 .
值得注意的是，形成应力保护结构326与穿硅通孔328的顺序可以调整，例如先形成穿硅通孔328后，再形成应力保护结构326。或者先进行形成穿硅通孔328的部份制作工艺后，再形成应力保护结构326，最后再进行部份制作工艺以完全形成穿硅通孔328。此外，本发明应力保护结构326能够提供应力保护的，不仅仅是针对穿硅通孔328，也可能是其他容易产生应力的装置。It should be noted that the order of forming the stress protection structure 326 and the TSV 328 can be adjusted, for example, the TSV 328 is formed first, and then the stress protection structure 326 is formed. Alternatively, a part of the manufacturing process for forming the TSV 328 is performed first, and then the stress protection structure 326 is formed, and finally a part of the manufacturing process is performed to completely form the TSV 328 . In addition, the stress protection structure 326 of the present invention can provide stress protection not only for the TSV 328 , but also for other devices prone to stress.
而于另外一个实施例中，在形成前述应力保护结构326的阻障层320与第一金属层318或第二金属层322的步骤时，也可以和形成半导体元件306中的欧姆接触(图未示)等结构一起形成，以节省制作工艺的时间以及成本。In another embodiment, when forming the barrier layer 320 and the first metal layer 318 or the second metal layer 322 of the aforementioned stress protection structure 326, the ohmic contact (not shown in the figure) in the semiconductor element 306 may also be formed. Shown) and other structures are formed together to save the time and cost of the manufacturing process.
如图8所示，本发明提供了一种具有应力保护装置的半导体结构，包含基底300、内层介电层310、穿硅通孔328以及应力保护结构326。基底300具有第一表面302以及第三表面330，两者相对设置。穿硅通孔328设置在基底300中并且贯穿第一表面302以及第三表面330。应力保护结构326设置在基底300以及内层介电层310中，其由外而内依次包含介电层316、第一金属层320以及密封的空气空间324。此外，应力保护结构326中空气空间324上部为第二金属层322，于一个实施例中，第一金属层320以及第二金属层322具有相同材质。由于应力保护结构326中具有空气空间324，其热膨胀系数相对于其他材质来的小，故能够提供适当的缓冲容量，针对穿硅通孔328邻近的地方例如半导体元件306，可以提供应力保护的功效。于一个实施例中，应力保护结构326的深度会大于半导体元件306中掺杂井308的深度。于一个实施方式中，应力保护结构326是连续的环型结构，其可以为各种几何形状。请参考图9与图10，所示为本发明应力保护结构的俯视图。如图9所示，应力保护结构326可以是圆形的，或者，如图10所示，应力保护结构326也可以是方形的。As shown in FIG. 8 , the present invention provides a semiconductor structure with a stress protection device, including a substrate 300 , an ILD layer 310 , a TSV 328 and a stress protection structure 326 . The base 300 has a first surface 302 and a third surface 330 disposed opposite to each other. The TSV 328 is disposed in the substrate 300 and passes through the first surface 302 and the third surface 330 . The stress protection structure 326 is disposed in the substrate 300 and the inner dielectric layer 310 , and it includes the dielectric layer 316 , the first metal layer 320 and the sealed air space 324 sequentially from outside to inside. In addition, the upper part of the air space 324 in the stress protection structure 326 is the second metal layer 322 . In one embodiment, the first metal layer 320 and the second metal layer 322 have the same material. Due to the air space 324 in the stress protection structure 326, its thermal expansion coefficient is smaller than other materials, so it can provide an appropriate buffer capacity, and it can provide stress protection for places adjacent to the TSV 328 such as the semiconductor element 306 . In one embodiment, the depth of the stress protection structure 326 is greater than the depth of the doping well 308 in the semiconductor device 306 . In one embodiment, the stress protection structure 326 is a continuous ring structure, which can have various geometric shapes. Please refer to FIG. 9 and FIG. 10 , which are top views of the stress protection structure of the present invention. As shown in FIG. 9, the stress protection structure 326 may be circular, or, as shown in FIG. 10, the stress protection structure 326 may also be square.
综上所述，本发明所提供的应力保护结构，其内具有空气空间，故可以提供适当的应力缓冲，以达到保护应力产生元件，例如穿硅通孔的功效。To sum up, the stress protection structure provided by the present invention has an air space therein, so it can provide proper stress buffering to achieve the effect of protecting stress-generating components, such as TSVs.
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.
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| CN102222654A (en) * | 2010-04-16 | 2011-10-19 | 南亚科技股份有限公司 | Semiconductor element with through hole on substrate and manufacturing method thereof |
| CN102412197A (en) * | 2010-09-22 | 2012-04-11 | 新科金朋有限公司 | Semiconductor device and method of forming conductive tsv with insulating annular ring |
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| CN102222654A (en) * | 2010-04-16 | 2011-10-19 | 南亚科技股份有限公司 | Semiconductor element with through hole on substrate and manufacturing method thereof |
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