CN116581154B - Process method of SGT device and SGT device - Google Patents

Abstract

The invention provides a process method of an SGT device and the SGT device, the process method comprises the steps of providing an N-type epitaxial substrate, etching a first groove on the N-type epitaxial substrate, growing a first oxide layer on the inner wall of the first groove in a thermal oxidation mode, filling N-type doped polysilicon, grinding and etching back to form a shielding gate in the first groove by adopting a CMP technology, etching the first oxide layer on the inner wall of the first groove to a preset depth by adopting a wet etching technology, growing a second oxide layer with a preset thickness on the inner wall of the second groove by adopting a thermal oxidation mode, sequentially depositing P-type doped polysilicon and N-type doped polysilicon in the second groove, grinding and flattening by adopting a CMP technology, and finally carrying out high-temperature annealing after well doping to obtain the SGT device with high breakdown voltage.

Description

Process method of SGT device and SGT device

Technical field

The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a process method of an SGT device and an SGT device.

Background technique

MOSFET can be roughly divided into the following categories: planar MOSFET; Trench (trench) MOSFET, mainly used in low-voltage fields; SGT (Shielded Gate Transistor, shielded gate trench) MOSFET, mainly used in medium-voltage and low-voltage fields; SJ - (Superjunction) MOSFET, mainly used in high voltage fields.

Among them, the SGT MOSFET structure has a charge coupling effect, which introduces horizontal depletion on the basis of the vertical depletion of the PN junction of traditional trench MOSFET devices. When using the same doping concentration of epitaxial material specifications, the device can obtain higher breakdown voltage. The deeper trench depth can use more silicon volume to absorb EAS (Energy Avalanche Stress, avalanche energy test) energy, so SGT can do better during avalanches and be better able to withstand avalanche breakdown and surge current. In application fields such as switching power supplies, motor control, and power battery systems, SGT MOSFETs combined with advanced packaging are very helpful in improving system performance and power density.

In the conventional process, SGT is formed by digging a trench on the epitaxial substrate, first forming a sidewall oxide layer through thermal oxygen, then filling the trench with polysilicon, etching the polysilicon downward to form a shielding gate, and then using wet The oxide layer on the sidewall is removed by etching, and then the gate oxide is generated through oxidation and then filled with polysilicon to form the gate. The peak of the SGT electric field intensity obtained by this process is in the well area and forms a PN junction with EPI (silicon grown by epitaxial technology). with the bottom of the trench.

The withstand voltage of SGT can be characterized by the integrated area of the electric field intensity curve along the trench direction. The larger the integrated area, the higher the withstand voltage. Although the traditional SGT introduces horizontal depletion, the peak of the electric field intensity is at the PN junction formed by the well region and EPI and the bottom of the trench. The electric field intensity distribution is "M" shaped, with a depression in the middle part, which limits the withstand voltage capability. limit.

Contents of the invention

Based on this, the purpose of the present invention is to provide a process method for an SGT device and an SGT device, aiming to solve the problem in the prior art that the peak of the electric field intensity is at the PN junction formed by the well region and EPI and the bottom of the trench, and the electric field intensity distribution is It is "M" shaped and has a dent in the middle, which limits the pressure resistance.

According to a processing method of an SGT device in an embodiment of the present invention, the processing method includes:

Provide an N-type epitaxial substrate, and perform etching on the N-type epitaxial substrate to obtain an N-type epitaxial substrate with a first trench;

Grow a first oxide layer on the inner wall of the first trench through thermal oxidation;

Filling the first trench with the first oxide layer with N-type doped polysilicon, grinding it down using CMP technology and then etching back to form a shield gate in the first trench;

Using wet etching technology, the first oxide layer on the inner wall of the first trench is etched to a predetermined depth to form a second trench for subsequent filling of P-type doped polysilicon;

By thermal oxidation, a second oxide layer with a predetermined thickness is grown on the inner wall of the second trench;

Deposit P-type doped polysilicon and N-type doped polysilicon sequentially into the second trench, and polish them using CMP technology;

After well doping, high-temperature annealing is performed to obtain SGT devices with high breakdown voltage.

Further, the depth of the first groove is 5.5 μm~6.5 μm.

Further, in the step of growing the first oxide layer on the inner wall of the first trench by thermal oxidation, oxygen is introduced at a temperature of 800°C to 1100°C to grow the first oxide layer with a thickness of 5600Å to 6500Å. oxide layer.

Further, the first trench with the first oxide layer is filled with N-type doped polysilicon, and is polished using CMP technology and then etched back to form a shield gate in the first trench. In the step, the distance between the surface of the shielding grid and the surface of the N-type epitaxial substrate is 1.3 μm~1.7 μm.

Further, in the step of using wet etching technology to etch the first oxide layer on the inner wall of the first trench to a preset depth, the preset depth is 2.5 μm ~ 3.5 μm.

Further, in the step of growing a second oxide layer with a predetermined thickness on the inner wall of the second trench by thermal oxidation, the thickness of the second oxide layer is 400Å~600Å.

Further, in the step of sequentially depositing P-type doped polysilicon and N-type doped polysilicon in the second trench and polishing them using CMP technology, the P-type doped polysilicon is doped Boron-containing polysilicon, in which the doping concentration of boron is 10 ¹⁷ atoms/cm ³ ~10 ²¹ atoms/cm ³ .

Further, in the step of sequentially depositing P-type doped polysilicon and N-type doped polysilicon in the second trench and polishing them using CMP technology, the N-type doped polysilicon deposited The thickness is 1.2μm~1.4μm.

Further, after the well is doped, high-temperature annealing is performed to obtain an SGT device with high breakdown voltage. The annealing temperature is 800°C to 1000°C.

According to an SGT device in an embodiment of the present invention, it is manufactured by the above-mentioned process method of an SGT device.

Compared with the prior art: the present invention provides a process method for an SGT device and an SGT device. The method provides an N-type epitaxial substrate and etches a first trench on the N-type epitaxial substrate. Through thermal oxidation, the first oxide layer is grown on the inner wall of the first trench, and then filled with N-type doped polysilicon, and polished using CMP technology and then etched back to form a shield gate in the first trench. Using method etching technology, the first oxide layer on the inner wall of the first trench is etched to a preset depth, and then a second oxide layer of a predetermined thickness is grown on the inner wall of the second trench through thermal oxidation, and the P-type doping is Polysilicon and N-type doped polysilicon are sequentially deposited in the second trench and polished using CMP technology. Finally, after well doping, high-temperature annealing is performed to obtain an SGT device with high breakdown voltage. Specifically, By forming the second trench and enhancing the depletion of the mesa (substrate next to the trench) on the side of the middle position of the second trench, the PN junction formed between the well region and the N-type epitaxial substrate and the two positions at the bottom of the trench An additional electric field intensity peak is added in the middle to increase the integrated area of the electric field intensity curve along the trench direction, thereby achieving the effect of increasing the SGT breakdown voltage.

Description of the drawings

Figure 1 is an implementation flow chart of a process method for an SGT device provided by an embodiment of the present invention;

Figure 2 is a schematic diagram of the preparation process of an SGT device provided by an embodiment of the present invention;

Figure 3 is a schematic diagram of the SGT electric field intensity distribution curve.

Detailed ways

In order to facilitate understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the invention are shown in the drawings. However, the invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It should be noted that when an element is referred to as being "mounted" on another element, it can be directly on the other element or intervening elements may also be present. When an element is said to be "connected" to another element, it can be directly connected to the other element or there may also be intervening elements present. The terms "vertical," "horizontal," "left," "right" and similar expressions are used herein for illustrative purposes only.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which the invention belongs. The terminology used herein in the description of the invention is for the purpose of describing specific embodiments only and is not intended to limit the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Referring to Figures 1 and 2, Figure 1 is an implementation flow chart of a process method for an SGT device provided by an embodiment of the present invention. Figure 2 is a schematic diagram of the preparation process of an SGT device provided by an embodiment of the present invention. The process method is specifically Includes the following steps:

S100: Provide an N-type epitaxial substrate, and perform etching on the N-type epitaxial substrate to obtain an N-type epitaxial substrate with a first trench;

Specifically, the N-type epitaxial substrate 1 can be a silicon substrate. First, a first trench is etched on the N-type epitaxial substrate 1 , where the depth of the first trench is 5.5 μm ~ 6.5 μm.

S200: Grow the first oxide layer on the inner wall of the first trench through thermal oxidation;

Specifically, after the etching of the first trench is completed, oxygen is introduced at a temperature of 800°C to 1100°C, and a first oxide layer 2 with a thickness of 5600Å to 6500Å is grown to cover the surface of the first trench. It should be noted that a high-quality oxide layer is generated by thermal oxygen as an effective isolation between the subsequent shield gate and the N-type epitaxial substrate 1. If the thickness is too thin, the isolation effect will be poor. If it is too thick, the isolation effect will be poor. During the subsequent filling of polysilicon, gaps will be generated in the middle, which will affect the quality of the SGT device.

S300: Fill the first trench with the first oxide layer with N-type doped polysilicon, grind it down using CMP technology and then etch back to form a shield gate in the first trench;

Specifically, the first trench is first filled with N-type doped polysilicon 3, then polished using CMP (Chemical Mechanical Planarization, chemical mechanical polishing) technology and then etched back to control the surface of the shield gate and the surface of the N-type epitaxial substrate 1 The distance is 1.3μm~1.7μm, in which the shielding grid can be used as a horizontally depleted field plate.

S400: Use wet etching technology to etch the first oxide layer on the inner wall of the first trench to a preset depth to form a second trench for subsequent filling of P-type doped polysilicon;

Specifically, the first oxide layer 2 on the inner wall of the first trench is etched by 2.5 μm to 3.5 μm to form a second trench for subsequent filling of P-type doped polysilicon 4. It should be noted that the second trench The bottom of the groove is located in the middle area in the depth direction of the first groove.

S500: Grow a second oxide layer with a predetermined thickness on the inner wall of the second trench through thermal oxidation;

Specifically, the second oxide layer (not shown) is the gate oxide layer, with a thickness of 400Å~600Å.

S600: Deposit P-type doped polysilicon and N-type doped polysilicon in the second trench in sequence, and polish them using CMP technology;

Specifically, P-type doped polysilicon 4 is first deposited, wherein the P-type doped polysilicon 4 is boron-doped polysilicon, and the boron doping concentration is 10 ¹⁷ atoms/cm ³ ~10 ²¹ atoms/cm ³ . P-type doped polysilicon 4 is used as a diffusion source for subsequent impurities. It diffuses through the gate oxide layer on its sidewall, that is, the second oxide layer, into the adjacent EPI (epitaxially grown silicon) substrate, that is, N-type After the epitaxial substrate 1 is etched back, N-type doped polysilicon 5 of 1.2 μm to 1.4 μm is deposited on top to form a gate electrode, and then polished using CMP technology.

S700: After well doping, high temperature annealing is performed to obtain SGT devices with high breakdown voltage.

Specifically, after the well is doped, it is annealed at a temperature of 800°C to 1000°C. At this time, the boron in the previously deposited P-type doped polysilicon will diffuse through the gate oxide layer on the sidewall to the N-type epitaxial lining next to it. In the bottom, A in Figure 2 represents the diffusion area, which forms a PN junction, enhances the depletion in the middle area of the SGT trench, and increases the breakdown voltage of the SGT device.

It should be noted that in the existing "hat-shaped" top-bottom structure SGT process, since the etching of the oxide layer is wet etching, when the sidewall oxide layer is etched, the oxide layers on the left and right sides of the top of the shield gate will also be etched. Etching will naturally form two grooves. After the subsequent gate POLY is filled in, a "hat-shaped" gate will be formed to surround the top of the shielding grid.

This technical solution is based on the original process, using the unique polysilicon gates on the left and right sides of the "hat-shaped" SGT, and changing the polysilicon doping type on both sides of the shield gate to change the original N-type polysilicon into a double-layer P-type polysilicon plus N-type polysilicon. The specific method is: after digging the trench on the N-type epitaxial substrate, generate a sidewall oxide layer through thermal oxidation, and then fill it with polysilicon to form the shield gate. After CMP grinding, etch back to a certain depth, and then perform the sidewall oxide layer first. Etching creates grooves on the shield gate, and then oxidizes to form a gate oxide layer. Next, P-type doped polysilicon is deposited, and then etched back to a certain depth, and a polysilicon gate is deposited. After subsequent well and source doping annealing, the P-type impurity boron in the groove will diffuse to the mesa on the side through the oxide layer. Inside, a PN junction is formed with the N-type epitaxial substrate, which enhances depletion in the horizontal direction.

This will add an electric field intensity peak between the PN junction formed by the well region and the N-type epitaxial substrate and the bottom of the trench, increasing the integral area of the electric field intensity curve, thereby increasing the breakdown voltage.

Please refer to Figure 3, which is a schematic diagram of the SGT electric field intensity distribution curve. In the area A where boron is diffused in the middle area of the trench, the electric field intensity becomes higher due to enhanced depletion. Compared with the prior art, the integrated area of the curve becomes larger, the breakdown voltage becomes higher.

The present invention will be further described below with specific examples:

Example 1

This embodiment provides a process method for an SGT device, including the following steps:

(1) Provide an N-type epitaxial substrate, wherein the N-type epitaxial substrate is a silicon substrate, and etching is performed on the N-type epitaxial substrate to obtain an N-type epitaxial substrate with a first trench depth of 5.5 μm. ;

(2) Through thermal oxidation, oxygen is introduced at a temperature of 800°C to grow a first oxide layer with a thickness of 5600Å;

(3) Fill the first trench with the first oxide layer with N-type doped polysilicon, grind it down using CMP technology and then engrav it back to form a shield gate in the first trench, where the surface of the shield gate is controlled The distance from the N-type epitaxial substrate surface is 1.3μm;

(4) Use wet etching technology to etch 2.5 μm of the first oxide layer on the inner wall of the first trench to form a second trench for subsequent filling of P-type doped polysilicon;

(5) Through thermal oxidation, a second oxide layer with a thickness of 400Å is grown on the inner wall of the second trench;

(6) P-type doped polysilicon and N-type doped polysilicon are deposited in the second trench in sequence, and polished using CMP technology. Among them, P-type doped polysilicon is boron-doped polysilicon, and boron is The doping concentration is 10 ¹⁷ atoms/cm ³ , P-type doped polysilicon is etched back and 1.2μm polysilicon is deposited on top to form the gate;

(7) After well doping, annealing is performed at a temperature of 800°C to obtain an SGT device with high breakdown voltage.

Example 2

This embodiment provides a process method for an SGT device, including the following steps:

(1) Provide an N-type epitaxial substrate, wherein the N-type epitaxial substrate is a silicon substrate, and etching is performed on the N-type epitaxial substrate to obtain an N-type epitaxial substrate with a first trench depth of 5.5 μm. ;

(2) Through thermal oxidation, oxygen is introduced at a temperature of 800°C to grow a first oxide layer with a thickness of 5600Å;

(3) Fill the first trench with the first oxide layer with N-type doped polysilicon, grind it down using CMP technology and then engrav it back to form a shield gate in the first trench, where the surface of the shield gate is controlled The distance from the N-type epitaxial substrate surface is 1.3μm;

(4) Use wet etching technology to etch 3 μm of the first oxide layer on the inner wall of the first trench to form a second trench for subsequent filling of P-type doped polysilicon;

(5) Through thermal oxidation, a second oxide layer with a thickness of 400Å is grown on the inner wall of the second trench;

(6) P-type doped polysilicon and N-type doped polysilicon are deposited in the second trench in sequence, and polished using CMP technology. Among them, P-type doped polysilicon is boron-doped polysilicon, and boron is The doping concentration is 10 ¹⁷ atoms/cm ³ , P-type doped polysilicon is etched back and 1.2μm polysilicon is deposited on top to form the gate;

(7) After well doping, annealing is performed at a temperature of 800°C to obtain an SGT device with high breakdown voltage.

Example 3

This embodiment provides a process method for an SGT device, including the following steps:

(1) Provide an N-type epitaxial substrate, wherein the N-type epitaxial substrate is a silicon substrate, and etching is performed on the N-type epitaxial substrate to obtain an N-type epitaxial substrate with a first trench depth of 5.5 μm. ;

(2) Through thermal oxidation, oxygen is introduced at a temperature of 800°C to grow a first oxide layer with a thickness of 5600Å;

(3) Fill the first trench with the first oxide layer with N-type doped polysilicon, grind it down using CMP technology and then engrav it back to form a shield gate in the first trench, where the surface of the shield gate is controlled The distance from the N-type epitaxial substrate surface is 1.3μm;

(4) Use wet etching technology to etch 3.5 μm of the first oxide layer on the inner wall of the first trench to form a second trench for subsequent filling of P-type doped polysilicon;

(5) Through thermal oxidation, a second oxide layer with a thickness of 400Å is grown on the inner wall of the second trench;

(6) P-type doped polysilicon and N-type doped polysilicon are deposited in the second trench in sequence, and polished using CMP technology. Among them, P-type doped polysilicon is boron-doped polysilicon, and boron is The doping concentration is 10 ¹⁷ atoms/cm ³ , P-type doped polysilicon is etched back and 1.2μm polysilicon is deposited on top to form the gate;

(7) After well doping, annealing is performed at a temperature of 800°C to obtain an SGT device with high breakdown voltage.

Example 4

This embodiment provides a process method for an SGT device, including the following steps:

(1) Provide an N-type epitaxial substrate, wherein the N-type epitaxial substrate is a silicon substrate, and etching is performed on the N-type epitaxial substrate to obtain an N-type epitaxial substrate with a first trench depth of 6 μm;

(2) Through thermal oxidation, oxygen is introduced at a temperature of 900°C to grow a first oxide layer with a thickness of 5900Å;

(3) Fill the first trench with the first oxide layer with N-type doped polysilicon, grind it down using CMP technology and then engrav it back to form a shield gate in the first trench, where the surface of the shield gate is controlled The distance from the N-type epitaxial substrate surface is 1.5μm;

(4) Use wet etching technology to etch 3 μm of the first oxide layer on the inner wall of the first trench to form a second trench for subsequent filling of P-type doped polysilicon;

(5) Use thermal oxidation to grow a second oxide layer with a thickness of 500Å on the inner wall of the second trench;

(6) P-type doped polysilicon and N-type doped polysilicon are deposited in the second trench in sequence, and polished using CMP technology. Among them, P-type doped polysilicon is boron-doped polysilicon, and boron is The doping concentration is 10 ¹⁸ atoms/cm ³ . After the P-type doped polysilicon is etched back, 1.3μm polysilicon is deposited on top to form the gate;

(7) After well doping, annealing is performed at a temperature of 900°C to obtain an SGT device with high breakdown voltage.

Example 5

This embodiment provides a process method for an SGT device, including the following steps:

(1) Provide an N-type epitaxial substrate, wherein the N-type epitaxial substrate is a silicon substrate, and etching is performed on the N-type epitaxial substrate to obtain an N-type epitaxial substrate with a first trench depth of 6.5 μm. ;

(2) Through thermal oxidation, oxygen is introduced at a temperature of 1000°C to grow a first oxide layer with a thickness of 6200Å;

(3) Fill the first trench with the first oxide layer with N-type doped polysilicon, grind it down using CMP technology and then engrav it back to form a shield gate in the first trench, where the surface of the shield gate is controlled The distance from the N-type epitaxial substrate surface is 1.7μm;

(4) Use wet etching technology to etch 3 μm of the first oxide layer on the inner wall of the first trench to form a second trench for subsequent filling of P-type doped polysilicon;

(5) Through thermal oxidation, a second oxide layer with a thickness of 600Å is grown on the inner wall of the second trench;

(6) P-type doped polysilicon and N-type doped polysilicon are deposited in the second trench in sequence, and polished using CMP technology. Among them, P-type doped polysilicon is boron-doped polysilicon, and boron is The doping concentration is 10 ¹⁹ atoms/cm ³ . After the P-type doped polysilicon is etched back, 1.4μm polysilicon is deposited on top to form the gate;

(7) After well doping, annealing is performed at a temperature of 1000°C to obtain an SGT device with high breakdown voltage.

Example 6

This embodiment provides a process method for an SGT device, including the following steps:

(1) Provide an N-type epitaxial substrate, wherein the N-type epitaxial substrate is a silicon substrate, and etching is performed on the N-type epitaxial substrate to obtain an N-type epitaxial substrate with a first trench depth of 5.5 μm. ;

(2) Through thermal oxidation, oxygen is introduced at a temperature of 800°C to grow a first oxide layer with a thickness of 5600Å;

(3) Fill the first trench with the first oxide layer with N-type doped polysilicon, grind it down using CMP technology and then engrav it back to form a shield gate in the first trench, where the surface of the shield gate is controlled The distance from the N-type epitaxial substrate surface is 1.3μm;

(4) Use wet etching technology to etch 3 μm of the first oxide layer on the inner wall of the first trench to form a second trench for subsequent filling of P-type doped polysilicon;

(5) Through thermal oxidation, a second oxide layer with a thickness of 400Å is grown on the inner wall of the second trench;

(6) P-type doped polysilicon and N-type doped polysilicon are deposited in the second trench in sequence, and polished using CMP technology. Among them, P-type doped polysilicon is boron-doped polysilicon, and boron is The doping concentration is 10 ²¹ atoms/cm ³ . After the P-type doped polysilicon is etched back, 1.2μm polysilicon is deposited on top to form the gate;

(7) After well doping, annealing is performed at a temperature of 800°C to obtain an SGT device with high breakdown voltage.

Comparative example 1

This comparative example provides an SGT device prepared through a traditional process, that is, after digging a trench on the epitaxial substrate, first forming a sidewall oxide layer through thermal oxygen, then filling the trench with polysilicon, and etching the polysilicon downward to form Shield the gate, then use wet etching to remove the oxide layer on the sidewalls, generate gate oxide through oxidation, and then fill it with POLY (polysilicon) to form the gate electrode.

Comparative example 2

This comparative example provides a process method for an SGT device. The difference from Embodiment 1 is that in step (4), wet etching technology is used to etch the first oxide layer on the inner wall of the first trench by 2 μm to form A second trench for subsequent filling of P-type doped polysilicon.

The SGT devices prepared from Examples 1 to 6, Comparative Example 1 and Comparative Example 2 were subjected to a breakdown voltage test of 100V. The specific results are as follows:

It can be seen from the table that the breakdown voltage of the SGT device prepared by the method in the embodiment of the present invention is significantly improved, and the highest breakdown voltage can reach 114V, while the SGT device prepared in Comparative Example 1 and Comparative Example 2 The breakdown voltages are only 110V and 106V respectively. Specifically, it can be seen from Example 1 to Example 2 that the breakdown voltage when the first oxide layer is etched to a depth of 3 μm is higher than the first oxide layer when the etching depth is 2.5 μm. When the etching depth of the first oxide layer exceeds 3 μm, the breakdown voltage is not further improved. Combined with Comparative Example 2, when the etching depth of the first oxide layer is less than 2.5 μm, Breakdown voltage drops. In Comparative Example 1, when only N-type doped polysilicon is deposited in the second trench and P-type doped polysilicon is not filled, the breakdown voltage of the SGT device is slightly better than that in Comparative Example 1. In addition, in Embodiment 6, when other conditions remain unchanged, when the doping concentration of boron is too high, the breakdown voltage of the SGT device will actually decrease.

An embodiment of the present invention also provides an SGT device, which is prepared by the above-mentioned process method of an SGT device.

In summary, the embodiments of the present invention provide a process method for an SGT device and an SGT device. The method provides an N-type epitaxial substrate, etches a first trench on the N-type epitaxial substrate, and then heats the SGT device. In the oxidation method, the first oxide layer is grown on the inner wall of the first trench, then filled with N-type doped polysilicon, and polished using CMP technology and then etched back to form a shield gate in the first trench, using wet etching. Using etching technology, the first oxide layer on the inner wall of the first trench is etched to a predetermined depth, and then a second oxide layer of a predetermined thickness is grown on the inner wall of the second trench through thermal oxidation, and the P-type doped polysilicon is and N-type doped polysilicon are sequentially deposited in the second trench and polished using CMP technology. Finally, after well doping, high-temperature annealing is performed to obtain an SGT device with high breakdown voltage. Specifically, by forming The second trench, and enhances the depletion of the mesa (substrate next to the trench) on the side of the middle position of the second trench, and then re-opens the second trench between the PN junction formed by the well region and the N-type epitaxial substrate and the bottom of the trench. Add an electric field intensity peak to increase the integrated area of the electric field intensity curve along the trench direction, thereby achieving the effect of increasing the SGT breakdown voltage.

The above-mentioned embodiments only express several implementation modes of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the patent scope of the present invention. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the scope of protection of the patent of the present invention should be determined by the appended claims.

Claims (8)

1. A process method for SGT devices, characterized in that the process method includes: Provide an N-type epitaxial substrate, and perform etching on the N-type epitaxial substrate to obtain an N-type epitaxial substrate with a first trench; Grow a first oxide layer on the inner wall of the first trench through thermal oxidation; The first trench with the first oxide layer is filled with N-type doped polysilicon, and is polished using CMP technology and then etched back to form a shield gate in the first trench, wherein the shield The distance between the gate surface and the N-type epitaxial substrate surface is 1.3μm~1.7μm; Wet etching technology is used to etch the first oxide layer on the inner wall of the first trench to a preset depth to form a second trench for subsequent filling of P-type doped polysilicon, wherein the The preset depth is 2.5μm~3.5μm; By thermal oxidation, a second oxide layer with a predetermined thickness is grown on the inner wall of the second trench; Deposit P-type doped polysilicon and N-type doped polysilicon sequentially into the second trench, and polish them using CMP technology; After the well is doped, high-temperature annealing is performed. The boron in the deposited P-type doped polysilicon will diffuse into the adjacent N-type epitaxial substrate through the second oxide layer on the sidewall to obtain an SGT device with high breakdown voltage. . 2. The process method of an SGT device according to claim 1, wherein the depth of the first trench is 5.5 μm~6.5 μm. 3. The process method of an SGT device according to claim 1, wherein in the step of growing the first oxide layer on the inner wall of the first trench by thermal oxidation, the temperature is 800°C to 1100°C. Oxygen is introduced under the conditions to grow a first oxide layer with a thickness of 5600Å~6500Å. 4. The processing method of an SGT device according to claim 1, wherein in the step of growing a second oxide layer with a predetermined thickness on the inner wall of the second trench by thermal oxidation, the The thickness of the second oxide layer is 400Å~600Å. 5. The process method of an SGT device according to claim 1, wherein the P-type doped polysilicon and the N-type doped polysilicon are deposited in the second trench sequentially, and CMP technology is used. In the step of grinding, the P-type doped polysilicon is boron-doped polysilicon, where the doping concentration of boron is 10 ¹⁷ atoms/cm ³ ~10 ²¹ atoms/cm ³ . 6. The process method of an SGT device according to claim 1, wherein the P-type doped polysilicon and the N-type doped polysilicon are sequentially deposited in the second trench, and CMP technology is used. In the polishing step, the N-type doped polysilicon is deposited to a thickness of 1.2 μm to 1.4 μm. 7. The process method of an SGT device according to claim 1, characterized in that, in the step of performing high-temperature annealing after the well doping to obtain an SGT device with a high breakdown voltage, the annealing temperature is 800°C~ 1000℃. 8. An SGT device, characterized in that it is prepared by the process method of an SGT device according to any one of claims 1 to 7.