CN102184964B - N-channel accumulative SiC IEMOSFET (Implantation and Epitaxial Metal-Oxide-Semiconductor Field Effect Transistor) device and manufacturing method thereof - Google Patents

Abstract

The invention discloses an N-channel accumulation type SiC IEMOSFET device and a manufacturing method, which mainly solve the problems of low channel electron mobility and large conductor resistance of the SiC IEMOSFET device in the prior art. Its technical features are: on the basis of the existing SiC IEMOSFET device structure, the conductive channel layer formed by implantation is replaced by epitaxy with a thickness of 0.1 μm to 0.2 μm, and the nitrogen ion doping concentration is 4×10 ¹⁶ cm ^{- 3 N-} epitaxial accumulation layer (6'), the epitaxial accumulation layer (6') is laterally located between the left source region N ⁺ contact (4a) and the right source region N ⁺ contact (4b), and vertically located between the isolation medium (2 ) and the JFET region (8). The invention has the advantages of high channel electron mobility, low on-resistance and low power consumption, and can be applied to the fields of automotive electronics, computers and communications.

Description

Fabrication method of N-channel accumulation SiC IEMOSFET device

technical field

The invention belongs to the technical field of microelectronics, and relates to a semiconductor device, in particular to an N-channel accumulation type SiC IEMOSFET device and a preparation method. the

Background technique

SiC has become one of the most advantageous semiconductor materials for manufacturing high-temperature, high-power electronic devices due to its excellent physical, chemical and electrical properties, and has a power device quality factor much greater than that of Si materials. The research and development of SiC power device MOSFET began in the 1990s. It has a series of advantages such as high input impedance, fast switching speed, high operating frequency, and high temperature and high pressure resistance. It has been used in switching regulated power supplies, high-frequency heating, automotive electronics and power amplifiers. and so on have been widely used. the

However, the quality of the contact interface between SiC and _SiO2 in current SiC power MOS devices is poor, and the high density of interface states and interface roughness lead to severe degradation of device channel mobility and on-resistance, and even make the performance of SiC-based devices not up to to the performance of Si-based devices. Therefore, how to reduce the contact interface roughness and interface state density of SiC and _SiO2 through process and structure improvement has been a relatively active topic.

Ion implantation and high temperature annealing process are the main reasons for the rough interface of SiC MOS devices. Studies have shown that the roughness of the surface will increase by more than 10 times after high temperature annealing at about 1600 degrees. Severe interface roughness can also lead to reduced reliability of the gate oxide layer. The double epitaxial MOSFET forms a p-well through p+ and ^p- double epitaxy, which avoids the impact of the interface roughness caused by the ion implantation process and the high concentration of p-type impurities on the channel mobility of the device. However, the interface groove formed by the trench etching after the p+ epitaxy will cause the breakdown characteristics of the device to degrade significantly. In order to solve this problem, SHINSUKE HARAD and others proposed an IEMOSFET in 2008, as shown in Figure 1.

Including gate 1, _SiO2 isolation dielectric 2, source 3, source region N ⁺ contact 4, P ⁺ contact 5, buried channel region 6, ^P- epitaxial layer 7, JFET region 8, P well 9, N ^- drift layer 10, N ⁺ substrate 11 and drain 12. This IEMOSFET structure uses selective ion implantation to form the p+ layer at the bottom of the p well, and then epitaxially forms the p- layer, avoiding the process of trench etching. Combined with the buried channel structure, the influence of the contact interface of SiC and SiO ₂ on the channel mobility is weakened, and the on-resistance of the device is greatly reduced. The on-resistance of the device with a breakdown voltage of 1100V reaches 4.3mΩ·cm ² .

Although the adoption of this structure and process improves the interface characteristics of the device to a certain extent, because the buried channel 6 of the device is still formed by ion implantation, the contact interface between SiC and SiO ₂ is rough, high lattice damage, A series of problems, such as low activation rate, greatly reduce the electron mobility of the inversion layer and increase the on-resistance of the device, which seriously affects the performance of the device.

Contents of the invention

The purpose of the present invention is to retain the existing advantages of the above-mentioned IEMOSFET, and improve the shortcomings of the above-mentioned prior art, and provide a SiC MOSFET structure and process method with high electron mobility and low on-resistance, so as to suppress the injection process. A series of problems such as the rough contact interface of SiC and SiO ₂ , high lattice damage, and low activation rate affect the performance of the device, and improve the performance of the device.

The purpose of the present invention is achieved like this:

The device structure of the present invention is improved on the IEMOSFET structure proposed by SHINSUKE HARADA et al. of Japan Industrial Technology Research Institute, and the formation process of the n-type buried trench is changed from ion implantation to the third epitaxy, so as to avoid the formation of the n-type buried trench by the implantation process. A series of problems such as interface roughness, high lattice damage, and low activation rate brought about by the channel. the

1. The device of the present invention includes from top to bottom: gate, _SiO2 isolation dielectric, source, source region N ⁺ contact, P ⁺ contact, P ^- epitaxial layer, JFET region, P well, N ^- drift layer, N ⁺ substrate and drain, wherein an ^N- epitaxial accumulation layer is provided between the SiO ₂ isolation medium and the JFET region to ensure the depth of the conductive channel of the device in the working state and reduce the influence of surface scattering on the mobility.

The ^N- epitaxial accumulation layer is located vertically between the SiO ₂ isolation dielectric and the JFET region, and laterally located between the N ⁺ contacts of the two source regions.

The thickness of the N ^- epitaxial accumulation layer is 0.1 μm˜0.2 μm.

The gate electrode is made of polysilicon doped with phosphorus ions, and the doping concentration is 5×10 ¹⁹ cm ^-3 to 1×10 ²⁰ cm ^-3 .

The thickness of the SiO ₂ isolation medium ranges from 50nm to 100nm.

The P ^- epitaxial layer is doped with boron ions, and the doping concentration is 1×10 ¹⁵ cm ^-3 to 1×10 ¹⁶ cm ^-3 .

Two. the manufacture method of device of the present invention, comprises following order:

(1) On the N ⁺ silicon carbide substrate, grow an N ^- drift layer doped with 8-9μm nitrogen ions, with a doping concentration of 1×10 ¹⁵ cm ^-3 to 2×10 ¹⁵ cm ^-3 , and an epitaxy temperature of 1570°C , the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is liquid nitrogen;

(2) Perform multiple selective implantation of aluminum ions on the N ^- drift layer doped with nitrogen ions to form a P well with a depth of 0.5 μm and a doping concentration of 3×10 ¹⁸ cm ^-3 , and the implantation temperature is 650°C;

(3) Epitaxially grow an aluminum ion-doped P ^- epitaxial layer with a ^thickness of 0.4 μm on the entire front surface of ^the silicon ^carbide wafer ^. °C, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is trimethylaluminum;

(4) Selectively implant multiple nitrogen ions in the middle region of the p-well to form a JFET region with a depth of 0.4 μm and a doping concentration of 1×10 ¹⁷ cm ^-3 , and the implantation temperature is 500°C;

(5) Epitaxially grow a 0.1μm-0.2μm thick nitrogen ion-doped N ^- epitaxial accumulation layer on the entire front side of the silicon carbide wafer, the doping concentration is 4×10 ¹⁶ cm ^-3 , the epitaxy temperature is 1570°C, and the pressure is 100mbar , the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is liquid nitrogen;

(6) On the nitrogen ion-doped N ^- epitaxial accumulation layer, perform multiple selective nitrogen ion implantations to form an N ⁺ source region with a depth of 0.25 μm and a doping concentration of 1×10 ¹⁹ cm ^-3 , and the implantation temperature 500°C; multiple times of selective implantation of aluminum ions on the ^N- epitaxial accumulation layer doped with nitrogen ions to form a P ⁺ contact with a depth of 0.5 μm and a doping concentration of 1×10 ¹⁹ cm ^-3 , the implantation temperature is 650°C;

(7) Carry out dry oxygen oxidation and wet oxygen oxidation sequentially on the entire silicon carbide front to form a SiO ₂ isolation medium of 50nm to 100nm, the dry oxygen oxidation temperature is 1200°C, and the wet oxygen oxidation temperature is 950°C;

(8) Deposit and form a 200nm phosphorous ion-doped polysilicon gate on the SiO ₂ isolation dielectric, with a doping concentration of 5×10 ¹⁹ cm ^-3 to 1×10 ²⁰ cm ^-3 , and a deposition temperature of 600 to 650°C , the deposition pressure is 60-80Pa, the reaction gas is silane and phosphine, and the carrier gas is helium;

(9) Deposit 300nm/100nm Al/Ti alloy as the contact metal layer of the source and drain, and anneal for 3 minutes in a nitrogen atmosphere at a temperature of 1100±50° C. to form an ohmic contact. the

Compared with the prior art, the present invention has the following advantages:

1) Since the present invention uses epitaxy to form the conductive channel instead of implantation, a series of problems such as rough contact interface between SiC and SiO ₂ , high lattice damage, and low activation rate caused by the implantation process are suppressed.

2) The present invention reduces the interface roughness of SiC and _SiO2 due to the use of epitaxy to form the conductive channel, thereby reducing the influence of surface scattering on the mobility, so that the carrier mobility is greatly increased; at the same time, the conductivity of the device is also reduced. The on-resistance reduces the power consumption of the device during operation and obtains better device performance.

3) The N ^- epitaxial accumulation layer of the present invention adopts low-doped epitaxy, so that the conductive channel has a certain depth, thereby reducing the influence of surface scattering on mobility.

4) The present invention adopts the epitaxial process instead of the implantation process to form the conductive channel in manufacturing, and the process is simple and easy to realize. the

Description of drawings

Figure 1 is a schematic diagram of the IEMOSFET device structure proposed by SHINSUKE HARADA et al. the

Fig. 2 is a schematic diagram of an N-channel accumulation SiC IEMOSFET device provided by the present invention. the

Fig. 3 is a production flow chart of the present invention. the

Detailed ways

Referring to Fig. 2, the device structure of the present invention includes from top to bottom: polysilicon gate 1, _SiO2 isolation dielectric 2, source metal 3, source region N ⁺ contact 4, P ⁺ contact 5, N ^- epitaxial accumulation layer 6' , P ^- epitaxial layer 7 , JFET region 8 , P well 9 , N ^- drift layer 10 , N ⁺ substrate 11 and drain 12 .

Wherein, the N ⁺ substrate 11 is a highly doped silicon carbide substrate; the convex region on the N ⁺ substrate 11 is an N ^- drift layer 10 doped with 8-9 μm nitrogen ions, and the doping concentration is 1×10 ¹⁵ cm ^-3 to 2×10 ¹⁵ cm ^-3 ; P well 9 is a region formed by multiple selective implantation of aluminum ions with a depth of 0.5 μm and a doping concentration of 3×10 ¹⁸ cm ^-3 , located in the convex N ^- The left and right upper corners of the drift layer 10; directly above the N ^- drift layer 10 are multiple nitrogen ion selective implants, forming a JFET region 8 with a depth of 0.4 μm and a doping concentration of 1×10 ¹⁷ cm ^-3 ; the JFET region 8, the left and right adjacent areas are aluminum ion ^- doped P- epitaxial layer 7 with a thickness of 0.4 μm, and the doping concentration is 1×10 ¹⁵ cm ^-3 to 1×10 ¹⁶ cm ^-3 ; the left and right upper corners of P well 9 It is the P + contact 5 with a depth of 0.5 μm and a doping concentration of 1×10 ¹⁹ cm ^-3 formed by multiple selective implantation of aluminum ions; near the P ⁺ contact 5 is the depth of multiple selective implantation of nitrogen ions ^. N ⁺ contact 4 in the source region with a doping concentration of 0.25 μm and a doping concentration of 1×10 ¹⁹ cm ^-3 ; the N ^- epitaxial accumulation layer 6′ is a nitrogen ion-doped N ^- epitaxial accumulation layer with a thickness of 0.1 μm to 0.2 μm, doped The concentration is 4×10 ¹⁶ cm ^-3 , the N ^- epitaxial accumulation layer 6' is laterally located between the N ⁺ contact of the left source region 4a and the N ⁺ contact of the right source region 4b, and vertically located above the JFET region 8; SiO ₂ The isolation medium 2 has a thickness of 50nm-100nm and is located above the N ^- epitaxial accumulation layer 6′; the polysilicon gate 1 is formed by depositing 200nm phosphorous ion-doped polysilicon, and the doping concentration is 5×10 ¹⁹ cm ^-3 ～ 1×10 ²⁰ cm ^-3 , located directly above the SiO ₂ isolation dielectric 2; the source metal 3 is a 300nm/100nm Al/Ti alloy formed by deposition, located at the source region N ⁺ contact 4 and P ⁺ contact 5 Above; the drain electrode 12 is formed by deposition of 300nm/100nm Al/Ti alloy, located on the back side of the silicon carbide substrate 11 .

Referring to Fig. 3, the manufacturing method of the device of the present invention is illustrated by the following examples. the

Example 1

Step 1. Epitaxially grow N ^- drift layer on N ⁺ silicon carbide substrate.

Clean the N ⁺ silicon carbide substrate 11 using RCA cleaning standards, and then epitaxially grow an N ^- drift layer 10 with a thickness of 8 μm and a nitrogen ion doping concentration of 1×10 ¹⁵ cm ^-3 on the substrate surface, as shown in Figure 3a, The process conditions are: the epitaxy temperature is 1570°C, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is liquid nitrogen.

Step 2. Multiple times of selective implantation of aluminum ions to form a P well. the

(2.1) Deposit a _SiO2 layer with a thickness of 0.2 μm on the front side of the silicon carbide wafer by low-pressure hot-wall chemical vapor deposition, and then deposit Al with a thickness of 1 μm as a barrier layer for the ion implantation of the P well 9, Forming the P well implantation region by photolithography and etching;

(2.2) Perform Al ion implantation into the P well implantation region four times at an ambient temperature of 650°C, using implantation energies of 450keV, 300keV, 200keV and 120keV successively, and implanting doses of 7.97×10 ¹³ cm ^-2 , 4.69×10 Aluminum ions of ¹³ cm ^-2 , 3.27×10 ¹³ cm ^-2 and 2.97×10 ¹³ cm ^-2 are implanted into the implantation region of the P well to form a P well with a depth of 0.5 μm and a doping concentration of 3×10 ¹⁸ cm ^-3 Well 9, as shown in Figure 3b;

(2.3) Clean the silicon carbide surface with RCA cleaning standard, and make C film protection after drying; then perform ion activation annealing in an argon atmosphere at 1700-1750 °C for 10 minutes. the

Step 3. Epitaxially grow the P ^- epi layer.

Epitaxially grow a P ^- epitaxial layer 7 with a thickness of 0.4 μm and an aluminum ion doping concentration of 1×10 ¹⁵ cm ^-3 on the front side of the silicon carbide wafer, as shown in Figure 3c. The process conditions are: the epitaxy temperature is 1570°C, and the pressure is 100mbar , the reaction gas uses silane and propane, the carrier gas uses pure hydrogen, and the impurity source uses trimethylaluminum.

Step 4. Selective implantation of nitrogen ions multiple times to form a JFET region. the

(4.1) Deposit a _SiO2 layer with a thickness of 0.2 μm on the front side of the silicon carbide wafer by low-pressure hot-wall chemical vapor deposition, and then deposit Al with a thickness of 1 μm as the barrier layer for ion implantation in the JFET region 8. Photolithography and etching to form the JFET implant region;

(4.2) Perform nitrogen ion implantation into the JFET implantation region four times at an ambient temperature of 500°C, using implantation energies of 300keV, 200keV, 140keV, and 80keV successively, and implanting doses of 1.70×10 ¹² cm ^-2 , 1.29×10 Nitrogen ions of ¹² cm ^-2 , 1.03×10 ¹² cm ^-2 and 1.13×10 ¹² cm ^-2 are implanted into the JFET implantation region to form a JFET region with a depth of 0.4 μm and a doping concentration of 1×10 ¹⁷ cm ^-3 8, as shown in Figure 3d;

(4.3) Clean the silicon carbide surface with the RCA cleaning standard, and make a C film protection after drying; then perform ion activation annealing in an argon atmosphere at 1700-1750 °C for 10 minutes. the

Step 5. Epitaxially grow the N ^- epitaxial accumulation layer.

Epitaxially grow an N ^- epitaxial accumulation layer 6' with a thickness of 0.1 μm and a doping concentration of 4×10 ¹⁶ cm ^-3 on the front side of the silicon carbide wafer, as shown in Figure 3e. The process conditions are: the epitaxy temperature is 1570°C, and the pressure is 100mbar , the reaction gas uses silane and propane, the carrier gas uses pure hydrogen, and the impurity source uses liquid nitrogen.

Step 6. Selective implantation of nitrogen ions multiple times to form an N ⁺ contact in the source region, and multiple selective implantations of aluminum ions to form a P ⁺ contact.

(6.1) Deposit a layer of _SiO2 with a thickness of 0.2 μm on the front of the silicon carbide wafer by low-pressure hot-wall chemical vapor deposition, and then deposit Al with a thickness of 1 μm as a barrier for N ⁺ contact ion implantation in the source region layer, the source region N ⁺ contact implantation region is formed by photolithography and etching.

(6.2) Under the ambient temperature of 500°C, carry out nitrogen ion implantation to the N ⁺ contact implantation region of the source region four times, using the implantation energy of 200keV, 140keV, 100keV and 65keV successively, and the implantation dose is 1.49×10 ¹⁴ cm ^-2 , Nitrogen ions of 7.99×10 ¹³ cm ^-2 , 7.25×10 ¹³ cm ^-2 and 7.02×10 ¹³ cm ^-2 are implanted into the implanted region of the N ⁺ contact, with a depth of 0.25 μm and a doping concentration of 1×10 ¹⁹ The source region N ⁺ contact 4 of cm ^-3 , as shown in Fig. 3f;

(6.3) Deposit a _SiO2 layer with a thickness of 0.2 μm on the front side of the silicon carbide wafer by low-pressure hot-wall chemical vapor deposition, and then deposit Al with a thickness of 1 μm as a barrier layer for P ⁺ contact ion implantation, Forming the P ⁺ contact implant region by photolithography and etching;

(6.4) Four times of Al ion implantation was carried out in the P ⁺ contact implantation region at an ambient temperature of 650°C. The implantation energies of 450keV, 300keV, 200keV and 120keV were used successively, and the implantation doses were 2.63×10 ¹⁴ cm ^-2 , 1.55× Aluminum ions of 10 ¹⁴ cm ^-2 , 1.08×10 ¹⁴ cm ^-2 and 9.79×10 ¹³ cm ^-2 are implanted into the P ⁺ contact implantation region with a depth of 0.5 μm and a doping concentration of 1×10 ¹⁹ cm ^-3 The P ⁺ contacts 5, as shown in Figure 3f;

(6.5) Clean the silicon carbide surface with the RCA cleaning standard, make a C film protection after drying, and then perform ion activation annealing in an argon atmosphere at 1700-1750 ° C for 10 minutes. the

Step 7. Oxidation to form a gate oxide film. the

(7.1) Dry oxygen oxidation at 1200°C for one hour, and then wet oxygen oxidation at 950°C for one hour to form an oxide film with a thickness of 50nm;

(7.2) Form the SiO ₂ isolation medium 2 by photolithography and etching, as shown in Figure 3g.

Step 8. Depositing and forming a polysilicon gate heavily doped with phosphorus ions with a doping concentration of 5×10 ¹⁹ cm ^-3 and a thickness of 200 nm.

Deposit and grow 200nm polysilicon on the front side of silicon carbide by low-pressure hot-wall chemical vapor deposition, and then retain the polysilicon on the gate oxide film by photolithography and etching to form a phosphorous ion doping concentration of 5×10 ¹⁹ cm ^-3 , a polysilicon gate 1 with a thickness of 200nm, as shown in Figure 3h, the process conditions are: deposition temperature is 600-650°C, deposition pressure is 60-80Pa, reaction gas is silane and phosphine, and carrier gas is helium.

Step 9. Depositing and forming a source contact metal layer and a drain contact metal layer. the

(9.1) Coating and developing the front side of the entire silicon carbide wafer to form N ⁺ and P ⁺ ohmic contact areas, depositing 300nm/100nm Al/Ti alloy, and then ultrasonic stripping to form the source metal 3 on the front side, such as Figure 3i;

(9.2) Deposit 300nm/100nm Al/Ti alloy on the back of the substrate as the drain electrode 12, as shown in Figure 3i;

(9.3) In a nitrogen atmosphere at 1100±50°C, anneal the entire silicon carbide wafer for 3 minutes to form ohmic contact electrodes. the

Example 2

Step 1. Epitaxial growth of N ^- drift layer on N ⁺ silicon carbide substrate.

Clean the N ⁺ silicon carbide substrate 11 with the RCA cleaning standard, and then epitaxially grow an N ^- drift layer 10 with a thickness of 8.5 μm and a nitrogen ion doping concentration of 1.5×10 ¹⁵ cm ^-3 on the substrate surface, as shown in Figure 3a , the process conditions are: the epitaxy temperature is 1570°C, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is liquid nitrogen.

Step 2. Multiple times of selective implantation of aluminum ions to form a P well. the

(2.1) Deposit a _SiO2 layer with a thickness of 0.2 μm on the front side of the silicon carbide wafer by low-pressure hot-wall chemical vapor deposition, and then deposit Al with a thickness of 1 μm as a barrier layer for the ion implantation of the P well 9, Forming the P well implantation region by photolithography and etching;

(2.2) Perform Al ion implantation into the P well implantation region four times at an ambient temperature of 650°C, using implantation energies of 450keV, 300keV, 200keV and 120keV successively, and implanting doses of 7.97×10 ¹³ cm ^-2 , 4.69×10 Aluminum ions of ¹³ cm ^-2 , 3.27×10 ¹³ cm ^-2 and 2.97×10 ¹³ cm ^-2 are implanted into the implantation region of the P well to form a P well with a depth of 0.5 μm and a doping concentration of 3×10 ¹⁸ cm ^-3 Well 9, as shown in Figure 3b;

(2.3) Clean the silicon carbide surface with RCA cleaning standard, and make C film protection after drying; then perform ion activation annealing in an argon atmosphere at 1700-1750 °C for 10 minutes. the

Step 3. Epitaxial growth of the P ^- epi layer.

Epitaxially grow a P ^- epitaxial layer 7 with a thickness of 0.4 μm and an aluminum ion doping concentration of 5×10 ¹⁵ cm ^-3 on the front side of the silicon carbide wafer, as shown in Figure 3c. The process conditions are: epitaxy temperature is 1570°C, pressure is 100mbar , the reaction gas uses silane and propane, the carrier gas uses pure hydrogen, and the impurity source uses trimethylaluminum.

Step 4. Selective implantation of nitrogen ions multiple times to form the JFET region. the

(4.1) Deposit a _SiO2 layer with a thickness of 0.2 μm on the front side of the silicon carbide wafer by low-pressure hot-wall chemical vapor deposition, and then deposit Al with a thickness of 1 μm as the barrier layer for ion implantation in the JFET region 8. Photolithography and etching to form the JFET implant region;

(4.2) Perform nitrogen ion implantation into the JFET implantation region four times at an ambient temperature of 500°C, using implantation energies of 300keV, 200keV, 140keV, and 80keV successively, and implanting doses of 1.70×10 ¹² cm ^-2 , 1.29×10 Nitrogen ions of ¹² cm ^-2 , 1.03×10 ¹² cm ^-2 and 1.13×10 ¹² cm ^-2 are implanted into the JFET implantation region to form a JFET region with a depth of 0.4 μm and a doping concentration of 1×10 ¹⁷ cm ^-3 8, as shown in Figure 3d;

(4.3) Clean the silicon carbide surface with the RCA cleaning standard, and make a C film protection after drying; then perform ion activation annealing in an argon atmosphere at 1700-1750 °C for 10 minutes. the

Step 5. Epitaxial growth of N ^- epitaxial accumulation layer.

Epitaxially grow an N ^- epitaxial accumulation layer 6' with a thickness of 0.15 μm and a doping concentration of 4×10 ¹⁶ cm ^-3 on the front side of the silicon carbide wafer, as shown in Figure 3e. The process conditions are: the epitaxy temperature is 1570°C, and the pressure is 100mbar , the reaction gas uses silane and propane, the carrier gas uses pure hydrogen, and the impurity source uses liquid nitrogen.

Step 6. Selective implantation of nitrogen ions multiple times to form N ⁺ contacts in the source region, and multiple selective implantations of aluminum ions to form P ⁺ contacts.

(6.1) Deposit a layer of _SiO2 with a thickness of 0.2 μm on the front of the silicon carbide wafer by low-pressure hot-wall chemical vapor deposition, and then deposit Al with a thickness of 1 μm as a barrier for N ⁺ contact ion implantation in the source region layer, the source region N ⁺ contact implantation region is formed by photolithography and etching.

(6.2) Under the ambient temperature of 500°C, carry out nitrogen ion implantation to the N ⁺ contact implantation region of the source region four times, using the implantation energy of 200keV, 140keV, 100keV and 65keV successively, and the implantation dose is 1.49×10 ¹⁴ cm ^-2 , Nitrogen ions of 7.99×10 ¹³ cm ^-2 , 7.25×10 ¹³ cm ^-2 and 7.02×10 ¹³ cm ^-2 are implanted into the implanted region of the N ⁺ contact, with a depth of 0.25 μm and a doping concentration of 1×10 ¹⁹ The source region N ⁺ contact 4 of cm ^-3 , as shown in Fig. 3f;

(6.3) Deposit a _SiO2 layer with a thickness of 0.2 μm on the front side of the silicon carbide wafer by low-pressure hot-wall chemical vapor deposition, and then deposit Al with a thickness of 1 μm as a barrier layer for P ⁺ contact ion implantation, Forming the P ⁺ contact implant region by photolithography and etching;

(6.4) Four times of Al ion implantation was carried out in the P ⁺ contact implantation region at an ambient temperature of 650°C. The implantation energies of 450keV, 300keV, 200keV and 120keV were used successively, and the implantation doses were 2.63×10 ¹⁴ cm ^-2 , 1.55× Aluminum ions of 10 ¹⁴ cm ^-2 , 1.08×10 ¹⁴ cm ^-2 and 9.79×10 ¹³ cm ^-2 are implanted into the P ⁺ contact implantation region with a depth of 0.5 μm and a doping concentration of 1×10 ¹⁹ cm ^-3 The P ⁺ contacts 5, as shown in Figure 3f;

(6.5) Clean the silicon carbide surface with the RCA cleaning standard, make a C film protection after drying, and then perform ion activation annealing in an argon atmosphere at 1700-1750 ° C for 10 minutes. the

Step 7. Oxidation to form a gate oxide film. the

(7.1) After dry oxygen oxidation at 1200°C for two hours, then wet oxygen oxidation at 950°C for one hour to form an oxide film with a thickness of 70nm;

(7.2) Form the SiO ₂ isolation medium 2 by photolithography and etching, as shown in Figure 3g.

Step 8. Deposit and form a polysilicon gate heavily doped with phosphorus ions with a doping concentration of 7×10 ¹⁹ cm ^-3 and a thickness of 200 nm.

Deposit and grow 200nm polysilicon on the front side of silicon carbide by low-pressure hot-wall chemical vapor deposition, and then retain the polysilicon on the gate oxide film by photolithography and etching to form a phosphorous ion doping concentration of 5×10 ¹⁹ cm ^-3 , a polysilicon gate 1 with a thickness of 200nm, as shown in Figure 3h, the process conditions are: deposition temperature is 600-650°C, deposition pressure is 60-80Pa, reaction gas is silane and phosphine, and carrier gas is helium.

Step 9. Depositing and forming a source contact metal layer and a drain contact metal layer. the

(9.1) Coating and developing the front side of the entire silicon carbide wafer to form N ⁺ and P ⁺ ohmic contact areas, depositing 300nm/100nm Al/Ti alloy, and then ultrasonic stripping to form the source metal 3 on the front side, such as Figure 3i;

(9.2) Deposit 300nm/100nm Al/Ti alloy on the back of the substrate as the drain electrode 12, as shown in Figure 3i;

(9.3) In a nitrogen atmosphere at 1100±50°C, anneal the entire silicon carbide wafer for 3 minutes to form ohmic contact electrodes. the

Example 3

Step A. Epitaxially grow an N ⁻ drift layer on the N ⁺ silicon carbide substrate.

Clean the N ⁺ silicon carbide substrate 11 using RCA cleaning standards, and then epitaxially grow an N ^- drift layer 10 with a thickness of 9 μm and a nitrogen ion doping concentration of 2×10 ¹⁵ cm ^-3 on the substrate surface, as shown in Figure 3a, The process conditions are: the epitaxy temperature is 1570°C, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is liquid nitrogen.

Step B. multiple times of selective implantation of aluminum ions to form a P well. the

(B1) Deposit a _SiO2 layer with a thickness of 0.2 μm on the front surface of the silicon carbide wafer by low-pressure hot-wall chemical vapor deposition, and then deposit Al with a thickness of 1 μm as a barrier layer for the ion implantation of the P well 9, Forming the P well implantation region by photolithography and etching;

(B2) Perform Al ion implantation into the P well implantation region four times at an ambient temperature of 650°C, using implantation energies of 450keV, 300keV, 200keV and 120keV successively, and implanting doses of 7.97×10 ¹³ cm ^-2 , 4.69×10 Aluminum ions of ¹³ cm ^-2 , 3.27×10 ¹³ cm ^-2 and 2.97×10 ¹³ cm ^-2 are implanted into the implantation region of the P well to form a P well with a depth of 0.5 μm and a doping concentration of 3×10 ¹⁸ cm ^-3 Well 9, as shown in Figure 3b;

(B3) Clean the silicon carbide surface with RCA cleaning standard, and make a C film protection after drying; then perform ion activation annealing in an argon atmosphere at 1700-1750 °C for 10 minutes. the

Step C. Epitaxially grow the P ^- epi layer.

Epitaxially grow a P ^- epitaxial layer 7 with a thickness of 0.4 μm and an aluminum ion doping concentration of 1×10 ¹⁶ cm ^-3 on the front side of the silicon carbide wafer, as shown in Figure 3c. The process conditions are: the epitaxy temperature is 1570°C, and the pressure is 100mbar , the reaction gas uses silane and propane, the carrier gas uses pure hydrogen, and the impurity source uses trimethylaluminum.

Step D. Selective implantation of nitrogen ions multiple times to form a JFET region. the

(D1) Deposit a _SiO2 layer with a thickness of 0.2 μm on the front side of the silicon carbide wafer by low-pressure hot-wall chemical vapor deposition, and then deposit Al with a thickness of 1 μm as the barrier layer for ion implantation in the JFET region 8. Photolithography and etching to form the JFET implant region;

(D2) Perform nitrogen ion implantation into the JFET implantation region four times at an ambient temperature of 500°C, using implantation energies of 300keV, 200keV, 140keV, and 80keV successively, and implanting doses of 1.70×10 ¹² cm ^-2 , 1.29×10 Nitrogen ions of ¹² cm ^-2 , 1.03×10 ¹² cm ^-2 and 1.13×10 ¹² cm ^-2 are implanted into the JFET implantation region to form a JFET region with a depth of 0.4 μm and a doping concentration of 1×10 ¹⁷ cm ^-3 8, as shown in Figure 3d;

(D3) Clean the silicon carbide surface with the RCA cleaning standard, and make a C film protection after drying; then perform ion activation annealing in an argon atmosphere at 1700-1750 °C for 10 minutes. the

Step E. Epitaxially grow the N ^- epitaxial accumulation layer.

Epitaxially grow an N ^- epitaxial accumulation layer 6' with a thickness of 0.2 μm and a doping concentration of 4×10 ¹⁶ cm ^-3 on the front side of the silicon carbide wafer, as shown in Figure 3e. The process conditions are: the epitaxy temperature is 1570°C, and the pressure is 100mbar , the reaction gas uses silane and propane, the carrier gas uses pure hydrogen, and the impurity source uses liquid nitrogen.

Step F: multiple nitrogen ions are selectively implanted to form N ⁺ contacts in the source region, and multiple aluminum ions are selectively implanted to form P ⁺ contacts.

(F1) Deposit a layer of _SiO2 with a thickness of 0.2 μm on the front side of the silicon carbide wafer by low-pressure hot-wall chemical vapor deposition, and then deposit Al with a thickness of 1 μm as a barrier for N ⁺ contact ion implantation in the source region layer, the source region N ⁺ contact implantation region is formed by photolithography and etching.

(F2) Under the ambient temperature of 500°C, nitrogen ion implantation was performed four times in the N ⁺ contact implantation region of the source region, and the implantation energies of 200keV, 140keV, 100keV and 65keV were successively adopted, and the implantation dose was 1.49×10 ¹⁴ cm ^-2 , Nitrogen ions of 7.99×10 ¹³ cm ^-2 , 7.25×10 ¹³ cm ^-2 and 7.02×10 ¹³ cm ^-2 are implanted into the implanted region of the N ⁺ contact, with a depth of 0.25 μm and a doping concentration of 1×10 ¹⁹ The source region N ⁺ contact 4 of cm ^-3 , as shown in Fig. 3f;

(F3) Deposit a layer of _SiO2 with a thickness of 0.2 μm on the front side of the silicon carbide wafer by low-pressure hot-wall chemical vapor deposition, and then deposit Al with a thickness of 1 μm as a barrier layer for P ⁺ contact ion implantation, Forming the P ⁺ contact implant region by photolithography and etching;

(F4) Four times of Al ion implantation was performed on the P ⁺ contact implantation region at an ambient temperature of 650°C, using implantation energies of 450keV, 300keV, 200keV and 120keV successively, and the implantation doses were 2.63×10 ¹⁴ cm ^-2 , 1.55× Aluminum ions of 10 ¹⁴ cm ^-2 , 1.08×10 ¹⁴ cm ^-2 and 9.79×10 ¹³ cm ^-2 are implanted into the P ⁺ contact implantation region with a depth of 0.5 μm and a doping concentration of 1×10 ¹⁹ cm ^-3 The P ⁺ contacts 5, as shown in Figure 3f;

(F5) Clean the silicon carbide surface with the RCA cleaning standard, make a C film protection after drying, and then perform ion activation annealing in an argon atmosphere at 1700-1750°C for 10 minutes. the

Step G. Oxidation to form a gate oxide film. the

(G1) After dry oxygen oxidation at 1200°C for three and a half hours, then wet oxygen oxidation at 950°C for one hour to form an oxide film with a thickness of 100nm;

(G2) Form the SiO ₂ isolation medium 2 by photolithography and etching, as shown in Figure 3g.

Step H. Deposit and form a polysilicon gate heavily doped with phosphorus ions with a doping concentration of 1×10 ²⁰ cm ^-3 and a thickness of 200 nm.

Deposit and grow 200nm polysilicon on the front side of silicon carbide by low-pressure hot-wall chemical vapor deposition, and then retain the polysilicon on the gate oxide film by photolithography and etching to form a phosphorous ion doping concentration of 5×10 ¹⁹ cm ^-3 , a polysilicon gate 1 with a thickness of 200nm, as shown in Figure 3h, the process conditions are: deposition temperature is 600-650°C, deposition pressure is 60-80Pa, reaction gas is silane and phosphine, and carrier gas is helium.

Step I. Depositing and forming a source contact metal layer and a drain contact metal layer. the

(I1) Coating and developing the front side of the entire silicon carbide wafer to form N ⁺ and P ⁺ ohmic contact regions, depositing 300nm/100nm Al/Ti alloy, and then ultrasonic stripping to form the source metal 3 on the front side, such as Figure 3i;

(I2) Deposit 300nm/100nm Al/Ti alloy on the back of the substrate as the drain electrode 12, as shown in Figure 3i;

(I3) In a nitrogen atmosphere at 1100±50° C., anneal the entire silicon carbide wafer for 3 minutes to form ohmic contact electrodes. the

Claims (1)

1. method for preparing N raceway groove accumulation type IEMOSFET comprises following order:

(1) at N ⁺The N of 8～9 μ m nitrogen ion dopings grows on the silicon carbide substrates sheet ^-Drift layer, doping content are 1 * 10 ¹⁵Cm ^-3～2 * 10 ¹⁵Cm ^-3, epitaxial temperature is 1570 ℃, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is pure hydrogen, impurity source is liquid nitrogen;

(2) at the N of nitrogen ion doping ^-Carry out repeatedly aluminium ion Selective implantation on the drift layer, forming the degree of depth is 0.5 μ m, and doping content is 3 * 10 ¹⁸Cm ^-3The P trap, implantation temperature is 650 ℃;

(3) be the P of the Al-doping of 0.4 μ m at the positive epitaxial growth thickness of whole silicon carbide plate ^-Epitaxial loayer, doping content are 1 * 10 ¹⁵Cm ^-3～1 * 10 ¹⁶Cm ^-3, epitaxial temperature is 1570 ℃, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is pure hydrogen, impurity source is trimethyl aluminium;

(4) carry out repeatedly the nitrogen ion selectivity at p trap zone line and inject, forming the degree of depth is 0.4 μ m, and doping content is 1 * 10 ¹⁷Cm ^-3The JFET district, implantation temperature is 500 ℃;

(5) at the N of the positive epitaxial growth 0.1 μ m of whole silicon carbide plate～nitrogen ion doping that 0.2 μ m is thick ^-Extension accumulation layer, doping content are 4 * 10 ¹⁶Cm ^-3, epitaxial temperature is 1570 ℃, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is pure hydrogen, impurity source is liquid nitrogen;

(6) at the N of nitrogen ion doping ^-Carry out first repeatedly the nitrogen ion selectivity on the extension accumulation layer and inject, forming the degree of depth is 0.25 μ m, and doping content is 1 * 10 ¹⁹Cm ^-3N ⁺Source region, implantation temperature are 500 ℃; Again at the N of nitrogen ion doping ^-Carry out repeatedly aluminium ion Selective implantation on the extension accumulation layer, forming the degree of depth is 0.5 μ m, and doping content is 1 * 10 ¹⁹Cm ^-3P ⁺Contact, implantation temperature is 650 ℃;

(7) whole carborundum front is carried out dry-oxygen oxidation and wet-oxygen oxidation successively, form the SiO of 50nm～100nm ₂Spacer medium, dry-oxygen oxidation temperature are 1200 ℃, and the wet-oxygen oxidation temperature is 950 ℃;

(8) at SiO ₂Deposit forms the polysilicon gate of the phosphonium ion doping of 200nm on the spacer medium, and doping content is 5 * 10 ¹⁹Cm ^-3～1 * 10 ²⁰Cm ^-3, deposition temperature is 600～650 ℃, and deposit pressure is 60～80Pa, and reacting gas is silane and hydrogen phosphide, and carrier gas is helium;

(9) the Al/Ti alloy of deposit 300nm/100nm, as the contact metal layer of source electrode and drain electrode, and annealing formed ohmic contact in 3 minutes in the nitrogen atmosphere under 1100 ± 50 ℃ of temperature.

Images