CN116454184A - High-light-efficiency LED epitaxial wafer, preparation method thereof and LED - Google Patents

Abstract

The invention provides a high-light-efficiency LED epitaxial wafer, a preparation method thereof and an LED, wherein the high-light-efficiency LED epitaxial wafer comprises an electron blocking layer, and the electron blocking layer comprises a first sub-layer, a second sub-layer and a third sub-layer; the first sub-layer is an AlN layer, the second sub-layer is a DGaN/DAlGaN superlattice layer, and the third sub-layer comprises P-type AlxGa _1‑x N/D _y Ga _1‑y N-superlattice layer, P-type Al _x Ga _1‑x N thin-layer reduction and D _y Ga _1‑y An N thin layer; the DGaN/DAlGaN superlattice layer comprises a DGaN layer and a DAlGaN layer which are periodically and alternately laminated. By the method, the effective injection efficiency of the holes is improved, the core difficulty of ionization activation of magnesium atoms is effectively solved, and the effective excitation of the magnesium atoms is improvedAnd (3) the active and incorporated components improve the generation of holes, thereby improving the luminous efficiency.

Description

A kind of high light efficiency LED epitaxial wafer and its preparation method, LED

technical field

The invention relates to the technical field of semiconductor preparation, in particular to a high-light-efficiency LED epitaxial wafer, a preparation method thereof, and an LED.

Background technique

As a typical representative of the third-generation semiconductor, gallium nitride material has the characteristics of large band gap and high electron mobility. In particular, gallium nitride-based devices are widely used in electronic systems such as wireless communication and radar in the microwave and millimeter wave frequency bands, and have very broad development prospects in the fields of optoelectronics and microelectronics.

At present, traditional gallium nitride diodes usually include a substrate, a buffer layer, n-type GaN, an active layer, an electron blocking layer, and a p-type GaN, and the main source of light emission is the active layer. For the epitaxial structure, the required holes come from the Mg ionization of p-type GaN, and the electron blocking layer is Al component. The AlGaN layer acts to block electron overflow, but also blocks hole injection. The main difficulty is to effectively overcome the very high Mg acceptor activation energy while satisfying the thermodynamic premise of high Mg incorporation. The AL component will reduce the activation energy of Mg, resulting in extremely low thermal activation efficiency. Since gallium nitride diodes are generally prepared by metal-organic chemical vapor deposition (MOCVD) systems, it is extremely important to realize p-type GaN by MOCVD methods. Based on MOCVD methods, high incorporation efficiency of Mg atoms in p-type GaN and effective ionization of Mg atoms can be achieved. An effective way to activate the two core difficulties is a key technology that urgently needs to be broken through.

Contents of the invention

Based on this, the object of the present invention is to provide a high-efficiency LED epitaxial wafer, its preparation method, and LED, so as to solve the deficiencies in the prior art.

In order to achieve the above object, the present invention provides a high-efficiency LED epitaxial wafer, including a substrate, a buffer layer, an N-type layer, an active layer, an electron blocking layer and a P-type layer stacked in sequence, and the electron blocking layer includes a stacked a first sublayer, a second sublayer, and a third sublayer on the active layer;

The first sublayer is an AlN layer, the second sublayer is a DGaN/DAlGaN superlattice layer, and the third sublayer includes a P-type Al _x Ga _1-x N/D _y Ga _1-y N superlattice layer. lattice layer, P-type Al _x Ga _1-x N thinned layer and D _y Ga _1-y N thinned layer;

The DGaN/DAlGaN superlattice layer includes periodically alternately stacked DGaN layers and DAlGaN layers, and the P-type Al _x Ga _1-x N/D _y Ga _1-y N superlattice layer includes periodically alternately stacked P-type Al _x Ga _1-x N layer and D _y Ga _1-y N layer, the thickness of the P-type Al _x Ga _1-x N thinned layer is less than that of the P-type Al _x Ga _1-x N layer thickness, the thickness of the D _y Ga _1-y N thinned layer is less than the thickness of the D _y Ga _1-y N layer;

Wherein, D is at least one of boron, indium or carbon.

Preferably, the thickness of the first sublayer is 4nm-6nm, the thickness of the DGaN layer and the DAlGaN layer are both 4nm-6nm, the P-type _{AlxGa1 -xN} layer and the _Dy The Ga _1-y N layers all have a thickness of 3nm-4nm.

Preferably, the Al element in the P-type Al _x Ga _1-x N layer gradually decreases with the period, the thickness of the D _y Ga _1-y N layer gradually increases with the period, and the P-type Al _x Ga ₁ The doping degree of Mg element in _{the -x} N layer is 1E+16 atoms/cm ³ ~2E+17 atoms/cm ³ .

Preferably, the value ranges of x and y in the P-type Al _x Ga _1-x N layer and the D _y Ga _1-y N layer are respectively: 0≤x≤1, 0≤y≤1, and x<y.

Preferably, the DGaN layer and the DAlGaN layer are alternately stacked at a period of 2-3, and the P-type Al _x Ga _1-x N layer and the D _y Ga _1-y N layer in the combined structure are alternately stacked The cycle is 3-4.

Preferably, the concentrations of gallium components in the P-type Al _x Ga _1-x N thinned layer and the D _y Ga _1-y N thinned layer are respectively lower than those of the P-type Al _x Ga _1-x The concentration of the gallium component in the N layer and the D _y Ga _1-y N layer.

Preferably, the substrate is one of a sapphire substrate, a SiC substrate and a SiO ₂ substrate.

In order to achieve the above object, the present invention also provides a method for preparing the above-mentioned high-luminous-efficiency LED epitaxial wafer, the method comprising:

acquire a substrate;

Nitrogen gas and hydrogen gas are fed into the first ambient temperature to perform high temperature treatment on the substrate, and a nitrogen source and an aluminum source are fed into the MOCVD reaction chamber to obtain buffer deposits on the substrate after the high temperature treatment layer;

Doping silicon with a first doping concentration at a second ambient temperature to form an N-type layer on the buffer layer;

Doping aluminum elements with a second doping concentration at a third ambient temperature and a first ambient pressure to form an active layer in the N-type layer;

Depositing an electron blocking layer on the active layer by vapor deposition at a fourth ambient temperature and a second ambient pressure;

Under the fifth ambient temperature and the third ambient pressure, magnesium element with a third doping concentration is doped to deposit a P-type layer on the electron blocking layer.

Preferably, the step of depositing an electron blocking layer on the active layer by vapor deposition comprises:

The nitrogen source, the aluminum source, the boron source and the gallium source are passed into the MOCVD reaction chamber, and the first sublayer, the second sublayer and the third sublayer are sequentially formed on the active layer by vapor deposition, Then stop feeding the aluminum source and the gallium source, and desorb and thin the surface layer of the third sublayer to obtain a P-type _{AlxGa1 -xN} thinned layer and _{DyGa1 -y} N thinned layer.

To achieve the above object, the present invention also provides an LED, comprising the high-efficiency LED epitaxial wafer described above.

The beneficial effects of the present invention are: the barrier energy level is provided by the first sublayer to block the migration of electrons, and the D element in the second sublayer can be used to insert or fill the vacant positions caused by dislocations, which not only suppresses the dislocations generated by line defects Extension, while reducing the probability of defect generation, it can also ensure that the fitting stress between the lattices and the corresponding stress field are small, so as to improve the effective injection efficiency of holes, and then use the surface effect of the third sublayer To realize the efficient incorporation of magnesium atoms, that is, to use the process of desorption and thinning of the surface layer of the third sublayer, so that the surface structure of the desorption and thinning operation is used as a barrier layer, and the periodic change of Al composition along the growth direction is realized. Modulation, so as to effectively solve the core difficulty of ionization and activation of magnesium atoms, improve the effective activation and incorporation of magnesium atoms, increase the generation of holes, and thus improve the luminous efficiency.

Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of drawings

Fig. 1 is a schematic structural diagram of a high-efficiency LED epitaxial wafer provided by the first embodiment of the present invention;

FIG. 2 is a flow chart of a method for manufacturing a high-efficiency LED epitaxial wafer provided by the second embodiment of the present invention.

Description of main component symbols:

The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings.

Detailed ways

In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the associated drawings. Several embodiments of the invention are shown in the drawings. However, the present invention can be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention will be thorough and complete.

It should be noted that when an element is referred to as being “fixed on” another element, it may be directly on the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and similar expressions are used herein for purposes of illustration only.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Please refer to FIG. 1 , which shows a high-efficiency LED epitaxial wafer in the first embodiment of the present invention, including a substrate 10, a buffer layer 20, an N-type layer 30, an active layer 40, an electron blocking layer and P-type layer 80 .

Wherein: the electron blocking layer includes a first sublayer 50, a second sublayer 60 and a third sublayer 70 stacked on the active layer 40;

The first sublayer 50 is an AlN layer, and the first sublayer 50 is used to provide a better energy barrier level;

The second sub-layer 60 is a DGaN/DAlGaN superlattice layer, and the DGaN/DAlGaN superlattice layer includes periodically alternately stacked DGaN layers 61 and DAIGaN layers 62, both of which are superlattice structures ;

The third sublayer 70 includes a P-type _{AlxGa1 -xN} / _{DyGa1 -yN} superlattice layer 71, a P-type _{AlxGa1 -xN} thinned layer 72 and a D _y Ga _1-y N thinned layer 73, P-type Al _x Ga _1-x N/D _y Ga _1-y N superlattice layer 71 includes periodically alternately stacked P-type Al _x Ga _1-x N layers 711 and D _y Ga _1-y N layer 712, it can be understood that by desorbing and thinning the surface layer of the pre-generated third sub-layer 70, the P-type Al _x Ga _1-x N thinned layer 72 and D _{The y} Ga _1-y N thinning layer 73 is specifically to perform desorption and thinning on the surface layer of the third sublayer 70. Since Ga atoms are easier to desorb than Al atoms in the AlGaN system, the third sublayer The surface layer is spontaneously converted to form a P-type _{AlxGa1 -xN} thinned layer 72 and a _{DyGa1 -yN} thinned layer 73 with a sub-nanometer thickness, and the remaining structure in the third sublayer 70 that has not been desorbed and thinned is P-type Al _x Ga _1-x N/D _y Ga _1-y N superlattice layer 71, so that in P-type Al _x Ga _1-x N thinned layer 72 and D _y Ga _1-y N thinned layer 73 The concentration of the gallium component is lower than the concentration of the gallium component in the P-type _{AlxGa1 -xN} layer 711 and the _{DyGa1 -yN} layer 712, respectively, and the P-type _{AlxGa1 -xN} thinned The thickness of the layer 72 is less than the thickness of the P-type _{AlxGa1 -xN} layer 711, and the thickness of the _{DyGa1 -yN} thinned layer 73 is less than the thickness of the _{DyGa1 -yN} layer 712. It should be noted that, D is at least one of boron, indium or carbon.

In some of these embodiments, _the thickness of the first sublayer 50 is 4nm-6nm, the thicknesses of the DGaN layer 61 and the DAlGaN layer 62 are both 4nm-6nm, and the P-type _{AlxGa1 -xN} layer 711 and _DyGa1 The thickness of the _-y N layer 712 is 3nm-4nm. It should be noted that the optimal thickness of the first sublayer 50 is 5 nm, the optimal thickness of the DGaN layer 61 and the DAlGaN layer 62 are both 5 nm, and the P-type Al _x Ga _1-x N layer 711 and D _y Ga _1-y The optimal thickness of the N layer 712 is 3.5nm.

It can be understood that since the DGaN layer 61 and the DAlGaN layer 62 in the second sub-layer 60 are relatively thin, the stress generated by the interface can be continuously distorted, thereby reducing the occurrence of defects.

In some of these embodiments, the DGaN layer 61 and the DAlGaN layer 62 are alternately stacked at a period of 2-3, and the P-type _{AlxGa1 -xN} layer 711 and the _{DyGa1 -yN} layer 712 in the combined structure are alternately stacked The cycle is 3-4.

In some of these embodiments, the Al element in the P-type Al _x Ga _1-x N layer 711 gradually decreases with the period, the thickness of the Dy _{Ga 1-y} N layer 712 gradually increases with the period, and the P-type Al _x Ga ₁ The doping degree of the Mg element in the _-x N layer 711 is 1E+16 atoms/cm ³ -2E+17 atoms/cm ³ .

In some of these embodiments, the value ranges of x and y in the P-type Al _x Ga _1-x N layer 711 and Dy _{Ga 1-y} N layer 712 are: 0≤x≤1, 0≤y≤1 , and x<y.

In some of the embodiments, the substrate 10 is one of a sapphire substrate, a SiC substrate and a SiO ₂ substrate.

In specific implementation, the barrier energy level is provided by the first sublayer 50 to block the migration of electrons, and the D element in the second sublayer 60 can be used to insert or fill the vacant positions caused by dislocations, which not only suppresses the dislocations generated by line defects Extending, while reducing the probability of defect generation, it can also ensure that the fitting stress between the crystal lattices and the corresponding stress field are small, so as to improve the effective injection efficiency of holes, and then use the surface of the third sub-layer 70 effect to realize the efficient incorporation of magnesium atoms, that is, to use the desorption and thinning process of the surface layer of the third sublayer 70 to complete the desorption and thinning operation. The modulation of changes can effectively solve the core difficulty of ionization and activation of magnesium atoms, improve the effective activation and incorporation of magnesium atoms, and increase the generation of holes, thereby improving the luminous efficiency.

It should be noted that the above-mentioned implementation process is only to illustrate the practicability of the application, but this does not mean that the high-luminous-efficiency LED epitaxial wafer of the application has only the above-mentioned only one implementation process. On the contrary, as long as the application can be implemented The implementation of high-efficiency LED epitaxial wafers can all be included in the feasible implementation solutions of this application.

Please refer to FIG. 2, which is a method for preparing a high-efficiency LED epitaxial wafer in the second embodiment of the present invention, which is used to prepare a high-luminous-efficiency LED epitaxial wafer in the first embodiment. The method includes the following steps:

Step S101, obtaining a substrate 10;

Wherein, the substrate 10 may be one of a sapphire substrate, a SiC substrate and a SiO ₂ substrate.

Step S102, injecting nitrogen and hydrogen gas at the first ambient temperature to perform high temperature treatment on the substrate 10, and injecting a nitrogen source and an aluminum source into the MOCVD reaction chamber to process the substrate 10 after the high temperature treatment. 10 is deposited to obtain a buffer layer 20;

Wherein, performing high-temperature treatment on the substrate 10 can avoid oxidation or contamination on the surface of the substrate 10. It can be understood that the first ambient temperature is 1000°C-1150°C, and the high-temperature treatment is specifically , the substrate 10 is placed in a MOCVD (Metal-organic Chemical Vapor Deposition, metal-organic chemical vapor deposition) reaction chamber, and then at the first ambient temperature, high-purity ammonia gas and Nitrogen, and treat the substrate at high temperature for 10 minutes to 15 minutes.

It is supplemented that the substrate 10 after the high temperature treatment is transferred to a PVD (Physical Vapor Deposition, physical vapor deposition) reaction chamber, ammonia gas is introduced into the PVD reaction chamber, trimethylaluminum is used as a target material, and Using direct current to carry out magnetron sputtering on the substrate, to generate the buffer layer 20 with a thickness of 10nm-30nm, that is, using trimethylaluminum and ammonia as the aluminum source and nitrogen source respectively, the buffer layer 20 The material is aluminum nitride. It should be noted that, in this embodiment, the optimum thickness of the buffer layer 20 is 15 nm.

Step S103, at a second ambient temperature, doping silicon with a first doping concentration to form an N-type layer 30 on the buffer layer 20;

Wherein, the second ambient temperature is 1000°C-1150°C, the first doping concentration of silicon is 1.5+E18 atoms/cm ³ , the N-type layer 30 is a GaN layer, and the thickness of the N-type layer 30 is 2nm-3nm, specifically, transfer the substrate 10 with the buffer layer 20 into the MOCVD reaction chamber, under the environmental conditions of 1000°C and the first doping concentration of silicon element is 1.5+E18atoms/cm ³ , forming the N-type layer 30 with a thickness of 2.5 nm on the buffer layer 20, that is, the optimum thickness of the N-type layer 30 is 2.5 nm.

Step S104, under the third ambient temperature and the first ambient pressure, doping the aluminum element with the second doping concentration to form the active layer 40 in the N-type layer 30;

Wherein, the third ambient temperature is 800°C-900°C, the thickness of the active layer 40 is 3nm-3.5nm, and the active layer 40 includes alternately stacked InGaN quantum well layers and AlGaN quantum barrier layers, so The stacking period of the active layer 40 is 6-15, the growth temperature of the InGaN quantum well layer in the active layer 40 is 800° C. to 900° C., and the thickness of the InGaN quantum well layer is 3 nm to 3.5 nm, The growth temperature of the AlGaN quantum barrier layer is 850° C. to 900° C. and the growth pressure is 200 torr to 250 torr, and the thickness of the AlGaN quantum barrier layer is 9 nm to 12 nm, and the Al composition is 0.1.

In order to grow the active layer 40 smoothly, specifically, the ambient temperature in the MOCVD reaction chamber is 900° C., high-purity NH ₃ is used as the N source, TMIn provides the In source, and trimethylgallium (TMGa) and trimethylgallium (TMGa) Ethyl gallium (TEGa) is used as the source of gallium, and trimethylaluminum (TMAl) is used as the source of aluminum, and alternately stacked InGaN quantum well layers and AlGaN quantum barrier layers are formed on the N-type layer 30 by a vapor deposition method to obtain The active layer 40 is required.

Step S105, depositing an electron blocking layer on the active layer 40 by vapor deposition at a fourth ambient temperature and a second ambient pressure;

Wherein, the fourth ambient temperature is 900°C-1000°C, the second ambient pressure is 100torr-200torr, and the electron blocking layer includes a first sublayer 50 and a second sublayer stacked on the active layer. layer 60 and a third sublayer 70 .

Step S106 , under the fifth ambient temperature and the third ambient pressure, doping magnesium with a third doping concentration to deposit a P-type layer 80 on the electron blocking layer.

Wherein, the P-type layer 80 is a GaN layer, and the growth conditions of the P-type layer 80 are: the growth temperature is 1000°C-1100°C, the growth pressure is 100torr-600torr, and the doping concentration of magnesium is 1E+19 atoms/cm ³ ~5E+20 atoms/cm ³ . Under the above growth conditions, the P-type layer 80 with a thickness of 20nm-200nm can be grown on the electron blocking layer, that is, the fifth ambient temperature is 1000°C-1100°C, and the third ambient pressure is 100torr-600torr, the third doping concentration is 1E+19 atoms/cm ³ ~5E+20 atoms/cm ³ , wherein the optimum value of the fifth ambient temperature is 1050°C, and the third ambient pressure The optimum value is 200 torr, and the optimum value of the third doping concentration is 5E+19 atoms/cm ³ .

Specifically, under the growth conditions of a growth temperature of 1050° C., a growth pressure of 200 torr, and a magnesium doping concentration of 5E+19 atoms/cm ³ , the P with a thickness of 100 nm is grown on the electron blocking layer. Type layer 80, it can be understood that if the doping concentration of magnesium is too high, the crystal quality will be damaged, while if the doping concentration is low, the hole concentration will be affected.

Through the above steps, the first sublayer 50 is used to provide a potential barrier energy level to block the migration of electrons, and the D element in the second sublayer 60 can be used to insert or fill the vacant positions caused by dislocations, which not only suppresses the extension of dislocations caused by line defects , while reducing the probability of defect generation, it can also ensure that the fitting stress between the lattices and the corresponding stress field are small, so as to improve the effective injection efficiency of holes, and then use the surface effect of the third sublayer 70 To achieve efficient incorporation of magnesium atoms, that is, to use the process of desorption and thinning of the surface layer of the third sublayer 70, so that the surface structure of the desorption and thinning operation is used as a barrier layer, and the periodic change of Al composition along the growth direction is realized Modulation, so as to effectively solve the core difficulty of ionization and activation of magnesium atoms, improve the effective activation and incorporation of magnesium atoms, increase the generation of holes, and thus improve the luminous efficiency.

In some of these embodiments, the step of depositing an electron blocking layer on the active layer 40 by vapor deposition method includes:

The nitrogen source, the aluminum source, the boron source and the gallium source are passed into the MOCVD reaction chamber, and the first sub-layer 50, the second sub-layer 60 and the third sub-layer are sequentially formed on the active layer 40 by vapor deposition. Sub-layer 70, then stop feeding the aluminum source and the gallium source, and desorb and thin the surface layer of the third sub-layer 70, so as to obtain the P-type _{AlxGa1 -xN} thinned layer 72 and D _y Ga _1-y N thinned layer 73 .

Wherein, the first sublayer 50 is an AlN layer, and the first sublayer 50 is used to provide a better barrier level; the second sublayer 60 is a DGaN/DAlGaN superlattice layer, and the DGaN/DAlGaN The superlattice _layer includes DGaN layers 61 and DAlGaN layers 62 stacked alternately periodically, both of which are superlattice structures; the third sublayer 70 includes P-type _AlxGa1 stacked in sequence _-x N/D _y Ga _1-y N superlattice layer 71, P-type Al _x Ga _1-x N thinned layer 72 and D _y Ga _1-y N thinned layer 73, P-type Al _x Ga _{1- The x} N/D _y Ga _1-y N superlattice layer 71 includes P-type Al _x Ga _1-x N layers 711 and D _y Ga _1-y N layers 712 that are periodically and alternately stacked.

It can be understood that the P-type _{AlxGa1 -xN} thinned layer 72 and the _{DyGa1 -yN} thinned layer 73 are obtained by desorbing and thinning the surface layer of the pre-formed third sublayer 70, Specifically, the surface layer of the third sublayer 70 is desorbed and thinned. Due to the fact that Ga atoms in the AlGaN system are more easily desorbed than Al atoms, the surface layer of the third sublayer spontaneously transforms into sub-nanometer-thick P-type Al. _x Ga _1-x N thinned layer 72 and D _y Ga _1-y N thinned layer 73, the remaining structure in the third sublayer 70 that has not been desorbed and thinned is P-type Al _x Ga _1-x N/D _y Ga _1-y N superlattice layer 71, thereby the concentration of the gallium component in P-type Al _x Ga _1-x N thinned layer 72 and D _y Ga _1-y N thinned layer 73 is respectively lower than that of P-type The concentration of the gallium component in the _{AlxGa1 -xN} layer 711 and the _{DyGa1 -yN} layer 712, and the thickness of the P-type _{AlxGa1 -xN} thinned layer 72 is smaller than that of the P-type _AlxGa1 -xN layer _{712. -} the thickness of the x N layer 711, the thickness of the D _y Ga _1-y N thinned layer 73 is less than the thickness of the D _y Ga _1-y N layer 712, it should be noted that D is at least one of boron, indium or carbon kind.

In some of these embodiments, the thickness of the first sublayer 50 is 4nm-6nm. If the thickness is less than 4nm, it is difficult to prevent the migration of electrons, and it is impossible to ensure that the potential energy can be regulated by the quality of the crystal, and defects are likely to occur, so that it cannot be effectively improved. The effective hole injection efficiency, if the thickness is greater than 6nm, will increase the operating voltage of the product, which is not conducive to improving the luminous efficiency. For example, the thickness of the first sub-layer 50 is 4nm, 5nm or 6nm.

In some of these embodiments, the thicknesses of the DGaN layer 61 and the DAlGaN layer 62 are both 4nm-6nm, and the thicknesses of the P-type _{AlxGa1 -xN} layer 711 and the _{DyGa1 -yN} layer 712 are both 3nm-4nm .

Wherein, when the thicknesses of the DGaN layer 61 and the DAlGaN layer 62 are both less than 4nm, due to being too thin, the amount of D may not be enough during the stress process generated by the twisted interface, and it is difficult to fill most of the vacant positions caused by dislocations, and the required Needed requirements; when the thickness of the DGaN layer 61 and the DAlGaN layer 62 are greater than 6nm, then relatively too thick, it is not easy to twist the stress generated by the interface; and, when the P-type Al _x Ga _1-x N layer 711 and When the thickness of the D _y Ga _1-y N layer 712 is less than 3nm, it is not conducive to improving the effective activation and incorporation of magnesium, and it is not conducive to improving the generation of holes. When the P-type Al _x Ga _1-x N layer 711 and D _y When the thickness of the Ga _1-y N layer 712 is greater than 4 nm, it is difficult to control the crystal quality, which is not conducive to improving the luminous efficiency.

It should be noted that the optimal thickness of the first sublayer 50 is 5 nm, the optimal thickness of the DGaN layer 61 and the DAlGaN layer 62 are both 5 nm, and the P-type Al _x Ga _1-x N layer 711 and D _y Ga _1-y The optimal thickness of the N layer 712 is 3.5nm. Experiments have shown that when the first sublayer, the DGaN layer 61, the DAlGaN layer 62, the P-type _{AlxGa1 -xN} layer 711 and the _{DyGa1 -yN} layer 712 are all at the optimum thickness, the light produced by them Efficiency is optimal.

It can be understood that since the DGaN layer 61 and the DAlGaN layer 62 in the second sub-layer 60 are relatively thin, the stress generated by the interface can be continuously distorted, thereby reducing the occurrence of defects.

In some of these embodiments, the DGaN layer 61 and the DAlGaN layer 62 are alternately stacked at a period of 2-3, and the P-type Al _x Ga _1-x N layer 711 and the D _y Ga _1-y N layer 712 in the combined structure are alternately stacked The cycle is 3-4.

In some of these embodiments, the Al element in the P-type Al _x Ga _1-x N layer 711 gradually decreases with the period, the thickness of the Dy _{Ga 1-y} N layer 712 gradually increases with the period, and the P-type Al _x Ga ₁ The doping degree of the Mg element in the _-x N layer 711 is 1E+16 atoms/cm ³ -2E+17 atoms/cm ³ .

In some of these embodiments, the value ranges of x and y in the P-type Al _x Ga _1-x N layer 711 and Dy _{Ga 1-y} N layer 712 are: 0≤x≤1, 0≤y≤1 , and x<y.

In a specific embodiment, the following test examples are given for illustration:

In this test, a traditional LED epitaxial wafer was used as the control group. The structure of the traditional LED epitaxial wafer is basically the same as that of the high-efficiency LED epitaxial wafer of the present application. The difference is that the electron blocking layer is a traditional structure, and Its thickness is 50 nm.

Set up 6 test groups, namely test group 1, test group 2, test group 3, test group 4, test group 5 and test group 6.

Wherein, the structure in the test group 1 is basically the same as the structure in the present application, the difference is that the thickness of the first sub-layer 50 in the electron blocking layer is 5nm, and the thickness of the DGaN layer 61 and the DAlGaN layer 62 are both 4nm , and the DGaN layer 61 and the DAlGaN layer 62 are alternately stacked at a period of 3, the thickness of the P-type Al _x Ga _1-x N layer 711 and the D _y Ga _1-y N layer 712 are both 3nm, and the P-type Al _x Ga _{1 -x} N layers 711 and D _y Ga _1-y N layers 712 are alternately stacked at a period of 3, and D is boron;

The structure in the test group 2 is basically the same as the structure in the test group 1, the difference is that D in the D _y Ga _1-y N layer 712 is indium;

The structure in test group 3 is basically the same as that in test group 1, except that the thickness of the P-type _{AlxGa1 -xN} layer 711 and the P-type _{DyGa1 -yN} layer 712 is 3.5nm , and the alternate stacking period of the P-type Al _x Ga _1-x N layer 711 and the P-type D _y Ga _1-y N layer 712 is 4;

The structure of the test group 4 is basically the same as that in the test group 3, except that D in the D _y Ga _1-y N layer 712 is indium;

The structure of the test group 5 is basically the same as that in the test group 3, except that the thicknesses of the DGaN layer 61 and the DAlGaN layer 62 are both 5 nm.

The structure of test group 6 is basically the same as that in test group 5, except that the thickness of the first sublayer 50 is 4 nm.

Optical tests were carried out on the control group, test group 1, test group 2, test group 3, test group 4, test group 5 and test group 6 respectively. According to the test results, the light efficiency of the LED epitaxial wafers has improved, as shown in the table below Show:

The LED in the third embodiment of the present invention includes the high-efficiency LED epitaxial wafer described above.

In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structure, material or characteristic is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The above-mentioned embodiments only express several implementation modes of the present invention, and the description thereof is relatively specific and detailed, but should not be construed as limiting the patent scope of the present invention. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the appended claims.

Claims (10)

1. A high-efficiency LED epitaxial wafer, comprising a substrate, a buffer layer, an N-type layer, an active layer, an electron blocking layer and a P-type layer stacked in sequence, wherein the electron blocking layer comprises The first sublayer, the second sublayer and the third sublayer on the active layer; The first sublayer is an AlN layer, the second sublayer is a DGaN/DAlGaN superlattice layer, and the third sublayer includes a P-type Al _x Ga _1-x N/D _y Ga _1-y N superlattice layer. lattice layer, P-type Al _x Ga _1-x N thinned layer and D _y Ga _1-y N thinned layer; The DGaN/DAlGaN superlattice layer includes periodically alternately stacked DGaN layers and DAlGaN layers, and the P-type _{AlxGa1 - xN} / _{DyGa1 -yN} superlattice layer includes periodically alternately stacked P-type Al _x Ga _1-x N layer and D _y Ga _1-y N layer, the thickness of the P-type Al _x Ga _1-x N thinned layer is less than that of the P-type Al _x Ga _1-x N layer thickness, the thickness of the D _y Ga _1-y N thinned layer is less than the thickness of the D _y Ga _1-y N layer; Wherein, D is at least one of boron, indium or carbon. 2. The high light efficiency LED epitaxial wafer according to claim 1, wherein the thickness of the first sub-layer is 4nm-6nm, the thickness of the DGaN layer and the DAlGaN layer are both 4nm-6nm, so The thicknesses of the P-type _{AlxGa1 -xN} layer and the _{DyGa1 -yN} layer are both 3nm-4nm. 3. The high-luminous-efficiency LED epitaxial wafer according to claim 1, wherein the Al element in the P-type _{AlxGa1 -xN} layer gradually decreases with the cycle, and the _{DyGa1 -yN} layer The thickness of the P-type _{AlxGa1 -xN} layer gradually increases with the period, and the doping degree of the Mg element in the P-type AlxGa1-xN layer is 1E+16 atoms/cm ³ ~2E+17 atoms/cm ³ . 4. The high-luminous-efficiency LED epitaxial wafer according to claim 3, characterized in that, the value ranges of x and y in the P-type Al _x Ga _1-x N layer and the D _y Ga _1-y N layer They are: 0≤x≤1, 0≤y≤1, and x<y. 5. The high-luminous-efficiency LED epitaxial wafer according to claim 1, characterized in that, the period of alternating stacking of the DGaN layer and the DAlGaN layer is 2-3, and the P-type _{AlxGa1 -xN} layer and The alternating stacking period of the D _y Ga _1-y N layers is 3-4. 6. The high light efficiency LED epitaxial wafer according to claim 1, characterized in that the gallium group in the P-type _{AlxGa1 -xN} thinned layer and the _{DyGa1 -yN} thinned layer The concentration of the component is lower than the concentration of the gallium component in the P-type _{AlxGa1 -xN} layer and the _{DyGa1 -yN} layer, respectively. 7. The high-efficiency LED epitaxial wafer according to claim 1, wherein the substrate is one of a sapphire substrate, a SiC substrate and a _SiO2 substrate. 8. A preparation method for preparing the high-luminous-efficiency LED epitaxial wafer according to any one of claims 1-7, characterized in that the method comprises: acquire a substrate; Nitrogen gas and hydrogen gas are fed into the first ambient temperature to perform high temperature treatment on the substrate, and a nitrogen source and an aluminum source are fed into the MOCVD reaction chamber to obtain buffer deposits on the substrate after the high temperature treatment layer; Doping silicon with a first doping concentration at a second ambient temperature to form an N-type layer on the buffer layer; Doping aluminum elements with a second doping concentration at a third ambient temperature and a first ambient pressure to form an active layer in the N-type layer; Depositing an electron blocking layer on the active layer by vapor deposition at a fourth ambient temperature and a second ambient pressure; Under the fifth ambient temperature and the third ambient pressure, magnesium element with a third doping concentration is doped to deposit a P-type layer on the electron blocking layer. 9. The method for preparing a high-efficiency LED epitaxial wafer according to claim 8, wherein the step of depositing an electron blocking layer on the active layer by vapor deposition comprises: The nitrogen source, the aluminum source, the boron source and the gallium source are passed into the MOCVD reaction chamber, and the first sublayer, the second sublayer and the third sublayer are sequentially formed on the active layer by vapor deposition, Then stop feeding the aluminum source and the gallium source, and desorb and thin the surface layer of the third sublayer to obtain a P-type _{AlxGa1 -xN} thinned layer and _{DyGa1 -y} N thinned layer. 10. An LED, characterized in that it comprises the high-luminous-efficiency LED epitaxial wafer according to any one of claims 1-8.