CN110718612A - Light emitting diode epitaxial wafer and manufacturing method thereof - Google Patents

Abstract

The invention discloses a light-emitting diode epitaxial wafer and a manufacturing method thereof, belonging to the technical field of semiconductors. Each quantum well layer of the multiple quantum well layer of the light-emitting diode epitaxial wafer includes a first quantum well sublayer, a second quantum well sublayer and a third quantum well sublayer that are stacked in sequence, and the In/ The Ga ratio is greater than or equal to the In/Ga ratio of the first quantum well sublayer and the third quantum well sublayer; the first quantum well sublayer is doped with Si; each quantum barrier layer includes sequentially stacked first quantum barrier sublayers , the second quantum barrier sublayer and the third quantum barrier sublayer; the Si/Ga ratio of the second quantum barrier sublayer is greater than or equal to the Si/Ga ratio of the first quantum barrier sublayer and the third quantum barrier sublayer. The light emitting diode epitaxial wafer can improve the energy band inclination phenomenon in the multiple quantum well layer, increase the overlapping degree of the wave functions of electrons and holes in the spatial distribution, and improve the internal quantum efficiency of the LED.

Description

Light-emitting diode epitaxial wafer and manufacturing method thereof

technical field

The present invention relates to the technical field of semiconductors, in particular to a light emitting diode epitaxial wafer and a manufacturing method thereof.

Background technique

GaN (gallium nitride) is one of the materials for making LED (Light Emitting Diode, light emitting diode) epitaxial wafers. GaN is an extremely stable compound and a hard high melting point material, and is also a direct transition wide band gap semiconductor material. physical and chemical properties, and has a high electron saturation rate. It has the characteristics of good thermal conductivity, large broadband forbidden and small dielectric constant and strong anti-irradiation ability, which can be used to prepare high-power devices with good stability, long life, corrosion resistance and high temperature resistance.

Typically, GaN-based LEDs are epitaxially grown on sapphire substrates. Traditional GaN-based LED epitaxial structures generally use InGaN/GaN superlattice structures as multiple quantum well layers. However, there is a large lattice mismatch between the InGaN layer and the GaN layer, resulting in a large compressive stress between the InGaN layer and the GaN layer. The compressive stress will generate a piezoelectric polarization electric field, which reduces the overlap of the wave functions of electrons and holes, leading to the inclination of the energy band of the multiple quantum well layer, resulting in a decrease in the internal quantum efficiency, thus affecting the luminous efficiency of LEDs.

SUMMARY OF THE INVENTION

The embodiments of the present invention provide a light-emitting diode epitaxial wafer and a manufacturing method thereof, which can improve the energy band tilt phenomenon in the multiple quantum well layer, increase the overlap of the wave functions of electrons and holes in the spatial distribution, and improve the internal efficiency of the LED. quantum efficiency. The technical solution is as follows:

In one aspect, a light-emitting diode epitaxial wafer is provided, the light-emitting diode epitaxial wafer includes a substrate, and a buffer layer, an undoped GaN layer, an N-type layer, and a multiple quantum well layer sequentially stacked on the substrate , an electron blocking layer, a P-type layer and a P-type contact layer, the multiple quantum well layer comprising alternately grown quantum well layers and quantum barrier layers,

Each of the quantum well layers includes a first quantum well sublayer, a second quantum well sublayer and a third quantum well sublayer stacked in sequence, the first quantum well sublayer, the second quantum well sublayer and the third quantum well sublayer The three quantum well sublayers are all InGaN layers, and the In/Ga ratio of the second quantum well sublayer is greater than or equal to the In/Ga ratio of the first quantum well sublayer and the third quantum well sublayer; the The first quantum well sublayer is doped with Si, and the doping concentration of Si in the first quantum well sublayer is 1*10 ¹⁷ cm ^-3 to 3*10 ¹⁷ cm ^-3 ;

Each of the quantum barrier layers includes a first quantum barrier sublayer, a second quantum barrier sublayer and a third quantum barrier sublayer stacked in sequence, the first quantum barrier sublayer, the second quantum barrier sublayer and the third quantum barrier sublayer The three quantum barrier sublayers are all Si-doped GaN layers, and the doping concentration of Si in the quantum barrier sublayer is 3*10 ¹⁷ cm ^-3 to 5*10 ¹⁷ cm ^-3 ; the second quantum barrier sublayer The Si/Ga ratio of is greater than or equal to the Si/Ga ratio of the first quantum barrier sublayer and the third quantum barrier sublayer.

Further, the thickness ratio of the first quantum well sublayer, the second quantum well sublayer and the third quantum well sublayer is 1:m:1, 4≤m≤6, and m is a positive integer.

Further, the thickness ratio of the first quantum barrier sublayer, the second quantum barrier sublayer and the third quantum barrier sublayer is 1:n:1, 4≤n≤6, and n is a positive integer.

Further, the Si/Ga ratio of the first quantum barrier sublayer gradually increases with the increase of the thickness, the Si/Ga ratio of the second quantum barrier sublayer is constant, and the third quantum barrier sublayer The Si/Ga ratio gradually decreases with increasing thickness.

Further, the Si/Ga ratio of the first quantum well sublayer gradually decreases as the thickness increases.

Further, the maximum value of the Si/Ga ratio of the first quantum well sublayer is 20-30% of the Si/Ga ratio of the second quantum barrier sublayer, and the Si/Ga ratio of the first quantum barrier sublayer is 20-30%. The minimum value of the Ga ratio is 20-30% of the Si/Ga ratio of the second quantum barrier sublayer, and the minimum value of the Si/Ga ratio of the third quantum barrier sublayer is the second quantum barrier sublayer 20 to 30% of the Si/Ga ratio.

In another aspect, a method for manufacturing a light-emitting diode epitaxial wafer is provided, the manufacturing method comprising:

providing a substrate;

growing a low temperature buffer layer, an undoped GaN layer, an N-type layer, a multiple quantum well layer, an electron blocking layer, a P-type layer and a P-type contact layer on the substrate in sequence;

The multiple quantum well layers include alternately grown quantum well layers and quantum barrier layers, and each of the quantum well layers includes a first quantum well sublayer, a second quantum well sublayer and a third quantum well layered in sequence sublayer, the first quantum well sublayer, the second quantum well sublayer and the third quantum well sublayer are all InGaN layers, and the In/Ga ratio of the second quantum well sublayer is greater than that of the first quantum well In/Ga ratio of the sublayer and the third quantum well sublayer; Si is doped in the first quantum well sublayer, and the doping concentration of Si in the first quantum well sublayer is 1*10 ¹⁷ cm ^-3 to 3*10 ¹⁷ cm ^-3 ;

Each of the quantum barrier layers includes a first quantum barrier sublayer, a second quantum barrier sublayer and a third quantum barrier sublayer stacked in sequence, the first quantum barrier sublayer, the second quantum barrier sublayer and the third quantum barrier sublayer The three quantum barrier sublayers are all Si-doped GaN layers, and the doping concentration of Si in the quantum barrier sublayer is 3*10 ¹⁷ cm ^-3 to 5*10 ¹⁷ cm ^-3 ; the second quantum barrier sublayer The Si/Ga ratio of is greater than the Si/Ga ratio of the first quantum barrier sublayer and the third quantum barrier sublayer.

Further, the growth temperature of the first quantum well sublayer and the third quantum well sublayer are both greater than or equal to the growth temperature of the second quantum well sublayer.

Further, the growth temperatures of the first quantum barrier sublayer and the third quantum barrier sublayer are both less than or equal to the growth temperature of the second quantum barrier sublayer.

Further, the Si/Ga ratio of the first quantum well sublayer gradually decreases as the thickness increases.

The beneficial effects brought by the technical solutions provided in the embodiments of the present invention are:

By dividing each quantum well layer into three sublayers, and the In/Ga ratio of the second quantum well sublayer is greater than or equal to the In/Ga ratio of the first quantum well sublayer and the third quantum well sublayer, therefore, the second quantum well The In content in the sublayer is relatively high, which can be used as the main light-emitting layer to ensure the light-emitting efficiency of the LED. The content of In in the first quantum well sublayer and the third quantum well sublayer is low, and they are in contact with the quantum barrier layer, which can reduce the lattice mismatch between the quantum well layer and the quantum barrier layer, thereby reducing compressive stress. At the same time, the first quantum well sublayer is doped with a small amount of Si, which can increase the electron concentration in the quantum well layer, thereby improving the energy band tilt phenomenon of the multiple quantum well layer and increasing the overlap of the spatial distribution of the wave functions of electrons and holes. degree, improve the internal quantum efficiency of LED. And since Si is an impurity, doping Si in the quantum well layer will affect the crystal quality of the well layer, and the first quantum well sublayer is not the main light-emitting layer. Therefore, doping Si in the first quantum well sublayer can reduce Si. The influence of impurity doping on the crystal quality of the well layer ensures the luminous efficiency of the well layer. Further, by dividing the quantum barrier layer into three sublayers, and the Si/Ga ratio of the second quantum barrier sublayer is greater than or equal to the Si/Ga ratio of the first quantum barrier sublayer and the third quantum barrier sublayer, that is, the same as the quantum well. The doping concentration of Si in the first quantum barrier sublayer and the third quantum barrier sublayer in contact with each other is less, which can ensure the crystal quality of the first quantum barrier sublayer and the third quantum barrier sublayer, thereby improving the well barrier. The interface quality between the two can further improve the luminous efficiency of the LED.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

1 is a schematic structural diagram of a light-emitting diode epitaxial wafer provided by an embodiment of the present invention;

2 is a schematic structural diagram of a multiple quantum well layer provided by an embodiment of the present invention;

3 is a method flowchart of a method for manufacturing a light-emitting diode epitaxial wafer provided by an embodiment of the present invention;

Fig. 4 is the energy band schematic diagram of the existing multiple quantum well layer;

FIG. 5 is a schematic diagram of an energy band of a multiple quantum well layer provided by an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

An embodiment of the present invention provides a light-emitting diode epitaxial wafer. FIG. 1 is a schematic structural diagram of a light-emitting diode epitaxial wafer provided by an embodiment of the present invention. As shown in FIG. 1 , the light-emitting diode epitaxial wafer includes a substrate 1, and is stacked in sequence Buffer layer 2, undoped GaN layer 3, N-type layer 4, multiple quantum well layer 5, low temperature P-type layer 6, electron blocking layer 7, high temperature P-type layer 8 and P-type contact layer on substrate 1 9.

2 is a schematic structural diagram of a multiple quantum well layer provided by an embodiment of the present invention. As shown in FIG. 2 , the multiple quantum well layer 5 includes multiple quantum well layers 51 and multiple quantum barrier layers 52 grown alternately.

Each quantum well layer 51 includes a first quantum well sublayer 511 , a second quantum well sublayer 512 and a third quantum well sublayer 513 that are sequentially stacked. The first quantum well sublayer 511 , the second quantum well sublayer 512 and the third quantum well sublayer 513 are all InGaN layers. The In/Ga ratio of the second quantum well sublayer 512 is greater than or equal to the In/Ga ratio of the first quantum well sublayer 511 and the third quantum well sublayer 513 . The first quantum well sublayer 511 is doped with Si, and the doping concentration of Si in the first quantum well sublayer 511 is 1*10 ¹⁷ cm ^-3 to 3*10 ¹⁷ cm ^-3 .

Each quantum barrier layer 52 includes a first quantum barrier sublayer 521 , a second quantum barrier sublayer 522 and a third quantum barrier sublayer 523 stacked in sequence, the first quantum barrier sublayer 521 and the second quantum barrier sublayer 522 and the third quantum barrier sublayer 523 are both Si-doped GaN layers, and the doping concentration of Si in the quantum barrier sublayer is 3*10 ¹⁷ cm ^-3 to 5*10 ¹⁷ cm ^-3 ; the second quantum barrier sublayer 522 The Si/Ga ratio is greater than or equal to the Si/Ga ratio of the first quantum barrier sublayer 521 and the third quantum barrier sublayer 523 .

It should be noted that the In/Ga ratio represents the ratio of the doping concentration of In and the doping concentration of Ga, and the Si/Ga ratio represents the ratio of the doping concentration of Si and the doping concentration of Ga. In this embodiment, the doping concentrations of Ga in each quantum well sublayer and each quantum barrier sublayer are equal.

In the embodiment of the present invention, each quantum well layer is divided into three sublayers, and the In/Ga ratio of the second quantum well sublayer is greater than or equal to the In/Ga ratio of the first quantum well sublayer and the third quantum well sublayer. Therefore, The In content in the second quantum well sublayer is relatively high, which can be used as the main light-emitting layer to ensure the light-emitting efficiency of the LED. The content of In in the first quantum well sublayer and the third quantum well sublayer is low, and they are in contact with the quantum barrier layer, which can reduce the lattice mismatch between the quantum well layer and the quantum barrier layer, thereby reducing compressive stress. At the same time, the first quantum well sublayer is doped with a small amount of Si, which can increase the electron concentration in the quantum well layer, thereby improving the energy band tilt phenomenon of the multiple quantum well layer and increasing the overlap of the spatial distribution of the wave functions of electrons and holes. degree, improve the internal quantum efficiency of LED. And since Si is an impurity, doping Si in the quantum well layer will affect the crystal quality of the well layer, and the first quantum well sublayer is not the main light-emitting layer. Therefore, doping Si in the first quantum well sublayer can reduce Si. The influence of impurity doping on the crystal quality of the well layer ensures the luminous efficiency of the well layer. Further, by dividing the quantum barrier layer into three sublayers, and the Si/Ga ratio of the second quantum barrier sublayer is greater than or equal to the Si/Ga ratio of the first quantum barrier sublayer and the third quantum barrier sublayer, that is, the same as the quantum well. The doping concentration of Si in the first quantum barrier sublayer and the third quantum barrier sublayer in contact with each other is less, which can ensure the crystal quality of the first quantum barrier sublayer and the third quantum barrier sublayer, thereby improving the well barrier. The interface quality between the two can further improve the luminous efficiency of the LED.

In this embodiment, the multiple quantum well layer 5 may include 8-15 quantum well layers 51 and 8-15 quantum barrier layers 52 grown alternately.

Further, the thickness ratio of the first quantum well sublayer 511 , the second quantum well sublayer 512 and the third quantum well sublayer 513 is 1:m:1, 4≤m≤6, and m is a positive integer. Since the second quantum well sublayer is the main light-emitting layer, setting the thickness of the second quantum well sublayer to be thick can ensure the light-emitting brightness of each quantum well layer. At the same time, setting the first quantum well sub-layer to be thinner can prevent Si impurities from being doped into the first quantum well sub-layer, which affects the crystal quality of the entire well layer.

It should be noted that the specific thickness ratio of the first quantum well sublayer 511 , the second quantum well sublayer 512 and the third quantum well sublayer 513 can be selected according to the light emission wavelength of the desired LED device. The longer the light emission wavelength is, the more the total amount of In of the quantum well layer is required, and the thicker the thickness of the second quantum well sublayer can be set. The longer and shorter the light emission is, the less the total amount of In of the quantum well layer is required, and the thinner the thickness of the second quantum well sublayer can be set.

Exemplarily, when the light emission wavelength of the desired LED device is 460 nm˜470 nm, the thickness ratio of the first sublayer 511 , the second sublayer 512 and the third sublayer 513 may be set to 1:4:1. When the light emission wavelength of the desired LED device is 515 nm˜525 nm, the thickness ratio of the first sublayer 511 , the second sublayer 512 and the third sublayer 513 may be set to 1:5:1. When the emission wavelength of the desired LED device is 520 nm˜530 nm, the thickness ratio of the first sublayer 511 , the second sublayer 512 and the third sublayer 513 may be set to 1:6:1.

Optionally, the total thickness of each quantum well layer 51 may be 2˜3 nm. If the thickness of the quantum well layer 51 is less than 2 nm, the recombination emission of electrons and holes in the quantum well layer 51 may be affected because the thickness of the quantum well layer 51 is too small, thereby reducing the luminous efficiency of the LED. If the thickness of the quantum well layer 51 is greater than 3 nm, more stress may be generated in the quantum well layer 51 because the thickness of the quantum well layer 51 is too large, affecting the crystal quality of the quantum well layer 51 and thus the luminous efficiency of the LED.

Further, the thickness ratio of the first quantum barrier sublayer 521 , the second quantum barrier sublayer 522 and the third quantum barrier sublayer 523 is 1:n:1, 4≤n≤6, and n is a positive integer. Since the doping concentration of Si in the second quantum barrier sublayer is the highest, the second quantum barrier sublayer can act as a main blocking layer to block electron overflow. Therefore, by setting the thickness of the second quantum barrier layer to be thick, the overflow of electrons can be reduced.

Optionally, the total thickness of each quantum barrier layer 52 may be 9˜20 nm. If the thickness of the quantum barrier layer 52 is less than 9 nm, the effect of blocking electron overflow may not be achieved because the thickness of the quantum barrier layer 52 is too small. If the thickness of the quantum barrier layer 52 is greater than 20 nm, the normal migration of carriers is easily affected, the recombination of electrons and holes is blocked, and the luminous efficiency of the LED is reduced.

Further, the Si/Ga ratio of the first quantum barrier sublayer 521 gradually increases as the thickness increases, the Si/Ga ratio of the second quantum barrier sublayer 522 is constant, and the Si/Ga ratio of the third quantum barrier sublayer 521 is constant. The Ga ratio gradually decreases with increasing thickness. Then the doping concentration of Si in the first quantum barrier sublayer gradually increases, and the doping concentration of Si in the part in contact with the quantum well layer in the first quantum barrier sublayer is less, which is beneficial to improve the interface quality between the well barriers. . Similarly, the doping concentration of Si in the portion of the third quantum barrier sublayer in contact with the quantum well layer is gradually reduced, which is beneficial to improve the interface quality between the well barriers.

In this embodiment, the Si/Ga ratio of the first quantum barrier sublayer 511 is gradually increased to the Si/Ga ratio of the second quantum barrier sublayer 512, and the Si/Ga ratio of the third quantum barrier sublayer 513 is increased by the second quantum barrier sublayer 512. The Si/Ga ratio of the barrier layer is gradually reduced to form a smooth transition.

Further, the Si/Ga ratio of the first quantum well sublayer 511 gradually decreases as the thickness increases. Then, the doping concentration of Si in the portion of the first quantum well sublayer 511 close to the second quantum well sublayer 512 is less, which can reduce the influence of doping Si impurities on the second quantum well sublayer 512 .

Optionally, the maximum value of the Si/Ga ratio of the first quantum well sublayer is 20-30% of the Si/Ga ratio of the second quantum barrier sublayer. If the doping concentration of Si in the first quantum well sublayer is too low, the effect of improving the energy band inclination of the well layer cannot be achieved. If the doping concentration of Si in the first quantum well sublayer is too high, it will affect the quantum well. The crystal quality of the layer.

Further, the minimum value of the Si/Ga ratio of the first quantum barrier sublayer is 20-30% of the Si/Ga ratio of the second quantum barrier sublayer, and the minimum value of the Si/Ga ratio of the third quantum barrier sublayer is 20-30% of the Si/Ga ratio of the second quantum barrier layer. At this time, it can not only ensure that the quantum barrier layer can play a role in blocking electron overflow, but also can ensure the interface quality between the well barriers.

Alternatively, the substrate 1 may be a sapphire substrate.

Optionally, the buffer layer 2 may be an AlN layer with a thickness of 15-35 nm.

Optionally, the thickness of the undoped GaN layer 3 is 1˜3 μm.

Optionally, the N-type layer 4 may be a Si-doped GaN layer with a thickness of 1˜5 μm.

Optionally, the low-temperature P-type layer 6 may be a Mg-doped GaN layer with a thickness of 10-40 nm.

Optionally, the electron blocking layer 7 may be a Mg-doped AlGaN layer with a thickness of 20-30 nm, and the doping concentration of Mg is less than 1*10 ¹⁹ cm ⁻³ .

Optionally, the P-type layer 8 may be a Mg-doped GaN layer with a thickness of 10-30 nm, and the doping concentration of Mg is greater than or equal to 1*10 ²⁰ cm ⁻³ .

Optionally, the P-type contact layer 9 may be a heavily Mg-doped GaN layer with a thickness of 30-50 nm, and the doping concentration of Mg is greater than or equal to 1*10 ²⁰ cm ⁻³ ,

An embodiment of the present invention provides a method for manufacturing a light-emitting diode epitaxial wafer, which is used to manufacture the light-emitting diode epitaxial wafer provided in the first embodiment. FIG. 3 is a method flow of the method for manufacturing a light-emitting diode epitaxial wafer provided by an embodiment of the present invention. Figure, as shown in Figure 3, the manufacturing method includes:

Step 301, providing a substrate.

In this embodiment, the substrate is sapphire, and the substrate can be placed on a graphite tray and sent into a reaction chamber to grow epitaxial materials.

Step 301 also includes:

The temperature of the reaction chamber is controlled to be 1050° C., the pressure is 200 to 500 Torr, the sapphire substrate is annealed in a pure hydrogen atmosphere for 5 to 6 minutes, and then the sapphire substrate is subjected to nitridation treatment.

The present invention uses Veeco EPIK700 MOCVD to grow high-brightness GaN-based LED epitaxial wafers. Use high-purity H2 or high-purity N2 or a mixture of high-purity H2 and high-purity N2 as the carrier gas, high-purity NH3 as the N source, trimethylgallium (TMGa) and triethylgallium (TEGa) as the gallium source, and three Methyl indium (TMIn) was used as the indium source, silane (SiH4) was used as the N-type dopant, trimethylaluminum (TMAl) was used as the aluminum source, and dicocene (CP ₂ Mg) was used as the P-type dopant. The substrate was (0001) sapphire, the reaction chamber pressure is between 50torr and 600torr.

Step 302, growing a buffer layer on the substrate.

The buffer layer is an AlN layer.

Specifically, the substrate is placed in the reaction chamber of a PVD (Physical Vapor Deposition) equipment, and the AlN buffer layer is grown by the PVD method, including: adjusting the temperature in the reaction chamber of the PVD equipment to 400-700° C., sputtering The radiation power is adjusted to 3000-5000W, the pressure is adjusted to 1-10 mtorr, and an AlN buffer layer with a thickness of 15-35 nm is grown.

It should be noted that MOCVD (Metal-organic Chemical VaporDeposition, metal organic compound chemical vapor deposition) method growth. In the specific implementation, the substrate is usually placed on a graphite tray and sent to the reaction chamber of the MOCVD equipment for the growth of the epitaxial material. Therefore, the temperature and pressure controlled in the above-mentioned growth process actually refer to the temperature and pressure in the reaction chamber. Specifically, trimethyl gallium or trimethyl ethyl is used as the gallium source, triethyl boron as the boron source, high-purity ammonia gas as the nitrogen source, trimethyl indium as the indium source, trimethyl aluminum as the aluminum source, N Silane is selected as the type dopant, and magnesium locene is selected as the P type dopant.

Step 303 , growing an undoped GaN layer on the buffer layer.

Exemplarily, the temperature of the reaction chamber is controlled at 1000-1200° C., the pressure is controlled at 100-500 torr, and an undoped GaN layer with a thickness of 1-3um is grown.

Step 304 , growing an N-type layer on the undoped GaN layer.

The N-type layer is a Si-doped GaN layer, and the Si doping concentration can be 10 ¹⁸ cm ^-3 to 10 ¹⁹ cm ^-3 .

Exemplarily, the temperature of the reaction chamber is controlled at 1000-1200° C., the pressure is controlled at 100-300 torr, and an N-type GaN layer with a thickness of 1-5um is grown.

Step 305 , growing a multiple quantum well layer on the N-type layer.

In this embodiment, the multiple quantum well layer 5 may include 8-15 quantum well layers and 8-15 quantum barrier layers which are grown alternately.

Each quantum well layer includes a first quantum well sublayer, a second quantum well sublayer, and a third quantum well sublayer that are stacked in sequence. The first quantum well sublayer, the second quantum well sublayer and the third quantum well sublayer are all InGaN layers, and the In/Ga ratio of the second quantum well sublayer is greater than or equal to the first quantum well sublayer and the third quantum well sublayer The In/Ga ratio of the layer. The first quantum well sublayer is doped with Si, and the doping concentration of Si in the first quantum well sublayer is 1*10 ¹⁷ cm ^-3 to 3*10 ¹⁷ cm ^-3 .

Each quantum barrier layer includes a first quantum barrier sublayer, a second quantum barrier sublayer and a third quantum barrier sublayer that are stacked in sequence. The first quantum barrier sublayer, the second quantum barrier sublayer and the third quantum barrier sublayer are all Si-doped GaN layers, and the doping concentration of Si in the quantum barrier sublayer is 3*10 ¹⁷ cm ^-3 to 5*10 ¹⁷ cm ^-3 . The Si/Ga ratio of the second quantum barrier sublayer is greater than or equal to the Si/Ga ratio of the first quantum barrier sublayer and the third quantum barrier sublayer.

It should be noted that the In/Ga ratio represents the ratio of the doping concentration of In and the doping concentration of Ga, and the Si/Ga ratio represents the ratio of the doping concentration of Si and the doping concentration of Ga. In this embodiment, the doping concentrations of Ga in each quantum well sublayer and each quantum barrier sublayer are equal.

Further, the thickness ratio of the first quantum well sublayer, the second quantum well sublayer and the third quantum well sublayer is 1:m:1, 4≤m≤6, and m is a positive integer.

Optionally, the total thickness of each quantum well layer may be 2˜3 nm.

It should be noted that the specific thickness ratio of the first quantum well sublayer, the second quantum well sublayer and the third quantum well sublayer can be selected according to the light emission wavelength of the desired LED device.

Further, the thickness ratio of the first quantum barrier sublayer, the second quantum barrier sublayer and the third quantum barrier sublayer is 1:n:1, 4≤n≤6, and n is a positive integer.

Optionally, the total thickness of each quantum barrier layer may be 9-20 nm.

Further, the Si/Ga ratio of the first quantum barrier sublayer increases gradually with the increase of thickness, the Si/Ga ratio of the second quantum barrier sublayer is constant, and the Si/Ga ratio of the third quantum barrier sublayer increases with the increase of thickness. gradually decreases with increasing thickness.

Further, the Si/Ga ratio of the first quantum well sublayer gradually decreases as the thickness increases.

Further, the maximum value of the Si/Ga ratio of the first quantum well sublayer is 20-30% of the Si/Ga ratio of the second quantum barrier sublayer, and the minimum value of the Si/Ga ratio of the first quantum barrier sublayer is The Si/Ga ratio of the second quantum barrier sublayer is 20-30%, and the minimum value of the Si/Ga ratio of the third quantum barrier sublayer is 20-30% of the Si/Ga ratio of the second quantum barrier sublayer.

Optionally, the growth temperatures of the first quantum well sublayer and the third quantum well sublayer are both greater than or equal to the growth temperature of the second quantum well sublayer. Since low temperature is conducive to the incorporation of In, setting the growth temperature of the second quantum well sublayer to a lower value can be beneficial to increase the In/Ga ratio of the second quantum well sublayer, thereby reducing the luminous effect of the LED device. The half-wave width improves the luminous concentration and luminous intensity of the LED device.

In this embodiment, the growth temperature of the first quantum well sublayer is gradually reduced to the growth temperature of the second quantum well sublayer, the second quantum well sublayer is grown at a constant temperature, and the growth temperature of the third quantum well sublayer is changed from the second quantum well sublayer to the growth temperature of the second quantum well sublayer. The growth temperature of the well sublayer is gradually increased to form a smooth transition.

Optionally, the maximum growth temperature of the first quantum well sublayer is 30-50°C higher than the growth temperature of the second quantum well sublayer, and the maximum growth temperature of the third quantum well sublayer is higher than that of the second quantum well sublayer. The growth temperature of the layers is 30-50°C higher.

Exemplarily, the growth temperature of the first quantum well sublayer is gradually reduced from 830 to 840°C to 790 to 800°C, the growth temperature of the second quantum well sublayer is 790 to 800°C, and the growth temperature of the third quantum well sublayer is 790 to 800°C. It gradually increased from 790 to 800 °C to 830 to 840 °C.

Optionally, the growth temperatures of the first quantum well sublayer and the third quantum well sublayer are both greater than or equal to the growth temperature of the second quantum well sublayer. Since low temperature is conducive to the incorporation of In, setting the growth temperature of the second quantum well sublayer to a lower value can be beneficial to increase the In/Ga ratio of the second quantum well sublayer, thereby reducing the luminous effect of the LED device. The half-wave width improves the luminous concentration and luminous intensity of the LED device.

In this embodiment, the growth temperature of the first quantum barrier sublayer is gradually increased to the growth temperature of the second quantum barrier sublayer, the second quantum barrier sublayer is grown at constant temperature, and the growth temperature of the third quantum barrier sublayer is increased from the second quantum barrier sublayer to the growth temperature of the second quantum barrier sublayer. The growth temperature of the quantum barrier layer is gradually lowered to form a smooth transition.

Optionally, the maximum growth temperature of the first quantum barrier sublayer is 20-30° C. lower than the growth temperature of the second quantum barrier sublayer, and the maximum growth temperature of the third quantum barrier sublayer is lower than that of the second quantum barrier layer. The growth temperature of the layer is 30-30°C lower.

Exemplarily, the growth temperature of the first quantum barrier sublayer is gradually increased from 830-840°C to 850-870°C, the growth temperature of the second quantum barrier sublayer is 850-870°C, and the growth temperature of the third quantum barrier sublayer is 850-870°C. The temperature was gradually decreased from 850 to 870°C to 830 to 840°C.

At this time, the temperature difference between the contact portion of the quantum well layer and the quantum barrier layer is small, which can prevent the growth temperature of the quantum barrier layer from being high, damage the crystal quality of the quantum well layer, and protect the quantum well. At the same time, the precipitation of In in the quantum well can be reduced, and the luminous intensity of the LED device can be improved.

Optionally, the growth pressures of the quantum well layer and the quantum barrier layer are both 100-300 Torr.

Step 306 , growing a low temperature P-type layer on the multiple quantum well layer.

The low-temperature P-type layer may be a Mg-doped GaN layer with a thickness of 10-40um.

Exemplarily, the temperature of the reaction chamber is controlled at 700-800° C., the pressure is controlled at 100-600 Torr, and a low-temperature P-type layer with a thickness of 10-40 μm is grown.

Step 307 , growing an electron blocking layer on the low temperature P-type layer.

The electron blocking layer is a Mg-doped AlGaN layer, and the doping concentration of Mg in the electron blocking layer is less than 10 ¹⁹ cm ^-3 .

Exemplarily, the temperature of the reaction chamber is controlled at 900-1000° C., the pressure is controlled at 100-300 Torr, and an electron blocking layer with a thickness of 20-30 nm is grown.

Step 308 , growing a P-type layer on the electron blocking layer.

The P-type layer is a Mg-doped GaN layer, and the doping concentration of Mg in the P-type layer is greater than or equal to 10 ²⁰ cm ^-3 Exemplarily, the temperature of the reaction chamber is controlled at 900-980° C., and the pressure is controlled at 300-600 Torr , a P-type layer with a thickness of 10 to 30 nm is grown.

Step 309 , growing a P-type contact layer on the P-type layer.

The P-type contact layer may be a GaN layer heavily doped with Mg, and the doping concentration of Mg is greater than or equal to 1*10 ²⁰ cm ⁻³ .

Exemplarily, the temperature of the reaction chamber is controlled at 850-1050° C., the pressure is controlled at 100-600 Torr, and a P-type contact layer with a thickness of 30-50 nm is grown.

After the above steps are completed, the temperature of the reaction chamber is lowered to 650-850° C., annealed in a nitrogen atmosphere for 5-15 minutes, and then gradually lowered to room temperature to complete the epitaxial growth of the light-emitting diode.

FIG. 4 is a schematic diagram of an energy band of an existing multi-quantum well layer, and FIG. 5 is a schematic diagram of an energy band of a multi-quantum well layer provided by an embodiment of the present invention. As shown in FIGS. 4 and 5 , the multi-quantum well layer provided by the present invention Compared with the existing multi-quantum well layer, the energy band inclination degree of the energy band is improved, and the overlapping area of the spatial distribution of the wave functions of electrons and holes is increased.

In the embodiment of the present invention, each quantum well layer is divided into three sublayers, and the In/Ga ratio of the second quantum well sublayer is greater than or equal to the In/Ga ratio of the first quantum well sublayer and the third quantum well sublayer. Therefore, The In content in the second quantum well sublayer is relatively high, which can be used as the main light-emitting layer to ensure the light-emitting efficiency of the LED. The content of In in the first quantum well sublayer and the third quantum well sublayer is low, and they are in contact with the quantum barrier layer, which can reduce the lattice mismatch between the quantum well layer and the quantum barrier layer, thereby reducing compressive stress. At the same time, the first quantum well sublayer is doped with a small amount of Si, which can increase the electron concentration in the quantum well layer, thereby improving the energy band tilt phenomenon of the multiple quantum well layer and increasing the overlap of the spatial distribution of the wave functions of electrons and holes. degree, improve the internal quantum efficiency of LED. And since Si is an impurity, doping Si in the quantum well layer will affect the crystal quality of the well layer, and the first quantum well sublayer is not the main light-emitting layer. Therefore, doping Si in the first quantum well sublayer can reduce Si. The influence of impurity doping on the crystal quality of the well layer ensures the luminous efficiency of the well layer. Further, by dividing the quantum barrier layer into three sublayers, and the Si/Ga ratio of the second quantum barrier sublayer is greater than or equal to the Si/Ga ratio of the first quantum barrier sublayer and the third quantum barrier sublayer, that is, the same as the quantum well. The doping concentration of Si in the first quantum barrier sublayer and the third quantum barrier sublayer that are in contact with each other is less, which can ensure the crystal quality of the first quantum barrier sublayer and the third quantum barrier sublayer, thereby improving the well barrier. The interface quality between the two can further improve the luminous efficiency of the LED.

The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention. Inside.

Claims (10)

1. A light emitting diode epitaxial wafer comprises a substrate, and a buffer layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer, an electronic barrier layer, a P-type layer and a P-type contact layer which are sequentially laminated on the substrate, wherein the multi-quantum well layer comprises a quantum well layer and a quantum barrier layer which are alternately grown,

each quantum well layer comprises a first quantum well sub-layer, a second quantum well sub-layer and a third quantum well sub-layer which are sequentially stacked, the first quantum well sub-layer, the second quantum well sub-layer and the third quantum well sub-layer are all InGaN layers, and the In/Ga ratio of the second quantum well sub-layer is larger than or equal to that of the first quantum well sub-layer and that of the third quantum well sub-layer; the first quantum well sub-layer is doped with Si, and the doping concentration of Si in the first quantum well sub-layer is 1 x 10¹⁷cm^-3～3*10¹⁷cm^-3；

Each quantum barrier layer comprises a first quantum barrier layer, a second quantum barrier layer and a third quantum barrier layer which are sequentially stacked, the first quantum barrier layer, the second quantum barrier layer and the third quantum barrier layer are all Si-doped GaN layers, and the doping concentration of Si in the quantum barrier layers is 3 x 10¹⁷cm^-3～5*10¹⁷cm^-3(ii) a The Si/Ga ratio of the second quantum barrier layer is larger than or equal to the Si/Ga ratio of the first quantum barrier layer and the third quantum barrier layer.

2. The light emitting diode epitaxial wafer of claim 1, wherein the thickness ratio of the first quantum well sub-layer, the second quantum well sub-layer and the third quantum well sub-layer is 1: m: m is more than or equal to 1 and 4 and less than or equal to 6, and m is a positive integer.

3. The light emitting diode epitaxial wafer of claim 1, wherein the thickness ratio of the first quantum barrier layer, the second quantum barrier layer and the third quantum barrier layer is 1: n: n is more than or equal to 1 and 4 and less than or equal to 6, and n is a positive integer.

4. The light emitting diode epitaxial wafer of claim 1, wherein the Si/Ga ratio of the first quantum barrier layer gradually increases with increasing thickness, the Si/Ga ratio of the second quantum barrier layer is constant, and the Si/Ga ratio of the third quantum barrier layer gradually decreases with increasing thickness.

5. The light emitting diode epitaxial wafer of claim 1, wherein the Si/Ga ratio of the first quantum well sub-layer gradually decreases with increasing thickness.

6. The light-emitting diode epitaxial wafer according to claim 1, wherein the maximum value of the Si/Ga ratio of the first quantum well sub-layer is 20-30% of the Si/Ga ratio of the second quantum barrier sub-layer, the minimum value of the Si/Ga ratio of the first quantum barrier sub-layer is 20-30% of the Si/Ga ratio of the second quantum barrier sub-layer, and the minimum value of the Si/Ga ratio of the third quantum barrier sub-layer is 20-30% of the Si/Ga ratio of the second quantum barrier sub-layer.

7. A manufacturing method of a light emitting diode epitaxial wafer is characterized by comprising the following steps:

providing a substrate;

growing a low-temperature buffer layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer, an electronic barrier layer, a P-type layer and a P-type contact layer on the substrate in sequence;

the multiple quantum well layer comprises quantum well layers and quantum barrier layers which are alternately grown, each quantum well layer comprises a first quantum well sub-layer, a second quantum well sub-layer and a third quantum well sub-layer which are sequentially stacked, the first quantum well sub-layer, the second quantum well sub-layer and the third quantum well sub-layer are InGaN layers, and the In/Ga ratio of the second quantum well sub-layer is larger than that of the first quantum well sub-layer and that of the third quantum well sub-layer; the first quantum well sub-layer is doped with Si, and the doping concentration of Si in the first quantum well sub-layer is 1 x 10¹⁷cm^-3～3*10¹⁷cm^-3；

Each quantum barrier layer comprises a first quantum barrier layer, a second quantum barrier layer and a third quantum barrier layer which are sequentially stacked, the first quantum barrier layer, the second quantum barrier layer and the third quantum barrier layer are all Si-doped GaN layers, and the doping concentration of Si in the quantum barrier layers is 3 x 10¹⁷cm^-3～5*10¹⁷cm^-3(ii) a The Si/Ga ratio of the second quantum barrier layer is greater than the Si/Ga ratio of the first quantum barrier layer and the third quantum barrier layer.

8. The method of manufacturing according to claim 7, wherein the growth temperature of each of the first quantum well sub-layer and the third quantum well sub-layer is equal to or greater than the growth temperature of the second quantum well sub-layer.

9. The manufacturing method according to claim 7, wherein the growth temperature of each of the first quantum barrier layer and the third quantum barrier layer is equal to or lower than the growth temperature of the second quantum barrier layer.

10. The method of claim 7 wherein the Si/Ga ratio of the first quantum well sublayer decreases with increasing thickness.

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