CN116400568A - Method for correcting overlay error and method for manufacturing semiconductor element - Google Patents

Abstract

The present disclosure provides a method for correcting overlay errors. The correction method includes generating a first overlay error based on a first overlay mark, wherein the first overlay error indicates a misalignment between a lower pattern and an upper pattern of the first overlay mark, and in response to In detecting the abnormality of the first overlay error, generating a second overlay error based on a second overlay mark, and determining whether the abnormality in the first overlay error is caused by the lower pattern and the second overlay error based on the second overlay error This misalignment of the upper pattern causes.

Description

Method for correcting overlay error and method for manufacturing semiconductor element

cross reference

This application claims priority to US Patent Application Nos. 17/568,041 and 17/568,118 (ie, with a priority date of "January 4, 2022"), the contents of which are incorporated herein by reference in their entirety.

technical field

The disclosure relates to a method for correcting stacking errors and a method for manufacturing a semiconductor element.

Background technique

With the development of the semiconductor industry, it becomes more important to reduce the overlay error of the photoresist pattern and the underlying pattern in the photolithography operation. Due to various factors, such as the asymmetric shape of the measurement structure, it is more difficult to correctly measure the overlay error, so a new overlay marker and method are needed to measure the overlay error more accurately.

The above "prior art" description only provides background technology, and does not acknowledge that the above "prior art" description discloses the subject matter of the present disclosure, and does not constitute the prior art of the present disclosure, and the above "prior art" Any description should not be considered as any part of this disclosure.

Contents of the invention

One aspect of the present disclosure provides an overlay corrected marker. The mark includes a first pattern and a second pattern. The first pattern is disposed on a first surface of a base. The second pattern is disposed on a second surface of the base, and the second surface of the base is opposite to the first surface of the base. The first pattern overlaps at least a portion of the second pattern, and the first pattern and the second pattern together define a first overlay error.

Another aspect of the present disclosure provides an overlay corrected marker. The mark includes a first overlay mark and a second overlay mark. The first overlay mark includes a first pattern and a second pattern disposed on a first surface of a substrate. The first overlay mark is used to generate a first overlay error. The second overlay mark includes a third pattern disposed on a second surface of the substrate and a fourth pattern disposed on the first surface of the substrate. The first surface of the substrate is opposite to the second surface of the substrate. The second overlay mark is used to generate a second overlay error, and the second overlay mark is used to correct the first overlay error.

Another aspect of the present disclosure provides a method for correcting overlay errors. The method includes generating a first overlay error based on a first overlay mark, wherein the first overlay error indicates a misalignment between a lower pattern and an upper pattern of the first overlay mark, and, in response to Detecting the abnormality of the first overlay error, generating a second overlay error based on a second overlay mark, and determining whether the abnormality in the first overlay error is caused by the lower pattern and the This misalignment of the upper pattern is caused.

Another aspect of the present disclosure provides a method of manufacturing a semiconductor element. The preparation method includes providing a substrate having a first surface and an opposite second surface thereof, forming a first pattern on the first surface of the substrate, and forming a second pattern on the second surface of the substrate. pattern, forming an intermediate structure covering the second pattern, forming a third pattern on the second surface of the substrate, wherein the second pattern and the third pattern together define a first overlay error, and in the A fourth pattern is formed on the second surface of the substrate, wherein the first pattern and the fourth pattern jointly define a second overlay error.

Embodiments of the present disclosure provide overlay markers for overlay error measurement. Two overlay marks can be shared to determine whether anomalies in overlay errors are caused by misalignment of current and previous layers, or by wafer warpage. Using two measuring steps with two superimposed marks prevents inaccurate adjustments of the exposure equipment. Therefore, the usable time of the exposure equipment can be increased.

The foregoing has outlined rather broadly the technical features and advantages of the present disclosure so that the following detailed description of the disclosure can be better understood. Other technical features and advantages forming the subject of claims of the present disclosure will be described hereinafter. Those skilled in the art to which the present disclosure belongs should understand that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those skilled in the art to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure defined by the claims.

Description of drawings

A more complete understanding of the disclosure of this application can be obtained when the accompanying drawings are considered with reference to the embodiments and claims, in which like reference numerals refer to like elements.

FIG. 1 is a top view illustrating a wafer according to some embodiments of the present disclosure.

FIG. 2 is an enlarged view illustrating the dotted region in FIG. 1 of some embodiments of the present disclosure.

Figure 3 is a top view illustrating overlay markers of some embodiments of the present disclosure.

3A is a cross-sectional view along line AA' of FIG. 3 illustrating some embodiments of the present disclosure.

FIG. 3B is a cross-sectional view illustrating some embodiments of the present disclosure along line BB' of FIG. 3 .

Figure 4 is a top view illustrating overlay markers of some embodiments of the present disclosure.

FIG. 4A is a cross-sectional view along line CC' of FIG. 4 illustrating some embodiments of the present disclosure.

Figure 5 is a cross-sectional view illustrating an overlay marker of some embodiments of the present disclosure.

Figure 6 is a cross-sectional view illustrating overlay markers of some embodiments of the present disclosure.

Figure 7 is a cross-sectional view illustrating overlay markers of some embodiments of the present disclosure.

Figure 8 is a cross-sectional view illustrating overlay markers of some embodiments of the present disclosure.

9 is a block diagram illustrating a semiconductor fabrication system of some embodiments of the present disclosure.

10 is a flowchart illustrating a method of making an overlay marker of various aspects of the present disclosure.

FIG. 11 is a flowchart illustrating a method of correcting overlay errors of various aspects of the present disclosure.

12 is a diagram illustrating hardware of a semiconductor fabrication system of various aspects of the present disclosure.

Explanation of reference signs:

10: Wafer

21: Overlapping markers

22: Overlapping markers

30: Cutting Road

40: chip

100: base

100s1: surface

100s2: Surface

110: overlay mark

111: pattern

112: pattern

120a: overlay mark

120b: overlay mark

120c: overlay mark

121a: pattern

121b: pattern

121c: pattern

122: pattern

122': Features

130: Intermediate structure

140: mask

150: virtual layer

160a: overlay marker

160b: overlay marker

161a: Pattern

161b: pattern

162: pattern

170: Intermediate structure

180: mask

300: Semiconductor Manufacturing System

310: Manufacturing Equipment

320-1,…,320-N: manufacturing equipment

330: Manufacturing Equipment

340-1,…,340-N: manufacturing equipment

350: Exposure Equipment

360: Stacking Measurement Devices

370: Overlay (OVL) correction system

380: network

390: Controller

400: Preparation Methods

410: Operation

420: Operation

430: Operation

440: Operation

450: Operation

500: method

510: Operation

520: Operation

530: Operation

540: Operation

550: Operation

560: Operation

570: Operation

600: Semiconductor Manufacturing System

601: Processor

603: computer readable storage medium

605: bus

607: Input and output (I/O) interface

609: Network interface

610: User Interface

A-A': line

BB': line

C-C': line

X: direction

Y: Direction

Z: Direction

Detailed ways

Embodiments, or examples, of the present disclosure illustrated in the drawings will now be described in specific language. It should be understood that no limitation of the scope of the present disclosure is intended here. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are considered to be within the ordinary skill of the art to which this disclosure pertains. Reference numbers may be repeated throughout the embodiments, but there is no intention that features of one embodiment apply to another, even if they share the same reference number.

It will be understood that although the terms first, second, third etc. may be used to describe various elements, elements, regions, layers or sections. can be used to describe various elements, components, regions, layers or sections but these elements, components, regions, layers or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms "a", "an" and "the" are intended to include plural forms unless the context clearly dictates otherwise. It should be further understood that when the terms "comprising" and "comprising" are used in this specification, they point out the existence of the stated features, integers, steps, operations, elements or elements, but do not exclude the existence or addition of one or more other features, An integer, step, operation, element, component, or group thereof.

FIG. 1 is a top view illustrating a wafer 10 according to various aspects of the present disclosure, and FIG. 2 is an enlarged view of the dotted region in FIG. 1 .

As shown in FIGS. 1 and 2 , a wafer 10 is sawn into a plurality of chips 40 along a dicing street 30 . Each chip 40 may include semiconductor elements, which may include active elements and/or passive elements. Active components may include a memory chip (eg, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, etc.), a power management chip (eg, a power management integrated circuit (PMIC) chip), a Logic chips (e.g., system-on-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microcontroller, etc.), a radio frequency (RF) chip, a sensor chip , a micro-electro-mechanical system (MEMS) chip, a signal processing chip (such as a digital signal processing (DSP) chip), a front-end chip (such as an analog front-end (AFE) chip) or other active components. Passive components may include a capacitor, a resistor, an inductor, a fuse or other passive components.

As shown in FIG. 2 , overlay marks 21 and 22 may be provided on wafer 10 . In some embodiments, overlay marks 21 or 22 may be located on scribe line 30 . Overlay marks 21 or 22 may be provided on the corners of the edges of each chip 40 . In some embodiments, the overlay marks 21 or 22 may be located inside the chip 40 . In some embodiments, overlay markers 21 may be used to measure whether openings in a current layer, such as a photoresist layer, are precisely aligned with a previous layer in semiconductor processing. In some embodiments, the overlay mark 21 can be used to generate a first overlay error between the current layer (or upper layer) and the previous layer (or lower layer). In some embodiments, overlay marks 22 may be used to create a second overlay between two patterns (eg, the current pattern and the reference pattern) on two opposite sides of wafer 10 . In some embodiments, the overlay mark 22 can be utilized to correct the first overlay error generated from the overlay mark 21 . In some embodiments, the overlay mark 22 can be used to determine whether the abnormality (or abnormality) in the first overlay error generated from the overlay mark 21 is caused by the misalignment of the current layer and the previous layer. In some embodiments, overlay flag 22 may be utilized to determine whether an anomaly in the first overlay error is caused by warpage of the wafer. In some embodiments, the overlay marks 21 and 22 can be shared to determine the degree of warpage of the wafer 10 . In some embodiments, the overlay marks 21 and 22 may be shared to determine whether an abnormality in the first overlay error generated from the overlay mark 21 is caused by warpage of the wafer 10 .

FIG. 3 is a top view illustrating an overlay marker 110 for aligning different layers on a substrate 100 according to various aspects of the present disclosure. As shown in FIG. 3 , a semiconductor device structure, such as a wafer, may include overlay marks 110 on a substrate 100 . In some embodiments, the overlay mark 21 shown in FIG. 2 may include similar or identical patterns or structures as the overlay mark 110 in FIG. 3 .

The substrate 100 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. Substrate 100 may include an elemental semiconductor, including silicon or germanium in single crystal form, polycrystalline form, or amorphous (amorphous) form; a compound semiconductor material, including silicon carbide, gallium arsenide, gallium phosphide, phosphide At least one of indium, indium arsenide and indium antimonide. An alloy semiconductor material comprising at least one of SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloyed semiconductor substrate may be a SiGe alloy with a graded Ge feature, where the composition of Si and Ge changes from a ratio at one location of the graded SiGe feature to another. In another embodiment, a SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate 100 may have a multilayer structure, or the substrate 100 may include a multilayer compound semiconductor structure.

The overlay mark 110 may include a pattern 111 and a pattern 112 on the substrate 100 . The pattern 111 may be a pattern of a previous layer. The pattern 112 may be a layered pattern. The front floor (or lower floor) may be located at a different level from the current floor (or upper floor). Each pattern 111 (or pattern 112) can be located in one of four orthogonal destination areas, two for measuring overlay error in the X direction and two for measuring overlay error in the Y direction.

When using an overlay mark (such as the overlay mark 110 ) to measure an overlay error, the deviation in the X direction is measured along a straight line in the X direction of the overlay mark 110 . The deviation in the Y direction is further measured along a straight line in the Y direction of the overlay mark 110 . A single overlay mark, including patterns 111 and 112, can be used to measure the X-direction and Y-direction deviation between two layers on the substrate. Therefore, it can be determined whether the current layer and the previous layer are accurately aligned according to the deviation in the X direction and the Y direction. The overlay error may include a deviation in the X direction (ΔX), a deviation in the Y direction (ΔY), or a combination of both.

FIG. 3A is a cross-sectional view taken along line AA' of FIG. 3 .

As shown in FIGS. 3 and 3A , the substrate 100 may have a surface 100s1 and a surface 100s2 opposite to the surface 100s1 . The surface 100s2 of the substrate 100 may be an active surface on which an input and output terminal is disposed. The surface 100s1 of the substrate 100 may be a back surface. The pattern 111 may be disposed on the surface 100s1 of the substrate 100 . The pattern 111 may be disposed in or under the intermediate structure 130 . In some embodiments, the pattern 111 may include the same material as an isolation structure. In some embodiments, the pattern 111 may be disposed at the same level as the isolation structure. Isolation structures may include, for example, shallow trench isolation (STI), field oxidation (FOX), local oxidation of silicon (LOCOS) features, and/or other suitable isolation elements. The isolation structure may include a dielectric material such as silicon oxide, silicon nitride, silicon oxy-nitride, fluorine-doped silicate (FSG), a low-k dielectric material, combinations thereof, and/or other suitable materials.

In some embodiments, the pattern 111 may include the same material as a gate structure. The gate structure can be sacrificial, eg, a dummy (dymmy) gate structure. In some embodiments, the pattern 111 may be disposed at the same elevation as the gate structure. In some embodiments, the pattern 111 may include a dielectric layer of the same material as a gate dielectric layer and a conductive layer of the same material as a gate electrode layer.

In some embodiments, the gate dielectric layer may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or a combination thereof. In some embodiments, the gate dielectric layer may include a dielectric material, such as a high-k dielectric material. A high-k material may have a dielectric constant (k value) greater than 4. High-k materials may include hafnium oxide (HfO2), zirconia (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), or other suitable materials. Other suitable materials are also contemplated by this disclosure.

In some embodiments, the gate electrode layer may include a polysilicon layer. In some embodiments, the fabrication technology of the gate electrode layer may be a conductive material such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta) or other suitable materials. In some embodiments, the gate electrode layer may include a work function layer. The fabrication technology of the work function layer is a metal material, and the metal material may include N-work function metal or P-work function metal. N-work function metals include tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC ), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), or combinations thereof. P-work function metals include titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), or combinations thereof. Other suitable materials are also contemplated by this disclosure. The gate electrode layer may be formed by low pressure chemical vapor deposition (LPCVD) and plasma enhanced CVD (PECVD).

In some embodiments, the pattern 111 may include the same material as a conductive via, and the material may be disposed on a conductive wire, such as the first metal layer (M1 layer). In this embodiment, the pattern 111 may include a barrier layer and a conductive layer surrounded by the barrier layer. The barrier layer may include metal nitride or other suitable materials. The conductive layer may include metals such as W, Ta, Ti, Ni, Co, Hf, Ru, Zr, Zn, Fe, Sn, Al, Cu, Ag, Mo, Cr, alloys or other suitable materials. In this embodiment, the pattern 111 can be formed by a suitable deposition process, such as sputtering or physical vapor deposition (PVD).

The intermediate structure 130 may include one or more intermediate layers made of an insulating material, such as silicon oxide or silicon nitride. In some embodiments, the intermediate structure 130 may include a conductive layer, such as a metal layer or an alloy layer. In some embodiments, one or more intermediate layers may be formed by a suitable film-forming method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). After the interlayer is formed, a thermal operation, such as rapid thermal annealing, may be performed. In other embodiments, a planarization operation, such as a chemical mechanical polishing (CMP) operation, is performed. In other embodiments, a removal operation, such as an etching process, may be performed. The etching process may include, for example, a dry etching process or a wet etching process. It is understood that additional operations may be provided before, during and after the above process, and that some of the above operations may be replaced or eliminated for other embodiments of the method. The order of operations/processes may be interchanged.

FIG. 3B is a cross-sectional view taken along line BB' of FIG. 3 .

As shown in FIGS. 3 and 3B , the pattern 112 is disposed on the intermediate structure 130 . The pattern 112 may be disposed on or over the surface 100s2 of the substrate 100 . In some embodiments, pattern 112 may be a plurality of openings defined by mask 140 . A mask 140 may be formed on the intermediate structure 130 and will be removed in a subsequent process. The mask 140 may include a positive or negative photoresist (such as polymer), or a hard mask (such as silicon nitride or silicon oxynitride). The layer including the mask 140 and the pattern 112 can be patterned using a suitable photolithographic method, for example, forming a photoresist layer on the intermediate structure 130, exposing the photoresist layer to the pattern through a mask, Or bake and develop the photoresist to form the mask 140 and the pattern 112 . A mask 140 may then be used to define a pattern into the intermediate structure 130, thus allowing the portions of the intermediate structure 130 exposed by the photoresist layer to be removed.

FIG. 4 is a top view illustrating an overlay marker 120a of some embodiments of the present disclosure. As shown in FIG. 4 , a semiconductor device structure, such as a wafer, may include overlay marks 120 a on a substrate 100 . In some embodiments, the overlay mark 22 shown in FIG. 2 may include similar or identical patterns or structures as the overlay mark 120a shown in FIG. 4 .

Overlay mark 120a may include patterns 121a and 122 . In some embodiments, the patterns 121 a and 122 may be disposed on two opposite surfaces of the substrate 100 . In some embodiments, the outline of the pattern 121a and the outline of the pattern 122 are equiform in plan view. In some embodiments, the outline of the pattern 121 a is symmetrical to the outline of the pattern 122 with respect to the XY plane. In some embodiments, the shape of the pattern 121a and the shape of the pattern 122 are substantially the same. In some embodiments, the size of the pattern 121a and the size of the pattern 122 are substantially the same. In some embodiments, the pattern 121a overlaps at least a portion of the pattern 122 along the Z direction. In some embodiments, each of patterns 121a and 122 may consist of a single continuous pattern. In some embodiments, the individual continuous patterns described above may have any profile or shape. In this embodiment, the pattern 121a can also be referred to as a reference pattern. In this disclosure, the term "isoform" may mean two patterns that are the same size and/or shape.

When using an overlay mark such as the overlay mark 120a to measure an overlay error, the deviation in the X direction is measured along a straight line in the X direction of the overlay mark 120a. The deviation in the Y direction is further measured along a straight line in the Y direction of the overlay mark 120a. Therefore, whether the patterns 121a and 122 are precisely aligned can be determined according to the deviation in the X direction and the Y direction. The overlay error may include a deviation in the X direction (ΔX), a deviation in the Y direction (ΔY), or a combination of both.

FIG. 4A is a cross-sectional view along line CC' of FIG. 4 illustrating some embodiments of the present disclosure.

In some embodiments, the pattern 121a may be disposed on the surface 100s1 of the substrate 100 . In some embodiments, the pattern 121a may include a layer protruding from the surface 100s1 of the substrate 100 , such as a dummy layer. In some embodiments, the material of the pattern 121a may include a polysilicon layer. In some embodiments, the fabrication technology of the pattern 121a may be a metal, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta) or other suitable materials. The pattern 121a may be formed by LPCVD, PECVD, sputtering, or other suitable processes. In some embodiments, the pattern 121a may include a material that is distinguishable from the material of the substrate 100 by an optical image. In some embodiments, the pattern 121a may include a material that is distinguishable from silicon oxide by an optical image.

In some embodiments, the pattern 122 may be disposed on or over the surface 100s2 of the substrate 100 . In some embodiments, the pattern 122 may be disposed on the intermediate structure 130 . In some embodiments, pattern 122 may be an opening or groove defined by mask 140 . Pattern 122 may be patterned using suitable photolithography, for example, forming a photoresist layer over intermediate structure 130, exposing the photoresist layer through a mask, or baking and developing photolithography. glue to form the mask pattern 122. In some embodiments, the patterns 112 and 122 may be located at the same horizontal level. In some embodiments, patterns 112 and 122 may be formed simultaneously. That is, the patterns 112 and 122 may be formed by the same process and by the same semiconductor manufacturing equipment. In some embodiments, the outline of pattern 122 may be different than the outline of pattern 112 .

In some embodiments, the overlay mark 110 can be used to generate a first overlay error, and the misalignment between the current layer and the previous layer can be measured by measuring the positions of the patterns 121 a and 122 . In some embodiments, the first overlay error may be an anomaly due to misalignment of the current layer and the previous layer. In some embodiments, the first overlay error is an anomaly caused by reasons other than misalignment of the current layer and the previous layer. For example, wafer warpage can cause anomalies in first overlay errors. In this case, the abnormality in the first overlay error is not caused by the misalignment of the current layer and the previous layer. If the exposure equipment is only adjusted according to the first overlay error, the adjusted exposure equipment will be due to inaccurate or inappropriate adjustments that lead to misalignment of the next wafer.

A second overlay error can be generated by using the overlay mark 120a. In some embodiments, the first overlay error can be corrected based on the second overlay error using the overlay marker 120a. In some embodiments, the overlay flag 120a can be used to determine whether anomalies in the first overlay are caused by wafer warping rather than misalignment of current and previous layers. If warping had not occurred, the optical image of pattern 121a would be superimposed on the image of pattern 122 . When wafer warpage occurs, a displacement will occur between the patterns 121a and 122 . In some embodiments, the second overlay error may increase as the degree of warpage increases. Therefore, the second overlay error can be regarded as an indicator for estimating wafer warpage. In some embodiments, when the second overlay error exceeds a predetermined value, it can be determined that the anomaly in the first overlay error is caused by a warping problem rather than misalignment. Therefore, the exposure apparatus can avoid inaccurate adjustment of the first overlay error and the second overlay error. Furthermore, both the first overlay error and the second overlay error can be obtained by an overlay measurement device. In this embodiment, there is no need to transfer wafers with anomalous first stack errors to warpage measurement equipment, such as patterned wafer geometry (PWG) metrology, thus improving the fabrication cycle time of semiconductor device structures.

FIG. 5 is a cross-sectional view illustrating an overlay marker 120b of some embodiments of the present disclosure. The overlay mark 120b shown in FIG. 5 may be similar to the overlay mark 120a shown in FIG. 4A, except that the overlay mark 120b may include a pattern 121b.

In some embodiments, the pattern 121b may be defined by a groove in the surface 100s1 of the substrate 100 . In some embodiments, etching may be performed on the surface 100s1 of the substrate 100 to form the pattern 121b. In some embodiments, the grooves of the substrate 100 can be filled with other materials, such as dielectric materials or conductive materials.

In this embodiment, the overlay flag 120b can be used to determine whether the abnormality in the first overlay is caused by wafer warpage rather than misalignment between the current layer and the previous layer. Therefore, the exposure apparatus may not be adjusted incorrectly or improperly due to the first overlay error and the second overlay error.

FIG. 6 is a cross-sectional view illustrating an overlay marker 120c of some embodiments of the present disclosure. The overlay mark 120c shown in FIG. 6 may be similar to the overlay mark 120a shown in FIG. 4A, except that the overlay mark 120c may include a pattern 121c.

In some embodiments, a dummy layer 150 may be formed on the surface 100s1 of the substrate 100 . In some embodiments, the pattern 121c may be defined by a groove in the dummy layer 150 . In some embodiments, etching may be performed on the dummy layer 150 to form the pattern 121c. In some embodiments, the grooves in the dummy layer 150 can be filled with other materials. In some embodiments, the dummy layer 150 may include a polysilicon layer. In some embodiments, the dummy layer 150 can be metal, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta) or other suitable materials. In some embodiments, a portion of the surface 100s1 of the substrate 100 may be exposed by the dummy layer 150 . In some embodiments, the groove in the dummy layer 150 may be a blind hole.

In this embodiment, the overlay flag 120c can be used to determine whether the abnormality in the first overlay is caused by wafer warpage rather than misalignment of the current layer and the previous layer. Therefore, the exposure apparatus may not be adjusted incorrectly or improperly due to the first overlay error and the second overlay error.

FIG. 7 is a cross-sectional view illustrating an overlay marker 160a of some embodiments of the present disclosure. The structure of the semiconductor device shown in FIG. 7 is similar to the structure of the semiconductor device shown in FIG. 4A , the difference is that the structure of the semiconductor device in FIG. 7 may further include an overlapping mark 160a.

A third overlay error can be generated by using the overlay mark 160a. The overlay flag 160a can be used to determine whether an anomaly of an overlay error generated by another pair of the current layer and the previous layer is caused by warpage on the wafer. Although not shown, it should be noted that another pair of counter and front layers may be located on and within the intermediate structure 170, respectively. The overlay flag 160a can be used to determine whether the abnormality of the overlay error is caused by the above-mentioned misalignment between the current layer and the previous layer.

The overlay mark 160a may include a pattern 161a and a pattern 162, both of which may be used in common to generate a third overlay error. In some embodiments, the pattern 161a may be disposed on the surface 100s1 of the substrate 100 . In some embodiments, the pattern 161a and the pattern 121a may be located at the same horizontal level. In some embodiments, the material of the pattern 161a may be the same as that of the pattern 121a and made by the same process. In some embodiments, the outline of the pattern 161a may be the same as the outline of the pattern 121a. In some embodiments, the outline of pattern 161a may be different from the outline of pattern 121a. In some embodiments, the pattern 161a may not overlap the pattern 121a in the Z direction.

In some embodiments, the pattern 162 may be disposed on or over the surface 100s2 of the substrate 100 . In some embodiments, pattern 162 may be located at a different location than the horizontal level of features 122'. The pattern 162 may be disposed on the intermediate structure 170 . Intermediate structure 170 may include one or more dielectric layers and conductive features disposed within the dielectric layers. Intermediate structure 170 may cover feature 122'. Features 122 ′ may be formed by filling the openings defined by pattern 122 with a conductive or dielectric material. Features 122 ′ may have the same pattern as pattern 122 . In some embodiments, the pattern 162 may be an opening or a groove defined by the mask 180 . A mask 180 may be formed on the intermediate structure 170 and will be removed in a subsequent process. The mask 180 may include a positive or negative photoresist. Mask 180 may be used to define a pattern in intermediate structure 170 such that portions of intermediate structure 170 exposed by the photoresist layer may be removed.

In some embodiments, the outline of the pattern 162 is conformal to the outline of the pattern 161a in a plan view. In some embodiments, the outline of the pattern 161a is symmetrical to the outline of the pattern 162 with respect to the XY plane. In some embodiments, the shape of pattern 161a and the shape of pattern 162 are substantially the same. In some embodiments, the size of the pattern 161a and the size of the pattern 162 are substantially the same. In some embodiments, pattern 161a overlaps at least a portion of pattern 162 along the Z-axis.

In this embodiment, the overlay marker 160a can be used to estimate the warp of the wafer at a different stage than the warpage estimation using the overlay marker 120a shown in FIG. 4A . In this embodiment, the overlay flag 160a can be used to determine whether the abnormality in overlay is caused by wafer warping, rather than misalignment between the current layer and the previous layer. Therefore, the exposure equipment can not be adjusted inaccurately due to the third layer overlay error.

Figure 8 is a cross-sectional view illustrating overlay markers of some embodiments of the present disclosure. The semiconductor device structure shown in FIG. 8 may be similar to the semiconductor device structure shown in FIG. 7 , the difference is that the semiconductor device structure may further include an overlapping mark 160b.

A third overlay error can be generated by using the overlay mark 160b. The overlay flag 160b may be used to determine whether an abnormality in an overlay error generated from another pair of the current layer and the previous layer is caused by warpage on the wafer. The overlay marks 160b can be used to estimate wafer warpage at another stage than the warpage estimation using the overlay marks 120a shown in FIG. 4A .

The overlay mark 160b may include a pattern 161b and a pattern 162, both of which may be used in common to generate a third overlay error. In some embodiments, the pattern 161b may be disposed on the surface 100s1 of the substrate 100 . In some embodiments, the pattern 161b and the pattern 121c may be located on different horizontal levels. In some embodiments, the pattern 121c may be defined by a groove in the dummy layer 150 . In some embodiments, the grooves in the dummy layer 150 may be filled with other materials, such as dielectric materials or conductive materials. In some embodiments, the pattern 161b may be another dummy layer or a groove of another dummy layer disposed on the dummy layer 150 . For example, the material of the pattern 161b may include a polysilicon layer, a metal layer or an alloy layer, and may be formed by LPCVD, PECVD, sputtering or other suitable processes.

Although FIG. 8 illustrates that the horizontal level of the pattern 161b is lower than that of the pattern 121c, the disclosure is not intended to be limiting. In some other embodiments, the horizontal level of the pattern 161b may be higher than that of the pattern 121c. In some embodiments, the pattern 161b may not overlap the pattern 121c in the Z direction.

In this embodiment, the overlay flag 160b can be used to determine whether the overlay abnormality is caused by wafer warpage rather than misalignment between the current layer and the previous layer. Thus, the exposure equipment is immune to inaccurate or improper adjustments due to third layer overlay errors.

FIG. 9 is a block diagram illustrating a semiconductor fabrication system 300 of some embodiments of the present disclosure.

The semiconductor fabrication system 300 may include fabrication equipment 310 , 320 - 1 , . . . , and 320 -N, 330 , 340 - 1 , . The overlay correction system 370 may be included in or built into the overlay measurement device 360 . Manufacturing equipment 310, 320-1, . . . , and 320-N, 330, 340-1, . Perform signal coupling. In some embodiments, overlay correction system 370 may be a stand-alone system signal-coupled to overlay measurement device 360 via network 380 .

Fabrication apparatus 310 may be used to form a reference pattern, such as pattern 121a, 121b, 121c, 160a or 160b as shown in Figure 4A, Figure 5, Figure 6, Figure 7 or Figure 8, respectively. Fabrication equipment 310 may be used to pattern the backside surface of the wafer as part of the overlay marking.

Fabrication equipment 320-1, . . . , and 320-N may be used to form elements or features between a front layer, such as pattern 111 shown in FIG. 3A, and a substrate. Each of the fabrication apparatuses 320-1, . Other crafts.

Fabrication apparatus 330 may be used to form patterns in a front layer, such as pattern 111 shown in FIG. 5 . In some embodiments, the fabrication equipment 330 may be used to form an isolation structure, a gate structure, a conductive via, or other layers. The pattern of the front layer may include dielectric material, semiconductor material or conductive material.

Fabrication equipment 340-1, . . . , and 340-N may be used to form an intermediate structure, such as intermediate structure 130 shown in FIG. 4A. Each of the fabrication equipment 340-1, . craft or other craft.

Exposure apparatus 350 may be used to form a layered pattern, such as patterns 112 and 122 shown in Figures 3B and 4A, respectively.

In some embodiments, the overlay measurement device 360 can be used to obtain optical images of the patterns of the previous layer and the current layer, and a first overlay error. In some embodiments, the overlay measurement device 360 may be used to generate a second overlay error based on the reference pattern and the patterns in the current layer (eg, patterns 121 and 122 ).

The overlay correction system 370 may include correction parameters for generating corrected first and second overlay errors. Overlay correction system 370 may include, for example, a computer or server. In some embodiments, each of the corrected first and second overlay errors can be generated or calculated by a program code or language. For example, the corrected first overlay error may be determined from the first overlay error obtained from the overlay measurement device 360 and the correction parameters of the overlay correction system 370 . In some embodiments, a deviation in the X direction ([Delta]X), a deviation in the Y direction ([Delta]Y), or a combination of both can be generated from the calibration parameters. Each of the X-direction deviation (ΔX), the Y-direction deviation (ΔY), or a combination thereof can be expressed by a formula including the correction parameter as a variable. In some embodiments, the overlay correction system 370 may receive optical image information from the previous layer's pattern (or reference pattern) and the current layer's pattern, and then generate X-direction deviation (ΔX), Y-direction deviation (ΔY), or A combination of the two to compensate for the first and second overlay errors obtained from the overlay measurement device 360 .

Network 380 may be the Internet or an internal network using a network communication protocol such as Transmission Control Protocol (TCP). Through the network 380, each of the manufacturing equipment 310, 320-1, . . . , and 320-N, 330, 340-1, . The controller 390 downloads or uploads work-in-process (WIP) information about wafers or fabrication equipment.

Controller 390 may include a processor, such as a central processing unit (CPU). In some embodiments, the controller 390 may be utilized to generate an instruction whether to adjust the exposure apparatus 350 based on the first overlay error and the second overlay error.

Although FIG. 9 does not show any other fabrication equipment preceding fabrication facility 310, this illustrative embodiment is not intended to be limiting. In other exemplary embodiments, various manufacturing equipment may be arranged before the manufacturing equipment 310, and may be used to perform various processes according to design requirements.

In the exemplary embodiment, wafer 301 is transferred to fabrication facility 310 to begin a series of different processes. Wafer 301 may go through various stages of processing to form at least one layer of material. The exemplary embodiments are not intended to limit the processing of wafer 301 . In other exemplary embodiments, wafer 301 may include various layers, or any stage between initiation and completion of a product, before wafer 301 is transferred to fabrication facility 310 . In an exemplary embodiment, wafer 301 may be measured by fabrication equipment 310, 320-1, . . . , and 320-N, 330, 340-1, . Device 360 processes sequentially.

FIG. 10 is a flow diagram illustrating a method 400 of making an overlay marker of various aspects of the present disclosure.

Fabrication method 400 begins at operation 410, where a substrate is provided. The substrate can have a first surface and a second surface opposite the first surface. The first surface may also be referred to as the rear surface. The second surface may also be referred to as an active surface on which active features are formed, such as a gate structure or a wire connected to input and output terminals.

Fabrication method 400 continues with operation 420, wherein a first pattern is formed on the first surface of the substrate. In some embodiments, the first pattern may be a polysilicon layer on the first surface of the substrate. In some embodiments, the first pattern may be a groove on the first surface of the substrate. In some embodiments, the first pattern may be a groove formed in a polysilicon layer on the first surface of the substrate. In some embodiments, the manufacturing method 400 may include forming a polysilicon layer on the first surface of the substrate, and then patterning the polysilicon layer to form a first pattern. In some embodiments, the remainder of the polysilicon layer may be used to define the first pattern. In some embodiments, a groove or an opening in the polysilicon layer may be used to define the first pattern. In some embodiments, the manufacturing method 400 may include removing a portion of the substrate from the first surface of the substrate to form a groove as the first pattern. The first pattern may be formed by, for example, the manufacturing apparatus 310 shown in FIG. 9 .

Fabrication method 400 continues with operation 430, wherein a second pattern is formed on the second surface of the substrate. The second pattern may include the same material as the isolation features, gate structures, or conductive vias. The second pattern may be formed by processes used to form isolation features, gate structures, or conductive vias. For example, the second pattern may be formed by the manufacturing apparatus 330 shown in FIG. 9 .

Fabrication method 400 continues with operation 440 where an intermediate structure is formed to cover the second pattern. The intermediate structure may comprise one or more intermediate layers formed of an insulating material, such as silicon oxide or silicon nitride. The intermediate structure may include conductive features formed in the dielectric layer. In some embodiments, the intermediate structure can be formed by CVD, PVG, ALD, dry etching, wet etching, CMP, or photolithography. The intermediate structure may be formed by, for example, fabrication equipment 340-1, . . . , and 340-N shown in FIG.

The fabrication method 400 continues with operation 450 , wherein a third pattern is formed to be vertically aligned with the second pattern, and a fourth pattern is formed to be vertically aligned with the first pattern. In some embodiments, the third pattern and the fourth pattern may be openings of a mask, such as a photoresist layer. In some embodiments, operation 450 may include, for example, forming a photoresist layer on the intermediate structure, exposing the photoresist layer to a pattern through a mask, baking and developing the photoresist to form a mask third pattern and fourth pattern. The third pattern and the fourth pattern may be formed by at least the exposure apparatus 350 shown in FIG. 9 .

The second pattern and the third pattern can be shared to generate a first overlay error measuring the offset between the previous layer and the current layer. The first pattern and the fourth pattern can be used cooperatively to generate a second overlay error, so as to determine whether the abnormality in the first overlay error is caused by the misalignment of the previous layer and the current layer. The first pattern, the second pattern, the third pattern and the fourth pattern may be used in common to measure the degree of wafer warpage.

FIG. 11 is a flowchart illustrating a method 500 of overlay correction for various aspects of the present disclosure.

The method begins at operation 510, where a first overlay mark and a second overlay mark are provided. The first overlay mark may include the overlay mark 110 shown in FIG. 3 , which may include a first pattern (eg, pattern 111 ) of a previous layer and a second pattern (eg, pattern 112 ) of a current layer. The second overlay mark may include the overlay mark 120 shown in FIG. 4 . The second overlay mark may include a third pattern (eg, pattern 121 ) and a fourth pattern (eg, pattern 122 ) of the current layer. In some embodiments, the second pattern and the fourth pattern may be formed by exposure equipment (eg, exposure equipment 350 ).

The method continues with operation 520 where a first overlay error is generated based on the first overlay mark and a second overlay error is generated based on the second overlay mark. In some embodiments, the optical image may be obtained from an overlay measurement device (eg, overlay measurement device 360 ). Overlay errors can arise based on the optical image. A first overlay error may be calculated based on the first pattern and the second pattern. The second overlay error may be calculated based on the third pattern and the fourth pattern. In some embodiments, operation 520 may also include correcting the first overlay error and the second overlay error by an overlay correction system (eg, overlay system 370 ).

The method continues with operation 530 where a first determination is performed to determine whether the first overlay error is abnormal. In some embodiments, the overlay measurement device may send a signal of the first overlay error to a controller (eg, controller 390) via a network (eg, network 380), and the controller may compare the first overlay error and a target first overlay error. In some embodiments, the target first overlay error may be predetermined based on semiconductor process requirements. In some embodiments, the controller may include a determination module (not shown) to perform operation 530 . In some embodiments, the first overlay error may be determined to be abnormal when the first overlay error exceeds a target first overlay error.

Next, based on the first determination of operation 530, operation 540 or operation 550 is performed. In some embodiments, when the first overlay error is not abnormal, the exposure equipment may be used to perform the next exposure process without adjusting the exposure equipment, as shown in operation 540 .

In some embodiments, when the first overlay error is abnormal, a second determination is performed to determine whether the second overlay error is abnormal, as shown in operation 550 . In some embodiments, the overlay measurement device may send a signal of the second overlay error to the controller, and the controller may then compare the second overlay error to a target second overlay error. In some embodiments, the target second overlay error may be predetermined based on semiconductor process requirements. In some embodiments, a determination module of the controller may perform operation 550 . In some embodiments, the second overlay error may be determined to be abnormal when the second overlay error exceeds a target second overlay error.

Next, based on the determination of operation 550, operation 560 or operation 570 is performed. In some embodiments, when the second overlay error has no abnormality, it may be determined that the warpage of the wafer does not cause the abnormality of the first overlay error. In this case, the exposure equipment may be adjusted and then utilized to perform the next exposure process, as shown in operation 560 .

In some embodiments, when the second overlay error is abnormal, it may be determined that the warping of the wafer causes the abnormality of the first overlay error. The next exposure process may be performed using the exposure equipment without adjusting the exposure equipment, as shown in operation 570 .

In some embodiments, the anomaly of the first overlay error is not caused by misalignment of the previous layer and the current layer, but by warpage of the wafer. If the exposure equipment is adjusted based on the first overlay error only, the next wafer will suffer misalignment of the current layer and the previous layer due to the inaccurate adjustment of the exposure equipment. To avoid such situations, the second overlay error can be used to determine whether the abnormality in the first overlay error is caused by wafer warpage rather than misalignment of the previous layer and the current layer. Inaccurate adjustment of the exposure equipment can be prevented by the two-step determination of two superimposed marks. Therefore, the usable time of the exposure equipment can be improved.

The processes illustrated in Figures 10 and 11 may be implemented in the controller 390, or computing system that organizes the fabrication of wafers by controlling each or a portion of the fabrication equipment in the facility. FIG. 12 is a diagram illustrating hardware of a semiconductor fabrication system 600 of various aspects of the present disclosure. System 600 includes one or more hardware processors 601 and a non-transitory computer-readable storage medium 603 encoded with, ie, stored with, program code (ie, a set of executable instructions). Computer readable storage medium 603 may also be encoded with instructions for interfacing with manufacturing equipment that produces semiconductor devices. The processor 601 is electrically connected to the computer-readable storage medium 603 through the bus 605 . Processor 601 is also electrically coupled to input and output (I/O) interface 607 via bus 605 . The network interface 609 is also electrically connected to the processor 601 via the bus 605 . The network interface is connected to a network so that the processor 601 and the computer-readable storage medium 603 can be connected to external elements via the network 380 . The processor 601 is configured to execute the computer program code encoded in the computer-readable storage medium 605, so that the system 600 can be used to perform some or all of the operations described in the methods shown in FIG. 10 and FIG. 11 .

In some exemplary embodiments, processor 601 is, but is not limited to, a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit. Various circuits or units are within the scope of the present disclosure.

In some demonstrative embodiments, computer readable storage medium 603 is, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or device or device). Computer readable storage medium 603 includes, for example, a semiconductor or solid state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read only memory (ROM), a hard disk, and/or an optical disk. In one or more exemplary embodiments utilizing optical disks, computer readable storage medium 603 also includes compact disk - read only memory (CD-ROM), compact disk - read/write (CD-R/W) and/or digital video compact disc (DVD).

In some exemplary embodiments, the storage medium 603 stores computer program codes configured to enable the system 600 to execute the methods shown in FIGS. 10 and 11 . In one or more exemplary embodiments, the storage medium 601 also stores information required for performing the methods illustrated in FIGS. A set of executable instructions for the operation of a method. In some exemplary embodiments, a user interface 610 , such as a graphical user interface (GUI), may be provided for the user to operate on the system 600 .

In some exemplary embodiments, the storage medium 603 stores instructions for interfacing with external machines. The instructions enable the processor 601 to generate instructions readable by an external machine to effectively implement the methods illustrated in Figures 10 and 11 during analysis.

System 600 includes input and output (I/O) interface 607 . The I/O interface 607 is connected to external circuits. In some exemplary embodiments, the I/O interface 607 may include, but is not limited to, a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and/or cursor direction keys for communicating information to the processor 601 and command.

In some exemplary embodiments, the I/O interface 607 may include a display, such as a cathode ray tube (CRT), liquid crystal display (LCD), speaker, and the like. For example, a monitor displays information.

System 600 may also include a network interface 609 coupled to processor 601 . Network interface 609 allows system 600 to communicate with network 380 to which one or more other computer systems are connected. For example, the system 600 can be connected to the manufacturing equipment 310, 320-1, ..., 320-N, 330, 340-1, ..., and 340-N through the network interface 609 connected to the network 380, the exposure equipment 350 And stack measurement device 360 .

One aspect of the present disclosure provides an overlay corrected marker. The mark includes a first pattern and a second pattern. The first pattern is disposed on a first surface of a base. The second pattern is disposed on a second surface of the base, and the second surface of the base is opposite to the first surface of the base. The first pattern overlaps at least a portion of the second pattern, and the first pattern and the second pattern together define a first overlay error.

Another aspect of the present disclosure provides an overlay corrected marker. The mark includes a first overlay mark and a second overlay mark. The first overlay mark includes a first pattern and a second pattern disposed on a first surface of a substrate. The first overlay mark is used to generate a first overlay error. The second overlay mark includes a third pattern disposed on a second surface of the substrate and a fourth pattern disposed on the first surface of the substrate. The first surface of the substrate is opposite to the second surface of the substrate. The second overlay mark is used to generate a second overlay error, and the second overlay mark is used to correct the first overlay error.

Another aspect of the present disclosure provides a method for correcting overlay errors. The method includes generating a first overlay error based on a first overlay mark, wherein the first overlay error indicates a misalignment between a lower pattern and an upper pattern of the first overlay mark, and responsive to In detecting the abnormality of the first overlay error, generating a second overlay error based on a second overlay mark, and determining whether the abnormality in the first overlay error is caused by the lower pattern and the second overlay error based on the second overlay error This misalignment of the upper pattern causes.

Another aspect of the present disclosure provides a method of manufacturing a semiconductor element. The preparation method includes providing a substrate having a first surface and an opposite second surface thereof, forming a first pattern on the first surface of the substrate, forming a pattern on the second surface of the substrate a second pattern, forming an intermediate structure covering the second pattern, forming a third pattern on the second surface of the substrate, wherein the second pattern and the third pattern together define a first overlay error, and in the base

A fourth pattern is formed on the second surface of the bottom, wherein the first pattern and the fourth pattern jointly define a second overlay error.

Embodiments of the present disclosure provide overlay markers for overlay error measurement. Two overlay marks can be shared to determine whether anomalies in overlay errors are caused by misalignment of current and previous layers, or by wafer warpage. Using two measuring steps with two superimposed marks prevents inaccurate adjustments of the exposure equipment. Therefore, the usable time of the exposure equipment can be increased.

0 Although the present disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions and

substitution without departing from the spirit and scope of the present disclosure as defined by the disclosed claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present disclosure is not limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, and materials that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. composition, means, method, or steps. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are included within the disclosed claims of the present disclosure.

Claims (13)

1. A method for correcting an overlay error, comprising: generating a first overlay error based on a first overlay mark, wherein the first overlay error indicates a misalignment between a lower pattern and an upper pattern of the first overlay mark; and An exception responsive to detecting the first overlay error: generating a second overlay error based on a second overlay mark; and According to the second overlay error, it is determined whether the abnormality of the first overlay error is caused by the misalignment between the lower pattern and the upper pattern. 2. The calibration method as claimed in claim 1, wherein the second overlay mark comprises a first pattern arranged on a substrate-first surface and a second pattern arranged on the substrate-second surface, And wherein the first surface of the substrate is opposite to the second surface of the substrate. 3. The calibration method as claimed in claim 2, wherein the second pattern and the upper pattern are located at the same horizontal level. 4. The calibration method as claimed in claim 2, wherein the second pattern at least overlaps with the first pattern. 5. The calibration method according to claim 2, wherein a contour of the first pattern and a contour of the second pattern are conformal in a plan view. 6. The calibration method as claimed in claim 2, wherein the lower pattern does not overlap with the upper pattern. 7. The correction method as claimed in claim 1, further comprising: It is determined whether the second overlay error is abnormal, and whether the lower pattern and the upper pattern are misaligned. 8. The calibration method as claimed in claim 1, wherein the first overlay error and the second overlay error are shared to determine whether the abnormality of the first overlay error is caused by warpage of the wafer. 9. A method for preparing a semiconductor element, comprising: providing a substrate having a first surface and an opposite second surface; forming a first pattern on the first surface of the substrate; forming a second pattern on the second surface of the substrate; forming an intermediate structure to cover the second pattern; forming a third pattern on the second surface of the substrate, wherein the second pattern and the third pattern together define a first overlay error; and A fourth pattern is formed on the second surface of the substrate, wherein the first pattern and the fourth pattern jointly define a second overlay error. 10. The manufacturing method according to claim 9, wherein a contour of the first pattern and a contour of the fourth pattern are conformal. 11. The preparation method according to claim 9, wherein forming the first pattern comprises: forming a layer on the first surface of the substrate; and The layer is patterned to form a first pattern. 12. The preparation method according to claim 9, wherein forming the first pattern comprises: A part of the substrate is removed to form a groove recessed from the first surface of the substrate, wherein the groove serves as the first pattern. 13. The preparation method according to claim 9, wherein forming the first pattern comprises: forming a layer on the first surface of the substrate; and A part of the layer is removed to form a groove, wherein the groove is used as the first pattern.

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