JP2014160749A - Semiconductor device manufacturing method - Google Patents

Abstract

In the case of high-order correction, it is necessary to measure with a large number of alignment marks, leading to a decrease in throughput.
In a lithography process, overlay correction between layers is performed by linear correction, overlay inspection is performed, and the inspection result is analyzed by two types of a primary correction model and a tertiary correction model. . Thereafter, unnecessary films are removed (regenerated) from the semiconductor wafer so that lithography processing can be performed again, and the same semiconductor wafer is subjected to lithography processing. In this case, since the distortion tendency of the semiconductor wafer does not change before and after the reproduction, the first lithography process and the second lithography process are performed based on the overlay inspection result. The first inspection result used at this time is a lithographic process by weighted tertiary correction using an overlay correction value intermediate between the overlay correction value of the primary correction model and the overlay correction value of the tertiary correction model. Do.
[Selection] Figure 3

Description

  The present invention relates to a method for manufacturing a semiconductor device, for example, a technique applicable to alignment adjustment in a lithography process in manufacturing a semiconductor device.

  It is known that various electronic devices typified by a semiconductor device are manufactured by exposing a plurality of layers on a substrate by using an exposure apparatus. In this exposure process, when the pattern of the second and subsequent layers is exposed on a substrate such as a semiconductor wafer, each shot area on which the pattern has already been formed on the substrate is aligned with the pattern image of the mask (substrate and reticle). Alignment), that is, alignment must be performed accurately.

  This alignment adjustment can be performed by, for example, approximating shift components of the entire shot, linear correction that approximates and corrects primary components such as the magnification, rotation, and orthogonality of each shot array, or higher-order components that occur in a bowed shape. What corrects using the correction value calculated | required by the high-order correction etc. which correct | amend by doing is known.

  For example, Patent Documents 1 to 3 are known as this type of alignment adjustment technique. Japanese Patent Application Laid-Open No. 2004-133867 calculates expected array coordinates from an alignment mark array model, and determines actual array coordinates from the coordinates.

  Japanese Patent Laid-Open No. 2004-228561 describes a subsequent exposure processing substrate when the correction amount in each exposure region of any three consecutive exposure processing substrates is within an allowable range compared to the average value of the correction amounts. The exposure process is performed as it is. When the correction amount in each exposure region of any three consecutive exposure processing substrates is not within the allowable range compared to the average value of the correction amounts, the fourth exposure processing substrate is corrected. Then, the average value of the correction amounts in the second to fourth exposure processing substrates that have been measured so far, including this exposure processing substrate, is recalculated. When the recalculated average value is compared with the measured value of each exposure area, and the error is within the allowable range, the subsequent exposure processing substrate performs the correction measurement of each exposure area. The exposure process is omitted.

  Patent Document 3 preliminarily detects a large number of alignment marks attached to a plurality of shots on a semiconductor wafer, and describes a model (conditions) for describing a nonlinear component of distortion of a semiconductor wafer based on a precise detection result. Make multiple decisions. At the time of semiconductor wafer exposure (lot processing), a small number of alignment marks are detected to determine the distortion of the semiconductor wafer, and a plurality of models (conditions) determined in advance based on the result are selected and selected. The pattern is sequentially aligned with a plurality of shots using a model and exposed.

Japanese Patent Laid-Open No. 5-114545 JP 2003-109889 A JP 2010-186918 A

  With the miniaturization of semiconductor devices, the overlay accuracy required for alignment adjustment is becoming stricter. High-order correction that approximates and corrects higher-order components and the like is often used because it enables correction of non-linear deformation or the like that occurs in a substrate due to process processing such as polishing or thermal expansion.

  However, in the case of high-order correction, it is necessary to perform measurement with a large number of alignment marks, which causes a problem that throughput is reduced. In addition, when high-order correction is used, there is a problem that linear correction that approximates and corrects primary components cannot be used in subsequent steps in order to correct nonlinear deformation and the like. As a result, high-order correction must be used in the subsequent steps and the throughput is greatly reduced.

  FIG. 20 is an explanatory diagram illustrating an example of measurement points of alignment measurement studied by the present inventors. The left side of FIG. 20 shows an example of measurement points for alignment measurement at the time of high-order correction, and the right side of FIG. 20 shows an example of measurement points for alignment measurement at the time of linear correction. FIG. 21 is an explanatory diagram illustrating an example in which measurement times of measurement points in FIG. 20 are compared.

  As shown in FIG. 20, the number of high-order correction measurement points is significantly larger than that of linear correction measurement points. Therefore, as shown in FIG. 21, the measurement time for the measurement point in the high-order correction requires more time than the measurement time for the measurement point in the linear correction, thereby reducing the throughput in semiconductor manufacturing. It will be.

  A method for manufacturing a semiconductor device according to an embodiment includes the following steps.

  This is a first lithography process in which the displacement amount measured in the alignment inspection is approximated by two or more higher-order correction equations to correct the overlay displacement amount between layers, and the first film is processed. This is a second lithography process in which a high-order correction formula is approximated by a weighted high-order correction formula obtained by multiplying a coefficient of less than 1 to correct the overlay displacement amount between layers and process the second film. This is a third lithography process in which the amount of misalignment between layers is corrected by approximation using a linear correction formula to process the third film.

  According to the one embodiment, the manufacturing efficiency of the semiconductor device can be improved.

It is explanatory drawing which shows the outline | summary of the alignment / overlay inspection of a semiconductor wafer and a mask. It is explanatory drawing which shows the outline of the exposure apparatus which performs the alignment / overlay inspection in this Embodiment 1. FIG. It is a flowchart which shows an example of the alignment process of the semiconductor wafer and mask in an exposure process. It is explanatory drawing which shows an example of the result (linear correction) of the overlay test | inspection in the process of step S102 of FIG. It is explanatory drawing which shows an example of the result of superposition inspection in the process of step S105 of FIG. 3 (weighted tertiary correction). It is explanatory drawing which shows an example of the result prediction of the overlay test | inspection by high order correction | amendment (tertiary correction). It is explanatory drawing which shows an example of the position alignment image by weighted 3rd correction | amendment. It is explanatory drawing which shows an example of the alignment image in the next process which performed the weighted tertiary correction | amendment in FIG. 10 is a flowchart showing an example of alignment processing between a semiconductor wafer and a mask in each manufacturing process according to the second embodiment. It is explanatory drawing which shows an example of the alignment test result before the process of step S201 of FIG. It is explanatory drawing which shows an example of the alignment test result in the process of step S201 of FIG. It is explanatory drawing which shows an example of the alignment test result in the process of step S202 of FIG. It is explanatory drawing which shows an example of the alignment test result in the process of step S206 of FIG. It is explanatory drawing which shows transition of the residual value in the alignment test | inspection by the process of FIG. 10, and the residual value in an overlay test | inspection. It is explanatory drawing which shows an example of the residual value of the semiconductor wafer by linear correction. It is explanatory drawing which shows an example of the residual value at the time of the weighted tertiary correction in the semiconductor wafer of FIG. It is explanatory drawing which shows the prediction relationship between the weighting coefficient (alpha) and a residual value. 14 is a flowchart illustrating an example of weighting coefficient determination processing according to the third embodiment. It is explanatory drawing which shows the example of decomposition | disassembly of the high order component in alignment error. It is explanatory drawing which shows an example of the measurement point of the alignment measurement which this inventor examined. It is explanatory drawing which shows an example which compared the measurement time of the measurement point in FIG.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., the shape of the component is substantially the case unless it is clearly specified and the case where it is clearly not apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
<Outline of alignment and overlay inspection>
In order to manufacture a semiconductor element using a semiconductor wafer, a circuit is formed in a stacked manner and a layer is provided. This layer is necessary by advancing detailed processes such as coating, exposure, and development. The pattern is formed. Such a process is called a so-called lithography process. In this lithography process, a desired pattern formed on a mask is transplanted on a semiconductor wafer (semiconductor substrate) on which an actual semiconductor element is formed by the above-described coating, exposure, and development processes.

  In such a lithography process in which a circuit pattern of a mask is superimposed and transferred on a semiconductor wafer, it is necessary to align the mask and the semiconductor substrate with high accuracy and accuracy.

  In this lithography process, when overlaying between layers, position measurement is performed using a pattern formed on a semiconductor wafer, and a patterning position is determined from the information.

  FIG. 1 is an explanatory diagram showing an outline of alignment / overlay inspection between a semiconductor wafer and a mask. FIG. 1A shows an outline of alignment inspection, and FIG. 1B shows an outline of overlay inspection.

  On the semiconductor wafer W, in the circuit pattern CP1 (actually formed on the semiconductor wafer W by a poly Si oxide film after etching) formed in the first step to be a layer to be bonded. Marks such as an inspection pattern KP1 which is a pattern used for alignment inspection and an alignment pattern AP1 used for alignment are formed.

An interlayer insulating film ISO made of, for example, silicon dioxide (SiO ₂ ) is formed on the circuit pattern CP1, the inspection pattern KP1, the alignment pattern AP1, and the like. A resist RST is applied on top of the interlayer insulating film ISO.

  In the alignment step, as shown in FIG. 1A, the position on the semiconductor wafer W is measured by the mark of the alignment pattern AP1 (position measurement in the stage coordinate system of the exposure apparatus).

  After the lithography is finished, as shown in FIG. 1B, the resist pattern RP1 formed in the second step to be the alignment layer and the inspection pattern KP1 formed in the first step are used to make relative Overlay inspection to measure the amount of misalignment (overlay displacement).

<Outline of exposure apparatus>
FIG. 2 is an explanatory diagram showing an outline of an exposure apparatus that performs alignment / overlay inspection in the first embodiment. Note that the hatching shown in FIGS. 2A to 2C indicates an execution position of the operation process in the exposure apparatus EXS.

  As illustrated, the exposure apparatus EXS includes a wafer stage STG, an alignment mark measurement unit AMS, a calculation unit OPE, a control unit CON, and an exposure processing unit LEN. Wafer stage STG mounts semiconductor wafer W to be inspected.

  The alignment mark measurement unit AMS performs alignment measurement on the semiconductor wafer W. The calculation unit OPE calculates the measurement result measured by the alignment mark measurement unit AMS. The controller CON performs control when moving the wafer stage STG. The exposure processing unit LEN performs an exposure process on the semiconductor wafer W.

  As shown in FIG. 2 (a), the exposure apparatus EXS observes the semiconductor wafer W that has been transferred and placed on the wafer stage STG using an alignment mark measuring unit AMS (shown by hatching), and the alignment mark (FIG. 1). The position of the alignment pattern AP1) is measured. The measurement result by the alignment mark measurement unit AMS is output to the calculation unit OPE.

  Subsequently, as shown in FIG. 2 (b), the above measurement result is calculated by the calculation unit OPE (indicated by hatching), and alignment mark coordinate information (design value or ideal value) given in advance, From the difference from the mark position measured in the stage coordinate system of the wafer stage STG of the exposure apparatus EXS, correction is performed so that the overlay deviation is reduced in the entire semiconductor wafer W. This correction is performed by approximating a linear expression or a cubic expression, which will be described later, and the exposure apparatus EXS performs patterning by performing an operation according to the approximate expression.

  Then, as shown in FIG. 2C, the control unit CON (indicated by hatching), according to the approximate expression calculated by the arithmetic unit OPE, the wafer stage STG (indicated by hatching) and the exposure processing unit LEN (indicated by hatching). Drive control). Thereby, the alignment is performed so that the relative displacement amount (overlay displacement) between the layers is minimized.

<Example of overlay correction processing>
FIG. 3 is a flowchart showing an example of the alignment process between the semiconductor wafer and the mask in the exposure process.

  First, in the lithography process, after overlay correction between layers is performed by linear correction (step S101), overlay inspection is performed (step S102). Then, the result of overlay inspection is analyzed with two types of a primary correction model and a tertiary correction model.

  As a result of analysis by the primary correction, the correctable amount is small and the residual value is large. On the other hand, in the third-order correction model, the correctable amount is large and the residual value is small. The semiconductor wafer that has been inspected is regenerated to remove the resist and other unnecessary films so that the lithography process can be performed again (step S103).

  Then, the same semiconductor wafer is subjected to lithography processing again (step S104). In the same semiconductor wafer, since the distortion tendency of the semiconductor wafer does not change before and after the reproduction, the second time based on the first lithography process (process in step S101) and the overlay inspection result (process in step S102). The lithography process is performed.

  The first inspection result used in the second lithography process is usually the overlay correction value of the primary correction model or the overlay correction value of the tertiary correction model. Lithography processing is performed by weighted tertiary correction using a correct overlay correction value (weighting coefficient). After this lithography process, overlay inspection is performed again (step S105), and overlay displacement is confirmed.

  Exposure equipment measures alignment marks on a semiconductor wafer, positions them, and exposes them (patterning). However, the positioning is not accurate due to the shape of the marks on the semiconductor wafer or the nuisance of the measuring equipment of the exposure equipment. There may not be.

  That is, although the exposure apparatus exposes so that there is no overlay displacement, the actual alignment pattern is displaced. However, such a phenomenon always shifts in the same way because the reproducibility of the measurement can be obtained because the mark shape and the habit of the measuring instrument are stable.

  For example, when there is always an overlay shift amount of about +10 nm in the lateral (X) direction, the overlay shift is eliminated if exposure is performed with a shift of about −10 nm in the lateral (X) direction from the measurement result of the exposure apparatus. Thus, the value for correcting the measurement of the exposure apparatus is the overlay correction value.

  Here, higher-order correction (here, third-order correction) in the semiconductor wafer surface is expressed by the following equation.

Here, x and y are positions (coordinates) on the semiconductor wafer, dx and dy are correction amounts at the position (x, y) on the semiconductor wafer, and a _x , b _x and c _x are coefficients.

dx ₃ = a _x3 * x ^ 3 + b _x3 * x ^ 2 * y + c _x3 * x * y ^ 2 + d _x3 * y ^ 3 + e _x3 * x ^ 2 + f _x3 * x * y + g _x3 * y ^ 2 + h _x3 * x + j _x3 * y + k _x3
dy ₃ = a _y3 * x ^ 3 + _by3 * x ^ 2 * y + c _y3 * x * y ^ 2 + d _y3 * y ^ 3 + e _y3 * x ^ 2 + f _y3 * x * y + g _y3 * y ^ 2 + h _y3 * x + j _y3 * y + _ky3 (Formula 1)
On the other hand, in the primary correction,
dx ₁ = h _x1 * x + j _x1 * y + k _x1
dy ₁ = h _y1 * x + j _y1 * y + _{ky 1} (Formula 2)
Where the higher-order term coefficients a _xi , b _xi , c _xi , d _xi , e _xi , f _xi , g _xi , a _yi , b _yi , c _yi , d _yi , _Multiplying e _yi , f _yi , g _yi (i = 1, 3) by a weighting coefficient α,
dx ₃ '= α (a _x3 * x ^ 3 + b _x3 * x ^ 2 * y + c _x3 * x * y ^ 2 + d _x3 * y ^ 3 + e _x3 * x ^ 2 + f _x3 * x * y + g _x3 * y ^ 2 + h _x3 * x + j _x3 * Y + k _x3 )
+ (1-α) (h _x1 * x + j _x1 * y + k _x1 )
dy ₃ '= α (a _y3 * x ^ 3 + b _y3 * x ^ 2 * y + c _y3 * x * y ^ 2 + d _y3 * y ^ 3 + e _y3 * x ^ 2 + f _y3 * x * y + g _y3 * y ^ 2 + h _y3 * x + j _y3 * Y + _ky3 )
+ (1-α) (h _y1 * x + j _y1 * y + k _y1 ) (Formula 3)
It becomes.

  Therefore, as described above, each coefficient is set as α = 0.5, which is an overlay correction value (weighting coefficient) intermediate between the overlay correction value of the primary correction model and the overlay correction value of the tertiary correction model. Recalculation and lithography processing is performed by weighted tertiary correction.

<Example of positioning for weighted tertiary correction>
FIG. 4 is an explanatory diagram showing an example of the overlay inspection result (linear correction) in the process of step S102 of FIG. FIG. 5 is an explanatory diagram showing an example of the result of overlay inspection (weighted third-order correction) in the process of step S105 of FIG. 3, and FIG. 6 shows the result of overlay inspection by higher-order correction (third-order correction). It is explanatory drawing which shows an example of anticipation.

  Since FIG. 4 is a linear correction, the weighting coefficient is α = 0, and in the case of FIG. 5, the weighting coefficient is α = 0.5 as the weighted third-order correction. Further, since FIG. 6 is the third-order correction, the weighting coefficient is α = 1.

  The arrows shown in FIGS. 4 to 6 indicate residual values. This residual value is distortion in the semiconductor wafer W that cannot be corrected after linear correction, weighted third-order correction, or third-order correction. The residual value is indicated by a vector, for example, and indicates that the residual value increases as the vector becomes longer.

  As shown in FIGS. 4 to 6, in the case of the weighted third-order correction with the weighting coefficient α = 0.5 (FIG. 5), the linear correction shown in FIG. 4 and the third-order correction shown in FIG. Residual value can be obtained.

  FIG. 7 is an explanatory diagram showing an example of an alignment image by weighted third order correction.

  In FIG. 7, a range indicated by a rectangle indicates a process allowable range PPA indicating that the semiconductor wafer W is within an allowable range of overlay deviation. In the center of the process allowable range PPA, alignment is performed. The target position TPS is shown.

  A cross mark indicated by a dotted line indicates a correction target position PS1 by linear correction. A cross mark indicated by a one-dot chain line indicates a correction target position PS3 by tertiary correction. A cross mark indicated by a solid line indicates a corrected target position PS2 corrected so as to be approximately halfway between the corrected target position PS1 by linear correction and the corrected target position PS3 by third-order correction by weighted third-order correction.

  As shown in FIG. 7, when the linear correction with the weighting coefficient α = 0 is used, the correction target position PS1 is greatly deviated from the alignment target position TPS and deviates from the process allowable range PPA.

  In this case, when the process is within the permissible range of the process permissible range PPA, the correction target position PS1 is adjusted to the vicinity of the target position TPS for alignment by third-order correction (weighting coefficient α = 1). It is necessary to be within the allowable range of the range PPA.

  However, here, the correction target position PS2 is intentionally subjected to weighted third-order correction (weighting coefficient α = 0.5) so that the correction target position PS2 is intermediate between the correction target position PS1 and the correction target position PS3. Adjustment is performed so that the position PS2 is within the allowable range of the process allowable range PPA.

  FIG. 8 is an explanatory diagram illustrating an example of an alignment image in the next process in which the weighted tertiary correction is performed in FIG.

  Also in FIG. 8, the range indicated by the rectangle indicates the process allowable range PPA indicating that it is within the allowable range of overlay deviation, and the alignment target position TPS1 is at the center of the process allowable range PPA. Is shown.

  In FIG. 8, since the alignment pattern is formed at the position of the correction target position PS2 in FIG. 7, the correction target position PS2 becomes the target position TPS1. In the next step in which the weighted third-order correction is performed in FIG. 7, when the third-order correction is performed, an alignment pattern can be formed at the correction target position PS4 indicated by the one-dot chain line. In addition, when linear correction is performed in the next step in which weighted tertiary correction is performed in FIG. 7, an alignment pattern can be formed at the correction target position PS5 indicated by the dotted line.

  In any case, the formation of the alignment pattern falls within the region of the process allowable range indicating the allowable range of the process. Therefore, in the next process, it is desirable to apply linear correction that has a high throughput and that facilitates correction in the next process.

  In this way, when weighted third order correction is performed, the target position correction portion by linear correction can be performed in the next step, and conversion from higher order correction to linear correction can be made possible.

  On the other hand, as shown in FIG. 7, when the correction target position PS1 cannot be set within the process allowable range PPA by linear correction, the third-order correction (the correction shown in FIG. 7) is performed so as to be within the process allowable range PPA. Only the target position PS3) could be performed.

  Therefore, in the next process, it is necessary to repeat high-order correction without entering the process allowable range PPA at the correction position by linear correction. In order to repeat high-order correction, it is necessary to perform measurement with a large number of alignment marks, which leads to a decrease in throughput.

  As described above, the linear correction can be performed in the next process in which the weighted third-order correction is performed. Therefore, the linear correction in the next process can be applied, and the semiconductor manufacturing throughput can be improved.

  The manufacturing method of the semiconductor device described in the first embodiment has the following processing.

  A first lithography process for processing the first film, a second lithography process for processing the second film, and a third lithography process for processing the third film.

  In the first lithography process, the amount of misalignment between layers is corrected by approximating the amount of deviation measured in the alignment inspection with two or more higher-order correction equations. In the second lithography process, the overlay deviation amount between layers is corrected by approximating the higher-order correction formula by a weighted higher-order correction formula obtained by multiplying the coefficient of less than 1 by one. In the third lithography process, the overlay deviation amount between layers is corrected by approximation using a linear correction equation.

  Moreover, the manufacturing method of the semiconductor device described in the first embodiment includes the following processes.

  The coefficient used in the weighted higher-order correction formula is calculated based on overlay inspection that measures the relative positional shift amount (overlay shift) between the resist pattern and the inspection pattern formed in the previous process.

(Embodiment 2)
In the first embodiment, the example in which the high-order component is reduced by performing the linear correction after performing the weighted third-order correction has been described. However, in the second embodiment, the process is performed over a plurality of steps. A case where higher order components are reduced will be described.

<Example of overlay correction processing>
FIG. 9 is a flowchart showing an example of the alignment process between the semiconductor wafer and the mask in each manufacturing process according to the second embodiment.

  First, in the contact hole forming step (CONT), after overlay correction between layers is performed by third-order correction (weighting coefficient α = 1) (step S201), overlay inspection is performed.

  Subsequently, in the first wiring layer forming step (M1), after overlay correction between layers is performed by weighted tertiary correction (step S202), overlay inspection is performed. At this time, the weighting coefficient α is set to 0.75.

  Then, in the first via hole forming step (V1), after overlay correction between layers is performed by weighted tertiary correction (step S203), overlay inspection is performed. Here, it is assumed that the weighting coefficient α = 0.5, which is a smaller value than that in the process of step S202.

  Thereafter, in the second wiring layer forming step (M2), the overlay correction between layers is performed by weighted tertiary correction (step S204), and then the overlay inspection is performed. In this case, the weighting coefficient α is set to a weighting coefficient α = 0.25 that is smaller than that in the process of step S203.

  Then, in the second via hole forming step (V2), after overlay correction between layers is performed by linear correction (step S205), overlay inspection is performed. Subsequently, in the third wiring layer forming step (M3), after overlay correction between layers is performed by linear correction (step S206), overlay inspection is performed.

<Application example of weighting coefficient α>
FIG. 10 is an explanatory diagram showing an example of the alignment inspection result before the process of step S201 of FIG. FIG. 11 is an explanatory diagram showing an example of the alignment test result in the process of step S201 in FIG. 9, and FIG. 12 is an explanatory diagram showing an example of the alignment test result in the process of step S202 in FIG. FIG. 13 is an explanatory diagram showing an example of an alignment inspection result in the process of step S206 of FIG.

  The arrows shown in FIGS. 11 to 13 indicate residual values. This residual value is distortion in the semiconductor wafer W that cannot be corrected after linear correction, weighted third-order correction, or third-order correction. The residual value is indicated by a vector, for example, and indicates that the residual value increases as the vector becomes longer.

  First, in the process of step S201, the distortion of the semiconductor wafer shown in FIG. 10 is corrected by the third order so that the residual value shown in FIG. 11 is obtained. Here, in the contact hole forming step, high accuracy is required for overlay between layers, and therefore correction by tertiary correction is performed.

  Subsequently, in the process of step S202, the residual value shown in FIG. 12 is corrected by performing weighted cubic correction with a weighting coefficient α = 0.75. Then, in the process of step S203, weighted tertiary correction is performed with a weighting coefficient α = 0.5, and in the process of step S204, weighted tertiary correction is performed with a weighting coefficient α = 0.25.

  Then, in the processes in steps S205 and S206, linear correction is performed, and in the second wiring layer forming process, which is the process in step S206, correction is performed so that the residual value shown in FIG. 13 is obtained.

  In this way, by setting the weighting coefficient α of the weighted third-order correction to a small value stepwise, it becomes possible to finally convert to linear correction even for a semiconductor wafer having a large high-order component.

<Changes in residual values>
FIG. 14 is an explanatory diagram showing the transition of the residual value in the alignment inspection by the processing of FIG. 10 and the residual value in the overlay inspection.

  In FIG. 14, the horizontal axis indicates the manufacturing process, and the vertical axis indicates the non-linear residual 3σ (non-linear distortion of the semiconductor wafer). In the manufacturing process, CONT is a contact hole forming process, M1 is a first wiring layer forming process, V1 is a first via hole forming process, M2 is a second wiring layer forming process, V2 is a second via hole forming process, and M3 is a third wiring. A layer forming step, V3 indicates a third via hole forming step, and M4 indicates a fourth wiring layer forming step.

  The thick line indicates the allowable range of the overlay deviation amount between layers, and the solid line indicates the residual value of the overlay inspection. The dotted line indicates the residual value of the alignment inspection, and the alternate long and short dash line indicates the prediction of the semiconductor wafer non-linear residual value that seems to be actually changing.

  The difference between the semiconductor wafer nonlinear residual value indicated by the one-dot chain line and the overlay inspection residual value is considered to be a high-order component corrected in each manufacturing process. As shown in the figure, the residual value of the alignment inspection indicated by the dotted line is smaller every time the manufacturing process is performed, and is stabilized after the third wiring layer forming process (M3).

  On the other hand, the residual value of the overlay inspection is larger than that after the third wiring layer forming step (M3), but has changed by about 0.01 μm or less, and the allowable range of overlay between layers indicated by a bold line (Process tolerance) is satisfied.

  Here, the allowable range of overlay between layers is, for example, about 0.01 μm in the contact hole forming step (CONT), and in the manufacturing steps after the first wiring layer forming step (M1), for example, 0. It is about 015 μm.

  In this case, the weighting coefficient α is gradually reduced to 0.75, 0.5, and 0.25, thereby gradually reducing the higher-order correction component, and the second via hole forming step (V2). Subsequent overlay correction by linear correction is possible in subsequent manufacturing processes.

  Also by the above, it is possible to correct the overlay deviation by linear correction, and it is possible to improve the throughput of semiconductor manufacturing.

  The method for manufacturing a semiconductor device described in this embodiment includes the following processes.

  The first lithography step is a contact hole forming step, and the second lithography step calculates a coefficient of a weighted higher-order correction formula from a deviation amount measured in the alignment inspection of the contact hole forming step.

  Also, the coefficient used in the weighted higher-order correction formula is calculated based on overlay inspection that measures the relative positional shift amount (overlay shift) between the resist pattern and the inspection pattern formed in the previous process. .

(Embodiment 3)
FIG. 15 is an explanatory diagram showing an example of the residual value of the semiconductor wafer by linear correction, and FIG. 16 is an explanatory diagram showing an example of the residual value at the time of the third-order weighting correction in the semiconductor wafer of FIG. FIG. 17 is an explanatory diagram showing a predicted relationship between the weighting coefficient α and the residual value.

<Overview>
In the third embodiment, the residual value when the weighting coefficient α is changed as shown in FIG. 17 is predicted from the comparison between the residual value by the linear correction and the residual value by the third-order correction, and overlapping between layers is performed. A value of the weighting coefficient α that is smaller than the allowable value of the misalignment amount is determined.

  When the weighting coefficient α is 0 (linear correction), as shown by the thick line in FIG. 15, there are cases where the overlay deviation amount is outside the allowable range (a value larger than about 15 nm). By setting the weighting coefficient α to 0.2, as shown in FIG. 16, all residual values can be within an allowable range of the overlay deviation amount (about 15 nm or less).

  In FIG. 17, when the weighting coefficient α is 0 and 0.1, the overlay deviation amount is outside the allowable range. Here, the thick line in FIG. 17 indicates the allowable value of the overlay deviation amount, and the lower part of the thick line is within the allowable value.

  Therefore, the weighting coefficient α may be determined to be 0.2 or more, but it is desired to make the weighting coefficient α as close to linear correction as possible. Therefore, from FIG. 17, it is the weighting coefficient α = 0.2 that the overlay deviation amount is within the allowable range in a state close to linear correction (the smallest weighting coefficient α). The coefficient α is determined to be 0.2.

<Example of determining weighting coefficient α>
FIG. 18 is a flowchart illustrating an example of weighting coefficient determination processing according to the third embodiment.

  First, the weighting coefficient α = 0 (linear correction) is started (step S301), and the correction value when the weighting coefficient α = 0 (linear correction) is determined from the alignment measurement in the previous process or the overlay inspection result in the corresponding process. An expected correction result (residual value) is calculated (step S302).

  It is determined whether or not the predicted correction result (residual value) is a value that can be tolerated by the process (allowable value of overlay deviation between layers) (step S303). The tolerance is determined from product requirements. In the process of step S303, if the residual value (= uncorrectable overlay deviation) is smaller than the allowable value, the alignment accuracy can be maintained even by linear correction with the weighting coefficient α = 0, so the weighting coefficient α = 0. It is determined (step S304).

  Further, in the process of step S303, when the residual value (= uncorrectable overlay deviation) is larger than the allowable value, the alignment accuracy cannot be maintained unless the weighting coefficient α is increased.

  Therefore, the value of the weighting coefficient α is increased (step S305), and the process of step S302 is executed. The processes of steps S302, S303, and S305 are repeatedly executed until the residual value (= uncorrectable overlay deviation) in the process of step S303 is smaller than the allowable value.

  Here, the processing of steps S302, S303, and S305 will be described in detail.

  In the process of step S305, since it is desired to make the shape as close to linear correction as possible, the increase value of the weighting coefficient α is desired to be small. Therefore, the increase value of the weighting coefficient α in the process of step S305 is set to 0.1, for example. Here, the increase value of the coefficient α is 0.1, but the increase value may be other than 0.1 (for example, 0.05, 0.2, etc.).

  First, in the process of step S303, when the residual value (= uncorrectable overlay error) is larger than the allowable value, the value of the weighting coefficient α is increased in the process of step S305.

  As described above, since the increment value of the weighting coefficient α is set to 0.1, here, the weighting coefficient α = 0 is increased to the weighting coefficient α = 0.1. Thereafter, recalculation is performed with the weighting coefficient α = 0.1 (step S302), and the residual value is compared with the allowable value (step S303).

  If the residual value falls below the allowable value, the weighting coefficient α = 0.1 is applied (α value determination) (step S304), and if it exceeds, the value of the weighting coefficient α is increased again (step S305).

  Here, recalculation is performed with the weighting coefficient α = 0.2 (step S302), and the residual value is compared with the allowable value (step S303). If the residual value falls below the allowable value, the weighting coefficient α = 0.2 (α value determination) is applied (step S304). If the residual value exceeds the allowable value in the process of step S303, the value of the weighting coefficient α is increased again (step S305).

  In this way, the value of the weighting coefficient α is gradually increased, and the processes in steps S302, S303, and S305 are repeated until the residual value becomes smaller than the allowable value. Depending on the state of the semiconductor wafer, the weighting coefficient α varies, for example, from 0.1 to 0.9.

  Therefore, it is difficult to fix the value of the weighting coefficient α, and by determining the value of the weighting coefficient α by the processing shown in FIG. 15, it is possible to cope with the situation for each semiconductor wafer.

  Therefore, it is possible to reduce the deviation from the allowable value compared to the case where the value of the weighting coefficient α is fixed. In addition, since the weighting coefficient α is selected as a state closer to linear correction, the number of steps required for conversion can be reduced compared to the case of gradually converting to linear correction in a plurality of manufacturing processes. it can.

<Decomposition example of higher-order components>
FIG. 19 is an explanatory diagram illustrating an example of decomposition of higher-order components in the alignment error.

  In FIG. 19, the horizontal axis represents the weighting coefficient α, and the vertical axis represents the superposition residual value.

  As shown in the figure, the higher-order component is decomposed into a random component RDM, an absorption component ASR, and a carry-over component TFR. The random component RDM is a higher-order component that cannot be corrected, and the absorption component ASR is a higher-order component that can be corrected in the process. The carry-over portion TFR is a high-order component carried over to the next process.

  Specifically, the distance between the correction target position PS2 and the correction target position PS3 in FIG. 7 of the first embodiment is the absorption amount ASR, and the distance between the correction target position PS2 and the correction target position PS1 is the carryover amount. TFR.

  In the case of FIG. 14 of the second embodiment, the higher-order component corrected in the corresponding process (the prediction of the semiconductor wafer non-linear residual value indicated by the one-dot chain line and the residual value of the overlay inspection indicated by the solid line) Is the carry-over TFR. The absorption ASR is a difference between the prediction of the semiconductor wafer nonlinear residual value in the corresponding process and the prediction of the semiconductor wafer nonlinear residual value in the next process.

  The superposition residual is the sum of the absorption component ASR and the random component RDM that is difficult to correct. As the higher-order correction weighting coefficient α is increased from 0 to 1, the absorption component ASR decreases and the carry-over component TRF increases. . By setting the superposition residual to the weighting coefficient α that is lower than the superposition deviation allowable value, it is possible to reduce the possibility that the superposition residual is outside the allowable value.

  From another point of view, since it is a process of reducing the carry-over amount TRF, it is possible to facilitate the follow-up with linear correction in the next step.

<About tertiary correction and weighted tertiary correction>
As a matter required to achieve device performance, it is necessary to satisfy “overlapping deviation amount” ≦ “overlapping deviation allowable amount”. Here, the overlay deviation amount remaining when ideally corrected is a residual value, and always “residual value” ≦ “(actual) overlay deviation amount”.

  Therefore, the condition “residual value” ≦ “overlapping deviation tolerance” should be achieved. In order to reduce the residual value, for example, in a process in which the base high-order component is large and the overlay displacement tolerance is small compared to other processes, such as the contact hole forming process (CONT). Therefore, it is necessary to take measures by high order correction.

  Then, in the next step, for example, the first wiring layer forming step (M1), the ground high-order component is maintained in a large state. Here, the allowable amount of misalignment in the first wiring layer forming process is a gentler allowance than that in the contact hole forming process, but the residual value in linear correction for a semiconductor wafer having a higher-order component is large. Therefore, the device performance cannot be satisfied (overlapping deviation cannot be allowed).

  Therefore, it is necessary to perform third (high) order correction that can reduce the residual value. This is because the residual value can only be increased (hereinafter referred to as “large”) (linear correction) or decreased (hereinafter referred to as “small”) (third-order correction).

  Then, the same process is repeated in the subsequent processes, and it becomes necessary to repeat the high-order correction until the (large) process in which the allowable amount of overlap is less than that in the first wiring layer forming process.

  High-order correction requires measurement with a large number of alignment marks, which leads to a reduction in throughput, and application to many processes decreases productivity.

  The following is a technique for performing high-order correction studied by the present inventors, and several methods are conceivable.

  First, the first technique calculates a third-order correction equation using the alignment measurement result. In order to calculate the third-order correction formula, it is necessary to measure many alignment marks on the semiconductor wafer (multi-point measurement), and the throughput of the exposure apparatus is reduced.

  The second technique is the same as the first technique in the first process, but reduces the number of alignment mark measurements in the subsequent processes. As the high-order correction formula, the one calculated in the first step is used. In this case, since a correction formula (correction coefficient) is used between processes, it is necessary to construct a complex advanced process control (APC) system.

  The third technique performs a closed process in each process. Optimal conditions are derived from the processing conditions and inspection results, and the processing conditions for the next lot (Lot) are reviewed. Again, in this case, it is necessary to construct a complicated APC system.

  As described above, in any technique, high-order correction is performed in all steps, and the overlay inspection needs to measure many points.

  Also in the first to third embodiments, the correspondence in the first step is the same as the first technique described above. The difference lies in whether the residual value is increased or decreased as described above for the first wiring layer forming step (M1) or the like where the overlay displacement tolerance is “medium”, and any arbitrary value therebetween Value (hereinafter referred to as medium).

  Since “underlying high-order component” − “high-order component to be corrected in the corresponding process” = “residual value”, in order to set the residual value to a medium level, the high correction in the first wiring layer forming step (M1). Make the next ingredient moderate.

  Further, since the next step of the first wiring layer forming step (M1), for example, “the higher order component of the first via hole forming step (V1)” = “the higher order component corrected in the first wiring layer forming step”. This leads to making the base higher-order component in the first via hole forming step (V1) smaller than that in the first wiring layer forming step. Therefore, linear correction can be performed in the first via hole forming step (V1) in which the overlay deviation allowable amount is “medium”.

  The method for manufacturing a semiconductor device described in the third embodiment has the following processing.

  The coefficient used in the weighted higher-order correction formula is closest to the linear correction formula among the numerical values in which the residual value indicating the overlay deviation that cannot be corrected is smaller than the tolerance of the overlay deviation in the third lithography process. Value.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

W Semiconductor wafer CP1 Circuit pattern KP1 Inspection pattern AP1 Alignment pattern ISO Interlayer insulating film RST Resist RP1 Resist pattern EXS Exposure apparatus STG Wafer stage AMS Alignment mark measurement unit OPE Calculation unit CON Control unit LEN Exposure processing unit

Claims (9)

A first lithography step of processing the first film by correcting the overlay displacement amount between the layers by approximating the displacement amount measured in the alignment inspection by two or more higher-order correction equations;
A second lithography step of processing a second film by correcting the overlay deviation amount between layers by approximating the higher-order correction formula by a weighted higher-order correction formula obtained by multiplying a coefficient of less than 1;
And a third lithography step of processing the third film by correcting the overlay deviation amount between the layers by approximation by a linear correction formula. In the manufacturing method of the semiconductor device according to claim 1,
Between the second lithography step and the third lithography step, the overlay deviation amount between layers is corrected by approximating the higher-order correction equation by a weighted higher-order correction equation obtained by multiplying the higher-order correction equation by a coefficient less than 1. A method for manufacturing a semiconductor device, comprising one or more fourth lithography steps for processing the fourth film. The method of manufacturing a semiconductor device according to claim 2.
The coefficients used in the weighted higher-order correction formula are:
A method of manufacturing a semiconductor device, wherein a smaller coefficient is used as the process proceeds to the third lithography process side which is a downstream process. In the manufacturing method of the semiconductor device according to claim 1,
The coefficients used in the weighted higher-order correction formula are:
A method of manufacturing a semiconductor device, which is a value closest to the linear correction formula among numerical values in which a residual value indicating an overlay error that cannot be corrected is smaller than an allowable range of overlay error in the third lithography step. In the manufacturing method of the semiconductor device according to claim 1,
The first lithography step includes
A contact hole forming process,
The second lithography step includes
A method of manufacturing a semiconductor device, wherein a coefficient of a weighted higher-order correction formula is calculated from a deviation amount measured in an alignment inspection in the contact hole forming step. The method of manufacturing a semiconductor device according to claim 2.
The first lithography step includes
A contact hole forming process,
The second and fourth lithography steps include
A method of manufacturing a semiconductor device, wherein a coefficient of a weighted higher-order correction formula is calculated from a deviation amount measured in an alignment inspection in the contact hole forming step. The method of manufacturing a semiconductor device according to claim 6.
The weighted higher-order correction formula of the fourth lithography step is
A method of manufacturing a semiconductor device, wherein a coefficient having a smaller value than a coefficient used in a weighted higher-order correction formula in the second lithography process is used. In the manufacturing method of the semiconductor device according to claim 1,
The coefficient used in the weighted higher-order correction formula is
A method for manufacturing a semiconductor device, which calculates based on overlay inspection for measuring a relative displacement amount between a resist pattern and an inspection pattern formed in a previous process. The method of manufacturing a semiconductor device according to claim 2.
The second and fourth lithography steps include
A method of manufacturing a semiconductor device, wherein a coefficient used in the weighted higher-order correction equation is calculated based on an overlay inspection that measures a relative displacement amount between a resist pattern and an inspection pattern formed in a previous process.

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