CN116381998A - Display panel, display device, display mother board and manufacturing method of display mother board - Google Patents

Abstract

The application provides a display panel, the display panel includes display area and binding area, and the display panel includes array substrate, and array substrate includes first substrate. The display panel further comprises a test wire and a first resistor element, the test wire is arranged on one side of the first substrate and located in the binding area, the first resistor element covers the test wire on the first substrate, a first groove is formed by surrounding the first resistor element, the test wire and the first substrate, and an opening of the first groove faces one side of the binding area opposite to the display area. The first groove is used for filling conductive solution, and after the display panel is formed, the conductive solution in the first groove flows out. Therefore, due to the existence of the first groove, the conductive adhesive tape can not be contacted with the surface of the test wiring exposed out of the first groove, and further the test wiring can not be short-circuited, so that poor display of the display panel is avoided, and the reliability of the display panel is improved. The application also provides a display device, a display motherboard and a manufacturing method of the display motherboard.

Description

Display panel, display device, display motherboard and manufacturing method thereof

technical field

The present application relates to the field of display technology, and in particular to a display panel, a display device with the display panel, a display motherboard with the display panel, and a method for manufacturing the display motherboard.

Background technique

Liquid crystal display devices have been widely used in people's lives and work because of their thin body, low power consumption, and low price. A liquid crystal display device generally includes a display panel and a backlight module, and the display panel is formed by cutting a display motherboard.

In the design of the display panel, a plurality of test traces are usually provided in the non-display area of the display panel for testing the conduction of each display panel on the display motherboard. When the display motherboard is cut to form multiple display panels, the test traces will be exposed from the sides of the display panels. In the subsequent process, a conductive adhesive tape will be pasted on the side of the display panel, and the conductive adhesive tape will easily be electrically connected to the exposed test wires, resulting in a short circuit of the test wires, which in turn leads to poor display on the display panel.

Therefore, how to solve the problem of poor display caused by the short circuit of the exposed test wires of the display panel in the prior art is an urgent problem to be solved by those skilled in the art.

Contents of the invention

In view of the deficiencies in the prior art above, the purpose of this application is to provide a display panel, a display device with the display panel, a display motherboard with the display panel, and a method for manufacturing a display motherboard. The invention solves the problem in the prior art that the test wiring exposed on the display panel is short-circuited and causes poor display.

In order to solve the above technical problems, an embodiment of the present application provides a display panel, the display panel includes a display area and a binding area arranged on one side of the display area, the display panel includes an array substrate, and the array substrate includes A first substrate, a portion of the first substrate is located in the bonding region. The display panel also includes a plurality of test lines and a plurality of first resistance elements, the test lines are arranged on one side of the first substrate and located in the binding area, and electrically connected to the array substrate connected, the first resistance element partially covers the test line on the first substrate, and the first resistance element, the test line and the first substrate surround to form a first A groove, the opening of the first groove faces the surface side of the binding area facing away from the display area. Wherein, the first groove is used for filling a conductive solution, and the conductive solution in the first groove flows out after the display panel is formed.

To sum up, the display panel provided by the embodiment of the present application retracts the test traces on the side of the binding area facing away from the display area, and the conductive adhesive tape will not interfere with multiple test traces. The surface of the line exposed to the first groove is in contact, so that the test line will not be short-circuited, which avoids the display failure of the display panel and improves the reliability of the display panel. Moreover, the display panel is not cut, and the test wiring is electrically connected to the test component through the conductive solution, and then the test component can provide the test electrical signal to the display panel to test the display panel.

In an exemplary embodiment, the display panel further includes a plurality of insulating elements, and the insulating elements are filled in the first groove, so as to insulate and support the surface of the test trace facing away from the display area. the first resistive element.

In an exemplary embodiment, the first resistance element further includes a chamfered end, and the chamfered end is an end of the first resistance element facing away from the display area. Wherein, when the test line points to the direction of the first resistance element, the slope of the chamfered end is inclined in the direction where the display area is located; or, when the first resistance element points to the direction of the test line direction, the slope at the chamfered end is inclined in the direction in which the display area is located.

In an exemplary embodiment, the binding area further includes a first flat area and a plurality of first recessed areas, wherein the plurality of first recessed areas are arranged at intervals, and a part of the circumference of each of the first recessed areas The side is wrapped by the first flat area, and the side of the first recessed area facing away from the display area exposes the first flat area. The first groove is located in the first recessed area, and the highest point of the sidewall of the first groove is less than or equal to that of the first substrate located in the first flat area facing the test The height of the surface of the trace.

Based on the same inventive concept, an embodiment of the present application further provides a display device, the display device includes a backlight module and the above-mentioned display panel, and the display panel is arranged on the light emitting side of the backlight module.

To sum up, the display device provided by the embodiment of the present application includes a backlight module and a display panel, and the display panel is retracted on the side of the binding area facing away from the display area through the test trace. The conductive adhesive tape will not be in contact with the surfaces of the plurality of test lines exposing the first groove, and the test lines will not be short-circuited, which avoids poor display of the display panel and improves the display panel reliability. Moreover, the display panel is not cut, and the test wiring is electrically connected to the test component through the conductive solution, and then the test component can provide the test electrical signal to the display panel to test the display panel.

Based on the same inventive concept, an embodiment of the present application further provides a display motherboard, the display motherboard includes a test assembly and the above-mentioned display panel, and the test assembly includes a second substrate, a plurality of conductive traces, and a plurality of first Two resistive elements, wherein the second substrate is connected to the first substrate and arranged on the same layer, the conductive traces are arranged on the same layer as the test traces and arranged at intervals, and the second resistive element connects the The conductive traces are partly covered on the second substrate, and connected to the first resistance element and arranged on the same layer; the second substrate, the conductive traces, and the second resistance element are in phase with each other. Surrounding to form a second groove, the opening of the second groove faces the opening of the first groove and communicates with the first groove. Wherein, the first groove and the second groove are filled with a conductive solution, and the conductive solution is respectively in contact with the test wiring and the conductive wiring, so as to connect the test wiring and the The conductive traces are electrically connected.

To sum up, the display motherboard provided by the embodiment of the present application includes a test module and a display panel, and the display panel is retracted on the side of the binding area facing away from the display area through the test wiring. The conductive adhesive tape will not be in contact with the surfaces of the plurality of test traces exposing the first groove, and the test traces will not be short-circuited, which avoids poor display of the display panel and improves the performance of the display panel. Display panel reliability. Moreover, the display panel is not cut, and the test wiring is electrically connected to the test component through the conductive solution, and then the test component can provide the test electrical signal to the display panel to test the display panel.

In an exemplary embodiment, the binding area further includes a first flat area and a plurality of first recessed areas, wherein the plurality of first recessed areas are arranged at intervals, and a part of the circumference of each of the first recessed areas The side is wrapped by the first flat area, and the side of the first recessed area facing away from the display area exposes the first flat area. The first groove is located in the first recessed area, and the highest point of the sidewall of the first groove is less than or equal to that of the first substrate located in the first flat area facing the test The height of the surface of the trace.

In an exemplary embodiment, the test assembly further includes a second flat area and a plurality of second recessed areas, the plurality of second recessed areas are arranged at intervals, and a part of the peripheral side of each of the second recessed areas is covered by the The second flat area is wrapped, and one side of the second depressed area is connected to the exposed side of the first depressed area. The second groove is located in the second recessed area, and the highest point of the sidewall of the second groove is less than or equal to the second substrate located in the second flat area facing the conductive The height of the surface of the trace.

In an exemplary embodiment, the conductive solution includes a conductive material with a mass ratio of 90% to 98% and an auxiliary material with a mass ratio of 2% to 10%, the conductive material is used for conducting electricity, and the auxiliary material Used to increase the fluidity of the conductive solution.

Based on the same inventive concept, an embodiment of the present application further provides a method for manufacturing a display motherboard, the method for manufacturing a display motherboard is used to manufacture the above-mentioned display motherboard, and the method for manufacturing a display motherboard includes:

An array substrate assembly is provided, the array substrate assembly includes a first substrate and a second substrate;

forming a conductive layer on the first substrate and on the second substrate;

Forming the conductive layer into a plurality of test traces and a plurality of conductive traces, and forming an accommodating space between the test traces and the conductive traces, wherein the accommodating space includes a first groove and a second groove, the test trace and the first groove are located on the first substrate, and the conductive trace and the second groove are located on the second substrate;

filling the accommodating space with a conductive solution;

At least part of a resistance component is formed on a side of the test trace facing away from the first substrate and a side of the conductive trace facing away from the second substrate, so that the resistance component covers the conductive solution , wherein the resistance component includes a first resistance element and a second resistance element, the first resistance element is located on the test trace, and the second resistance element is located on the conductive trace.

To sum up, the display motherboard formed by the method for manufacturing a display motherboard provided in the embodiment of the present application includes a test module and a display panel, and the display panel is retracted from the binding area through the test traces. On one side of the display area, the conductive adhesive tape will not be in contact with the surface of the plurality of test traces exposing the first groove, and the test traces will not be short-circuited, which avoids the display panel Display defects occur and the reliability of the display panel is improved. Moreover, the display panel is not cut, and the test wiring is electrically connected to the test component through the conductive solution, and then the test component can provide the test electrical signal to the display panel to test the display panel.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application. Those of ordinary skill in the art can also obtain other drawings based on these drawings without any creative effort.

FIG. 1 is a schematic structural diagram of a display motherboard disclosed in the first embodiment of the present application;

FIG. 2 is a schematic structural diagram of a display panel disclosed in a second embodiment of the present application;

FIG. 3 is a schematic diagram of the first layer structure of the display panel disclosed in the second embodiment of the present application;

FIG. 4 is a schematic diagram of a first partial layer structure of the display motherboard shown in FIG. 1;

FIG. 5 is a schematic diagram of the second layer structure of the display panel disclosed in the second embodiment of the present application;

FIG. 6 is a schematic diagram of the third layer structure of the display panel disclosed in the second embodiment of the present application;

FIG. 7 is an enlarged schematic diagram of structure VII in the display panel shown in FIG. 6;

FIG. 8 is a schematic diagram of the fourth layer structure of the display panel disclosed in the third embodiment of the present application;

FIG. 9 is a schematic diagram of a plane structure corresponding to the display panel shown in FIG. 8;

FIG. 10 is an enlarged schematic diagram of structure X in the display panel shown in FIG. 8;

FIG. 11 is a schematic diagram of a three-dimensional structure corresponding to the binding area of the display panel shown in FIG. 8;

FIG. 12 is a schematic diagram of a second partial layer structure of the display motherboard shown in FIG. 1;

FIG. 13 is a schematic plan view of the display motherboard shown in FIG. 12;

FIG. 14 is an enlarged schematic view of structure XIIII in the display motherboard described in FIG. 12;

FIG. 15 is a schematic diagram of the layer structure of the display device disclosed in the third embodiment of the present application;

FIG. 16 is a schematic flowchart of a method for manufacturing a display motherboard disclosed in the third embodiment of the present application;

17 is a schematic structural diagram corresponding to step S20a of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application;

FIG. 18 is a schematic flowchart of step S30a of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application;

FIG. 19 is a schematic structural diagram corresponding to step S31a of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application;

FIG. 20 is a schematic structural diagram corresponding to step S32a of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application;

FIG. 21 is a schematic structural diagram corresponding to step S40a of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application;

FIG. 22 is a schematic structural diagram corresponding to step S20b of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application;

FIG. 23 is a schematic structural diagram corresponding to step S30b of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application;

FIG. 24 is a schematic structural diagram corresponding to step S40b of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application;

FIG. 25 is a schematic structural diagram corresponding to step S50b of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application.

Explanation of reference signs:

1-display area; 2-non-display area; 4-test wiring; 6-insulation component; 10-display panel; 10a-display panel; 10b-display panel; 10c-display panel; 11-array substrate; 13-liquid crystal layer; 15-color film substrate; 16-sealing glue; 17-shielding layer; 18-first resistance element; 18a-chamfered end; 19-conductive gel; 20-test component; 20a-second flat area; 20b-second recessed area; 21-test element; 23-second substrate; 24-conductive wiring; 26-second resistance element; 40-test wiring assembly; 41-conductive solution; 60-conductive layer; 70 -resistor assembly; 80-accommodating space; 100-display motherboard; 100a-display motherboard; 100b-display motherboard; 111-first substrate; 113-drive circuit layer; 115-insulating layer; 131-liquid crystal molecules 200-display device; 201-binding area; 201a-first flat area; 201b-first recessed area; a-first groove; b-second groove. S10-S50-show the steps of the method for making the motherboard; S10a-S50a-show the steps of the method for making the motherboard; S31a-S32a-show the steps of step S30a; S10b-S50b-show the steps of the method for making the motherboard.

Detailed ways

In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Preferred embodiments of the application are shown in the accompanying drawings. However, the present application can be embodied in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the application more thorough and comprehensive.

The following descriptions of the various embodiments refer to the accompanying drawings to illustrate specific embodiments that the present application can be used to implement. The serial numbers assigned to components in this document, such as "first", "second", etc., are only used to distinguish the described objects, and do not have any sequence or technical meaning. The "connection" and "connection" mentioned in this application all include direct and indirect connection (connection) unless otherwise specified. The directional terms mentioned in this application, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., only is to refer to the direction of the attached drawings. Therefore, the direction terms used are for better and clearer description and understanding of the present application, rather than indicating or implying that the referred device or element must have a specific orientation, and must have a specific orientation. construction and operation, therefore should not be construed as limiting the application.

In the description of this application, it should be noted that unless otherwise specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Ground connection, or integral connection; can be mechanical connection; can be directly connected, can also be indirectly connected through an intermediary, and can be internal communication between two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application in specific situations. It should be noted that the terms "first" and "second" in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the term "comprising", "may include", "comprises", or "may include" used in this application indicates the existence of the corresponding disclosed functions, operations, elements, etc., and does not limit other one or more more Functions, operations, components, etc. In addition, the term "comprises" or "comprises" means that there are corresponding features, numbers, steps, operations, elements, components or combinations thereof disclosed in the specification, and does not exclude the existence or addition of one or more other features, numbers, steps, Operations, elements, components, or combinations thereof, are intended to cover non-exclusive inclusions. It should also be understood that the meaning of "at least one" described herein is one or more, such as one, two or three, etc., and the meaning of "multiple" is at least two, such as two or three etc., unless expressly and specifically defined otherwise.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terminology used herein in the description of the application is only for the purpose of describing specific embodiments, and is not intended to limit the application.

Please refer to FIG. 1 . FIG. 1 is a schematic structural diagram of a display motherboard disclosed in a first embodiment of the present application. In the embodiment of the present application, the display motherboard 100 includes a plurality of display panels 10 and at least one test component 20, the test component 20 is connected between two adjacent display panels 10, and the test The assembly 20 is electrically connected to two adjacent display panels 10 , and the testing assembly 20 is used to provide a test electrical signal to the display panels 10 to test the display panels 10 . Wherein, testing the display panel 10 refers to: testing the continuity of the circuit of the display panel 10 and testing the light emission of the display panel 10 .

In the implementation manner of the present application, please refer to FIG. 1 and FIG. 2 together. FIG. 2 is a schematic structural diagram of the display panel disclosed in the second embodiment of the present application. The display panel 10 includes a display area 1 and a non-display area 2 surrounding the display area 1 . The display area 1 is used for image display, and the non-display area 2 is used for setting other auxiliary display components or modules and signal lines.

In an exemplary embodiment, the display area 1 of the display panel 10 includes a plurality of pixel units (not shown) distributed in an array, and the plurality of pixel units are used for performing image display.

In the embodiment of the present application, please refer to FIG. 1 , the display motherboard 100 further includes a plurality of test wiring assemblies 40 , and the plurality of test wiring assemblies 40 are located in the non-display area 2 of the display panel 10 And the area where the test component 20 is located. The test assembly 20 includes a test element 21, the test element 21 is connected to a plurality of the test wire assemblies 40 to be electrically connected, and the test element 21 is used to pass the test wire assembly 40 to the display panel. 10 provides the test electrical signal.

In an exemplary embodiment, the plurality of test wire assemblies 40 located on one display panel 10 are arranged at intervals and parallel to each other, and the plurality of test wire assemblies 40 are insulated from each other.

In an exemplary embodiment, the test element 21 may be a plurality of traces. The test assembly 20 also includes connecting wires, which are electrically connected to the test element 21 to electrically connect the test element 21 to external electronic components or electronic components.

In an exemplary embodiment, the display motherboard 100 is cut along the cutting line Q shown in FIG. 1 to form a plurality of display panels 10 as shown in FIG. Wiring 4 , the testing wiring 4 is a part of the testing wiring assembly 40 , and the testing wiring 4 is located in the non-display area 2 . A plurality of the test wires 4 can be spaced apart and arranged in parallel, and the multiple test wires 4 are insulated from each other. The non-display area 2 also includes a binding area 201, the binding area 201 is set on one side of the display area 1, when the display panel 10 is not cut, the binding area 201 and the test The area where the component 20 is located is connected. Wherein, the cutting direction of the cutting line Q is perpendicular to the extending direction of the test wiring 4 .

In the related art, in the display panel formed by cutting, one side of the test wiring exposes the side of the binding area facing away from the display area, and the exposed side of the test wiring is connected to the surface of the binding area facing away from the display area. align.

In the implementation manner of the present application, please refer to FIG. 3 , which is a schematic diagram of the first layer structure of the display panel disclosed in the second embodiment of the present application. The display panel 10 includes an array substrate 11 , a liquid crystal layer 13 , a color filter substrate 15 and a sealant 16 . The array substrate 11 is opposite to the color filter substrate 15 and arranged at intervals, and the liquid crystal layer 13 is arranged between the array substrate 11 and the color filter substrate 15 . The liquid crystal layer 13 is located in the display area 1 , the sealant 16 is disposed in the non-display area 2 , between the array substrate 11 and the color filter substrate 15 and in the liquid crystal layer 13 side of the perimeter. The liquid crystal layer 13 includes a plurality of liquid crystal molecules 131, the array substrate 11 and the color filter substrate 15 are used to form a preset electric field, and the preset electric field is used to drive a plurality of liquid crystal molecules 131 to deflect, so that The display panel 10 displays different gray scales. The sealant 16 is used to seal the liquid crystal layer 13 between the array substrate 11 and the color filter substrate 15 and bond the array substrate 11 and the color filter substrate 15 .

In the embodiment of the present application, please refer to FIG. 3 , the array substrate 11 includes a first substrate 111 , a driving circuit layer 113 and an insulating layer 115 . The first substrate 111 is disposed on the side of the liquid crystal layer 13 facing away from the color filter substrate 15, and is spaced from the liquid crystal layer 13. The first substrate 111 is located in the display area 1 and The non-display area 2. The driving circuit layer 113 is disposed on the side of the first substrate 111 facing the liquid crystal layer 13, and is located in the display area 1 and the non-display area 2, and the insulating layer 115 is disposed on the driving circuit The side of the layer 113 facing away from the first substrate 111 is connected to the sealant 16 , and the insulating layer 115 is used to insulate the liquid crystal layer 13 and the driving circuit layer 113 .

In an exemplary embodiment, the driving circuit layer 113 includes at least a plurality of scanning lines and a plurality of data lines, and the data lines transmit data signals for display to the plurality of pixel units located in the display area 1 , the scan line transmits a scan signal for controlling when the pixel unit receives the data signal.

In an exemplary embodiment, please refer to FIG. 3 , the part of the first substrate 111 is located in the bonding area 201, the test trace 4 is located in the first substrate 111 and the driving circuit layer is provided. 113 and located in the binding area 201. That is, the test wiring 4 and the driving circuit layer 113 are arranged on the same side of the first substrate 111, and the driving circuit layer 113 is not located in the bonding area 201, the testing wiring Line 4 is located in the binding region 201 . The test wiring 4 is electrically connected to the driving circuit layer 113 , and the testing wiring 4 may be electrically connected to the scanning lines of the driving circuit layer 113 to transmit test electrical signals to the scanning lines.

In the embodiment of the present application, please refer to FIG. 3 , the display panel 10 further includes a shielding layer 17, and the shielding layer 17 is arranged on the side of the color filter substrate 15 facing away from the liquid crystal layer 13. Layer 17 is used to shield external electric fields and discharge static electricity. It can be understood that the external electric field will affect the preset electric field, and further affect the deflection of the liquid crystal molecules 131 , resulting in poor display of the display panel 10 . Moreover, if the shielding layer 17 is electrostatically charged, the shielding layer 17 will form an interference electric field with the array substrate 11 , and the interference electric field will affect the deflection of the liquid crystal molecules 131 , resulting in poor display of the display panel 10 .

In the embodiment of the present application, please refer to FIG. 3 , the display panel 10 further includes a plurality of first resistor elements 18 and a plurality of conductive gels 19 . The first resistance element 18 partially covers the test wire 4 on the first substrate 111 and is located in the bonding area 201 . The conductive gel 19 is disposed on the side of the first resistance element 18 facing away from the test wire 4 and located in the bonding area 201 . The conductive gel 19 is connected to the shielding layer 17 and the first resistance element 18 respectively, so as to electrically connect the shielding layer 17 to the first resistance element 18 .

In an exemplary embodiment, the first resistance element 18 may be connected to the insulating layer 115 or may be spaced apart from the insulating layer 115 , which is not specifically limited in the present application. The conductive gel 19 can be connected to the color filter substrate 15 and the sealant 16, and can also be spaced apart from the color filter substrate 15 and the sealant 16. The application is not specifically limited to this.

In an exemplary embodiment, the material of the first resistance element 18 may be indium tin oxide (Indium TinOxide, ITO), which has relatively weak conductivity. Compared with the test wiring 4 , the conductivity of the first resistance element 18 is weaker, that is, the first resistance element 18 is an insulator compared to the test wiring 4 . Therefore, when testing the display panel 10 , the test wire 4 is not electrically connected to the first resistance element 18 , so as to prevent the test electrical signal from being transmitted to the first resistance element 18 . Moreover, the first resistive element 18 has relatively weak conductivity, which can conduct away static electricity on the shielding layer 17 . Wherein, the material of the test wire 4 may include any one or more of metal materials such as platinum, gold, aluminum, copper, titanium, silver, chromium, nickel, etc., which is not specifically limited in the present application.

In an exemplary embodiment, the display panel 10 further includes conductive adhesive tape (not shown in the figure), and the conductive adhesive tape is attached to the first resistor element 18 and the circuit board, so that the first resistor element 18 The element 18 is electrically connected to the circuit board, and the shielding layer 17 is electrically connected to the circuit board, so as to conduct static electricity on the shielding layer 17 . However, in the related art, the conductive adhesive tape is likely to be in contact with the exposed surfaces of a plurality of the test wires 4 , resulting in a short circuit of the test wires 4 , and further resulting in poor display of the display panel 10 .

In the embodiment of the present application, the first resistance element 18 partially covers the test wiring 4 on the first substrate 111 , and the first resistance element 18 and the first substrate 111 Extending the side of the test line 4 facing away from the driving circuit layer 113, the first resistance element 18, the test line 4 and the first substrate 111 surround each other to form a first recess. Groove a, wherein the first resistance element 18 and the first substrate 111 form the sidewall of the first groove a, and the side of the test trace 4 facing away from the driving circuit layer 113 forms the The bottom surface of the first groove a, the opening of the first groove a faces the side of the binding area 201 facing away from the display area 1 . That is, in the direction where the display area 1 points to the binding area 201, the part of the first substrate 111 located in the binding area 201 is longer than the test wiring 4, and the first resistance element 18, the part located in the binding area 201 is also longer than the test wiring 4, thereby forming the first groove a, and the side of the test wiring 4 facing away from the driving circuit layer 113 is the first groove a. The bottom surface of the groove a. The display panel 10 is not cut, and the conductive solution is filled in the first groove a; after the display panel 10 is cut, the conductive solution in the first groove a flows out. That is, the first groove a is used to fill the conductive solution, and the conductive solution in the first groove a flows out after the display panel 10 is formed.

It can be understood that, the test trace 4 is arranged between the first substrate 111 and the first resistance element 18, and forms the bottom wall of the first groove a, that is, the test trace The line 4 is separated from the side of the bonding area 201 facing away from the display area 1 by a distance of the first groove a, and the conductive adhesive tape will not expose the first groove a with a plurality of the test lines 4. The surface of a groove a is in contact, that is, the conductive adhesive tape will not extend into the bottom surface of the first groove a to contact the test wiring 4, and then the test wiring 4 will not be short-circuited, avoiding The display panel 10 has poor display, and the reliability of the display panel 10 is improved. Moreover, when the display panel 10 is not cut, the test wiring 4 is electrically connected to the test component 20 through the conductive solution, and the test component 20 can provide the test circuit 20 to the display panel 10. signal to test the display panel 10 .

In an exemplary embodiment, the display panel 10 may be a display panel of a twisted nematic mode (Twisted Nematic, TN), a display panel of a vertical alignment mode (Vertical Alignment, VA), an in-plane switching mode (In-Plane Switching (IPS) display panel or Fringe Field Switching (Fringe Field Switching, FFS) display panel, which is not specifically limited in the present application.

To sum up, the display panel 10 provided by the embodiment of the present application includes a display area 1 and a binding area 201 disposed on one side of the display area 1 . The display panel 10 includes an array substrate 11 , and the array substrate 11 includes a first substrate 111 , and a part of the first substrate 111 is located in the binding area 201 . The display panel 10 also includes a test line 4 and the first resistance element 18, the test line 4 is set on one side of the first substrate 111 and is located in the binding area 201, the first A resistive element 18 partially covers the test trace 4 on the first substrate 111 and is located in the bonding area 201 . The test wire 4 is used to electrically connect with the array substrate 11 to transmit test electrical signals to the array substrate 11 . The first resistance element 18 , the test wiring 4 and the first substrate 111 surround each other to form a first groove a, and the opening of the first groove a faces to the back of the bonding region 201 on one side of the display area. When the display panel 10 is not cut, the conductive solution is filled in the first groove a; after the display panel 10 is cut, the conductive solution in the first groove a flows out. Therefore, the test wiring 4 is retracted on the side of the binding area 201 facing away from the display area 1, and the conductive adhesive tape will not expose the first groove with a plurality of the testing wiring 4 The surfaces of a are in contact with each other, so that the test wire 4 will not be short-circuited, which avoids display failure of the display panel 10 and improves the reliability of the display panel 10 . Moreover, the display panel 10 is not cut, the test wire 4 is electrically connected to the test assembly 20 through the conductive solution, and the test assembly 20 can provide the test electrical signal to the display panel 10 , to test the display panel 10 .

In the embodiment of the present application, please refer to FIG. 1 and FIG. 4 together. FIG. 4 is a schematic diagram of a first partial layer structure of the display motherboard shown in FIG. 1 . The test component 20 is disposed on a side of the binding area 201 facing away from the display area 1 . The test assembly 20 further includes a second substrate 23 , a plurality of conductive wires 24 and a plurality of second resistance elements 26 . Wherein, the second substrate 23 is arranged on the same layer as the first substrate 111 and connected. The conductive trace 24 is arranged on the side of the test trace 4 facing away from the driving circuit layer 113, and is spaced from the test trace 4, and is connected to the second substrate 23, that is, The conductive traces 24 are arranged on the same layer as the test traces 4 and spaced apart. The second resistor element 26 partially covers the conductive trace 24 on the second substrate 23 , and is connected to the first resistor element 18 and disposed on the same layer. The conductive traces 24 are used to electrically connect with the test element 21 .

In an exemplary embodiment, the material of the second resistance element 26 may be indium tin oxide (Indium TinOxide, ITO), which has relatively weak conductivity. Compared with the conductive wiring 24 , the conductivity of the second resistance element 26 is weaker, that is, the second resistance element 26 is an insulator compared to the conductive wiring 24 . Therefore, when the display panel 10 is tested, the conductive wire 24 is not electrically connected to the second resistance element 26 , so as to prevent the test electrical signal from being transmitted to the second resistance element 26 . The material of the conductive trace 24 may include but not limited to: any one or more of metal materials such as platinum, gold, aluminum, copper, titanium, silver, chromium, nickel, etc., which is not specifically limited in the present application.

In the embodiment of the present application, please refer to FIG. 4 , the second substrate 23 , the conductive wiring 24 and the second resistance element 26 surround each other to form a second groove b, and the second groove The opening of the groove b faces the opening of the first groove a and communicates with the first groove a. The display panel 10 is not cut, and the conductive solution 41 is filled in the second groove b; after the display panel 10 is cut, the conductive solution 41 in the second groove b flows out. That is, the first groove a and the second groove b of the display motherboard 100 are filled with the conductive solution 41 . The conductive solution 41 is in contact with the test wire 4 and the conductive wire 24 respectively, so as to electrically connect the test wire 4 and the conductive wire 24 .

In the embodiment of the present application, the conductive solution 41 includes conductive materials with a mass ratio of 90% to 98%, for example, 90%, 92%, 95%, 97%, 98%, or other values. This is not specifically limited. Wherein, the conductive solution 41 can be one or more of materials such as aluminum silver plating, copper silver plating, glass silver plating and graphite nickel plating. The conductive solution 41 also includes auxiliary materials with a mass ratio of 2% to 10%, for example, 2%, 3%, 5%, 8%, 10%, or other values, which are not specifically limited in this application. Wherein, the auxiliary material can be rubber silicon.

It can be understood that the conductive material is used to conduct electricity, and the auxiliary material is used to increase the fluidity of the conductive solution 41, so that the conductive solution 41 can be connected to the second groove a from the first groove a. Slot b flows out.

In an exemplary embodiment, when the test component 20 points to the bonding area 201, the second substrate 23 is longer than the conductive trace 24, and the second resistance element 26 is longer than the test trace. line 4, and further form the second groove b, and the side of the conductive trace 24 facing the test trace 4 is the bottom surface of the second groove b.

In an exemplary embodiment, the test wire 4 , the conductive solution 41 and the conductive wire 24 constitute the test wire assembly 40 .

In an exemplary embodiment, the distance between the bottom surface of the first groove a and the bottom surface of the second groove b is 50um to 1000um, that is, the test trace 4 and the conductive trace 24 are mutually The distance between the facing surfaces is 50um to 1000um, for example, 50um, 200um, 410um, 500um, 700um, 730um, 870um, 1000um, or other values, which are not specifically limited by the present application.

In an exemplary embodiment, the depth of the first groove a is 15um to 350um, for example, 15um, 50um, 150um, 230um, 300um, 320um, 350um, or other values, which are not specifically limited in the present application. Wherein, the depth of the first groove a refers to the distance from the bottom surface of the first groove a to the opening of the first groove a.

It can be understood that, in order to avoid the size of the first groove a being too large, causing the first resistive element 18 to be unable to support its own weight and rupture, the size of the first groove a should be as small as possible, so the setting The depth of the first groove a is 15um to 350um.

Based on the same inventive concept, please refer to FIG. 5 , which is a schematic diagram of the second layer structure of the display panel disclosed in the second embodiment of the present application. The difference between the display panel 10 a of the second layer structure and the display panel 10 of the first layer structure is that the display panel 10 a of the second layer structure further includes a plurality of insulating elements. For the description of the similarities between the display panel 10a of the second layer structure and the display panel 10 of the first layer structure, please refer to the relevant description of the display panel 10 of the first layer structure, and details will not be repeated here.

Specifically, in the embodiment of the present application, the display panel 10a includes a plurality of insulating elements 6, and the insulating elements 6 are filled in the first groove a, so that the test wiring 4 faces away from the The surface of the display area 1 is insulated, and the insulating element 6 is also used to support the first resistance element 18 to prevent the resistance element 18 from cracking due to lack of support. The surface of the test wiring 4 facing away from the display area 1 is the surface of the testing wiring 4 facing away from the driving circuit layer 113 .

In an exemplary embodiment, the material of the insulating element 6 may be ultraviolet (Ultraviolet, UV) glue or other insulating materials, which are not specifically limited in the present application.

Based on the same inventive concept, please refer to FIG. 6 , which is a schematic diagram of the third layer structure of the display panel disclosed in the second embodiment of the present application. The difference between the display panel 10b of the third layer structure and the display panel 10a of the second layer structure is that the first resistance element 18 of the display panel 10b of the third layer structure also includes a chamfered end. For the description of the similarities between the display panel 10b of the third layer structure and the display panel 10a of the second layer structure, please refer to the related description of the display panel 10a of the second layer structure, and details will not be repeated here.

Specifically, in the implementation manner of the present application, please refer to FIG. 6 and FIG. 7 together. FIG. 7 is an enlarged schematic view of structure VII in the display panel shown in FIG. 6 . The first resistive element 18 also includes a chamfered end 18a, which is the end of the first resistive element 18 facing away from the driving circuit layer 113, that is, the chamfered end 18a is the end of the first resistive element 18. A resistance element 18 faces away from one end of the display area 1 . In the direction in which the display area 1 points to the binding area 201, the length of the first substrate 111 located in the binding area 201 is longer than the length of the first resistance element 18, and the first resistance The length of the element 18 is longer than the length of the test track 4 .

In one embodiment of the present application, when the test trace 4 points to the direction of the first resistance element 18 , the slope of the chamfered end 18 a is inclined in the direction where the display area 1 is located. In other embodiments of the present application, when the first resistance element 18 points to the direction of the test wiring 4 , the slope of the chamfered end 18 a is inclined in the direction where the display area 1 is located. The present application does not specifically limit the inclination direction of the slope of the chamfered end 18a.

In an exemplary embodiment, the insulating element 6 is also filled to the slope of the chamfered end 18a, that is, the insulating element 6 is also provided on the slope of the chamfered end 18a. Further, the surface of the insulating element 6 facing away from the test wiring 4 is flush with the surface of the insulating element 6 facing away from the chamfered end 18a.

In an exemplary embodiment, the chamfered end 18a may also be formed by cutting.

It can be understood that, by forming the chamfered end 18a at the end of the first resistance element 18 facing away from the display area 1, the quality of the first resistance element 18 is reduced, and the first resistance element 18 can be further avoided. A resistive element 18 fails to support its own mass and breaks. At the same time, the contact between the first resistance element 18 and the conductive adhesive tape can be avoided by the chamfered end 18a. Moreover, under the effect of the slope of the chamfered end 18a, the insulating material can flow into the first groove a more easily, so that the insulating element 6 formed by the insulating material can fill up the entire first groove a. The groove a is beneficial to improve the insulating and supporting functions of the insulating element 6 .

Based on the same inventive concept, please refer to FIG. 8 , which is a schematic diagram of a fourth layer structure of the display panel disclosed in the third embodiment of the present application. The difference between the display panel 10c of the fourth layer structure and the display panel 10a of the second layer structure is that: the binding area 201 of the display panel 10c of the fourth layer structure also includes a first flat area and a first recessed area . For the description of the similarities between the display panel 10c of the fourth layer structure and the display panel 10a of the second layer structure, please refer to the relevant description of the display panel 10a of the second layer structure, and details will not be repeated here.

Specifically, please refer to FIG. 9 together. FIG. 9 is a schematic diagram of a plane structure corresponding to the display panel shown in FIG. 8 . In the embodiment of the present application, the binding area 201 of the display panel 10c of the fourth layer structure further includes a first flat area 201a and a plurality of first recessed areas 201b, wherein the plurality of first recessed areas 201b Set at intervals, part of the peripheral side of each first recessed area 201b is wrapped by the first flat area 201a, and the side of the first recessed area 201b facing away from the display area 1 exposes the first flat area. District 201a.

In an exemplary embodiment, the planar shape of the first depressed area 201b may be rectangular, and the three sides of the first depressed area 201b are surrounded by the first flat area 201a, and the first depressed area 201b One side exposes the first flat area 201a. The number of the first recessed regions 201b is determined by the number of the test wires 4, which is not specifically limited in the present application.

In the implementation manner of the present application, please refer to FIG. 10 , which is an enlarged schematic diagram of structure X in the display panel shown in FIG. 8 . A part of the first substrate 111 located in the bonding area 201 is located in the first planar area 201a, and another part is located in the first recessed area 201b. A part of the test wire 4 is located in the first flat area 201a, and another part is located in the first recessed area 201b. A part of the first resistance element 18 is located in the first flat area 201a, and another part is located in the first recessed area 201b.

In the embodiment of the present application, please refer to FIG. 10 , the first groove a is located in the first recessed area 201b, and the highest point of the side wall of the first groove a is less than or equal to that located in the first recessed area. The height of the surface of the first substrate 111 facing the test trace 4 in a flat area 201 a. That is, the entire first groove a is below the surface of the first substrate 111 located in the first flat region 201a facing the test wiring 4, that is, the first groove a is formed in the inside the first substrate 111. Wherein, the height refers to: the reference plane (the surface of the first substrate 111 facing away from the test wiring 4 is the reference plane) to the side of the first substrate 111 facing the first resistance element 18 distance.

It can be understood that please refer to FIG. 11 , which is a three-dimensional structural diagram corresponding to the binding area of the display panel shown in FIG. 8 . By forming the first groove a in the first substrate 111, when an external force acts on the vicinity of the first groove a, the first substrate 111 located in the first flat region 201a The surface facing the test trace 4 can also serve as a support, further avoiding the risk of cracking of the first resistance element 18 located in the first recessed area 201b due to lack of support. Moreover, by forming the first groove a in the first substrate 111, it is not necessary to form the first resistance element 18 on the side of the first groove a, and the The conductive solution 41 is injected into a groove a, which simplifies the manufacturing process of the display motherboard.

In an exemplary embodiment, the surface of the first resistive element 18 located in the first recessed area 201b facing away from the first groove a and the first substrate located in the first flat area 201a 111 is aligned with the surface of the test trace 4 .

In an exemplary embodiment, the surface of the first substrate 111 located in the first planar area 201a facing the test trace 4 is higher than the first substrate located in the first recessed area 201b. The height of the surface of the substrate 111 facing the test wiring 4, that is, the thickness of the first substrate 111 located in the first flat area 201a is greater than that of the first substrate located in the first recessed area 201b. The thickness of the bottom 111 makes the height of the test wires 4 located in the first flat area 201a higher than the height of the test wires 4 located in the first recessed area 201b, and makes the height of the test wires 4 located in the first recessed area 201b The height of the first resistance element 18 in the flat area 201a is higher than the height of the first resistance element 18 in the first recessed area 201b, and the first groove a is formed in the first substrate 111 inside.

In an exemplary embodiment, please refer to FIG. 9, the width W of the first groove a may be 200um to 1500um, for example, 200um, 300um, 500um, 800um, 1000um, 1300um, 1500um, or other values, This application does not specifically limit this. Wherein, the width of the first groove a refers to: between the side of the first groove a facing the other first groove a and the side facing away from the other first groove a distance.

In an exemplary embodiment, the surface of the first substrate 111 located in the first planar area 201a facing the test line 4 and the surface of the first substrate 111 located in the first recessed area 201b The distance between the surface facing the test trace 4 can be 1 to 100um, that is, the first substrate 111 located in the first flat area 201a and the first substrate 111 located in the first recessed area 201b The height difference between a substrate 111 can be 1 to 100um, for example, 1um, 20um, 50um, 70um, 80um, 100um, or other values, which is not specifically limited in the present application.

In an exemplary embodiment, the first resistance element 18 of the display panel 10c of the fourth layer structure may also include a chamfered end 18a, and the slope of the chamfered end 18a may also fill the insulating element 6, the present application There is no specific limitation on this.

It can be understood that, the side walls of the first groove a of the display panel 10 of the first layer structure may include four side walls, wherein one side wall is formed by the first substrate 111, and the other three are formed by the first substrate 111. The side walls are formed by said first resistive element 18 . The side wall of the first groove a of the display panel 10c of the fourth layer structure may include four side walls, wherein, three side walls are formed by the first substrate 111, and the other side wall is formed by the first substrate 111. A resistive element 18 is formed.

In summary, the display panel 10a provided in the embodiment of the present application is not cut, and the conductive solution 41 is filled in the first groove a; after the display panel 10 is cut, the conductive solution 41 in the first groove a The conductive solution 41 flows out. Therefore, the test wiring 4 is retracted on the side of the binding area 201 facing away from the display area 1, and the conductive adhesive tape will not expose the first groove with a plurality of the testing wiring 4 The surfaces of a are in contact with each other, so that the test wire 4 will not be short-circuited, which avoids display failure of the display panel 10 and improves the reliability of the display panel 10 . Moreover, the display panel 10 is not cut, and the test wiring 4 is electrically connected to the test component 20 through the conductive solution 41, and the test component 20 can provide the test circuit to the display panel 10. signal to test the display panel 10 .

Based on the same inventive concept, please refer to FIG. 12 , which is a schematic diagram of the second partial layer structure of the display motherboard shown in FIG. 1 . The difference between the display motherboard 100b of the second layer structure and the display motherboard 100a of the first layer structure shown in FIG. , the second flat area and the second recessed area. For the description of the similarities between the display motherboard 100b of the second layer structure and the display motherboard 100a of the first layer structure, please refer to the related description of the display motherboard 100a of the first layer structure. For the related description of 201a and the first recessed region 201b, please refer to the related description of the display panel 10c with the fourth layer structure, and details will not be repeated here.

Specifically, please refer to FIG. 13 . FIG. 13 is a schematic plan view of the display motherboard shown in FIG. 12 . In the embodiment of the present application, the test assembly 20 further includes a second flat area 20a and a plurality of second recessed areas 20b, the plurality of second recessed areas 20b are arranged at intervals, and each of the second recessed areas 20b Part of the peripheral side is wrapped by the second flat area 20a. One side of the second recessed region 20b is connected to the exposed side of the first recessed region 201b, that is, the side of the second recessed region 20b connected to the first recessed region 201b is not covered by the first recessed region 201b. Two flat areas 20a wrap.

In an exemplary embodiment, the planar shape of the second recessed area 20b may be rectangular, and the three sides of the second recessed area 20b are wrapped by the second flat area 20a, and the second recessed area 20b One side exposes the second planar region 20a, and is connected to the side of the first recessed region 201b exposing the first planar region 201a. The number of the second recessed regions 20 b is determined by the number of the conductive traces 24 , which is not specifically limited in the present application.

In the embodiment of the present application, please refer to FIG. 14 , which is an enlarged schematic view of structure XIII in the display motherboard shown in FIG. 12 . A part of the second substrate 23 is located in the second flat region 20a, and another part is located in the second recessed region 20b. A part of the conductive trace 24 is located in the second flat area 20a, and another part is located in the second recessed area 20b. A part of the second resistance element 26 is located in the second flat region 20a, and another part is located in the second recessed region 20b.

In the embodiment of the present application, please refer to FIG. 12 , the second groove b is located in the second recessed area 20b, and the highest point of the side wall of the second groove b is less than or equal to that located in the second concave region 20b. The height of the surface of the second substrate 23 facing the conductive wiring 24 in the second planar area 20a. That is, the entire second groove b is below the surface of the second substrate 23 located in the second flat region 20a facing the conductive wiring 24, that is, the second groove b is formed in the inside the second substrate 23. Wherein, the height refers to: the reference plane (the surface of the second substrate 23 facing away from the conductive trace 24 is the reference plane) to the side of the second substrate 23 facing the second resistance element 26 distance.

It can be understood that, by forming the second groove b in the second substrate 23, there is no need to form the second resistance element 26 on the side of the second groove b, and the The conductive solution 41 is injected into the second groove b, which simplifies the manufacturing process of the display motherboard.

In an exemplary embodiment, the surface of the second resistive element 26 located in the second recessed area 20b facing away from the second groove b and the second substrate located in the second flat area 20a 23 is aligned with the surface facing the conductive trace 24 .

In an exemplary embodiment, the height of the surface of the second substrate 23 located in the second planar region 20a facing the conductive traces 24 is higher than that of the second substrate located in the second recessed region 20b. The height of the surface of the substrate 23 facing the conductive wiring 24, that is, the thickness of the second substrate 23 located in the second flat area 20a is greater than that of the second substrate located in the second recessed area 20b. The thickness of the bottom 23 makes the height of the conductive traces 24 located in the second flat area 20a higher than the height of the conductive traces 24 located in the second recessed area 20b, and makes the conductive traces 24 located in the second recessed area The height of the second resistance element 26 in the flat area 20a is higher than the height of the second resistance element 26 in the second recessed area 20b, and the second groove b is formed in the second substrate Within 23.

It can be understood that, the side walls of the second groove b of the display motherboard 100a of the first layer structure may include four side walls, wherein one side wall is formed by the second substrate 23, and the other three are formed by the second substrate 23. A side wall is formed by the second resistance element 26. The side walls of the second groove b of the display motherboard 100b of the second layer structure may include four side walls, wherein three side walls are formed by the second substrate 23, and the other side wall is formed by the first side wall. Two resistive elements 26 are formed.

Please refer to FIG. 15 . FIG. 15 is a schematic diagram of the layered structure of the display device disclosed in the third embodiment of the present application. In the embodiment of the present application, the display device 200 may include a stacked display panel and a backlight module, the display panel is arranged on the light output side of the backlight module, and the display panel is used to The image is displayed under the backlight provided by the set.

In the implementation manner of the present application, the backlight module may be an edge-type backlight module or a direct-type backlight module, which is not specifically limited in the present application.

It can be understood that the display device can be used in electronic devices including but not limited to tablet computers, notebook computers, desktop computers, mobile phones, and vehicle displays. According to the embodiment of the present invention, the specific type of the display device is not particularly limited, and those skilled in the art can design correspondingly according to the specific use requirements of the display device, and details are not repeated here.

In an exemplary embodiment, the display device may also include other necessary components and components such as a driver board, a power supply board, a high voltage board, and a key control board. The functions are supplemented correspondingly, and will not be repeated here.

In summary, the display device provided by the embodiment of the present application includes a display panel and a backlight module, the display panel 10a is not cut, the first groove a is filled with a conductive solution 41; the display panel 10 is After cutting, the conductive solution 41 in the first groove a flows out. Therefore, the test wiring 4 is retracted on the side of the binding area 201 facing away from the display area 1, and the conductive adhesive tape will not expose the first groove with a plurality of the testing wiring 4 The surfaces of a are in contact with each other, so that the test wire 4 will not be short-circuited, which avoids display failure of the display panel 10 and improves the reliability of the display panel 10 . Moreover, the display panel 10 is not cut, and the test wiring 4 is electrically connected to the test component 20 through the conductive solution 41, and the test component 20 can provide the test circuit to the display panel 10. signal to test the display panel 10 .

Based on the same inventive concept, the third embodiment of the present application also provides a method for manufacturing a display motherboard, which is used for manufacturing the display motherboard shown in FIG. 4 and FIG. 12 . For the content related to the display motherboard manufacturing method provided by the third embodiment of the present application, please refer to the relevant description of the display motherboard in the above embodiments, and details are not repeated here. Please refer to FIG. 16 . FIG. 16 is a schematic flowchart of a method for manufacturing a display motherboard disclosed in the third embodiment of the present application. The method for manufacturing a display motherboard may include the following steps.

S10 , providing an array substrate assembly, where the array substrate assembly includes a first substrate 111 and a second substrate 23 .

S20 , forming a conductive layer on the first substrate 111 and the second substrate 23 .

S30. Form the conductive layer into a plurality of test traces 4 and a plurality of conductive traces 24, and form an accommodating space between the test traces 4 and the conductive traces 24, wherein the accommodating The space includes a first groove a and a second groove b, the test wiring 4 and the first groove a are located on the first substrate 111, the conductive wiring 24 and the second groove Groove b is located on the second substrate 23 .

S40, filling the accommodating space with a conductive solution 41.

S50, forming at least some resistance components on the side of the test wiring 4 facing away from the first substrate 111 and the side of the conductive wiring 24 facing away from the second substrate 23, so that the resistance The assembly covers the conductive solution 41, wherein the resistance assembly includes a first resistance element 18 and a second resistance element 26, the first resistance element 18 is located on the test wiring 4, and the second resistance element 26 located on the conductive trace 24 .

It can be understood that in step S10, the provided array substrate assembly has a color filter substrate assembly on it, that is, the array substrate assembly and the color filter substrate assembly have been boxed; or, after step S50, the array substrate assembly and the color filter substrate Components to boxes, the present application does not specifically limit this. Wherein, the color filter substrate assembly includes a plurality of color filter substrates, and the box alignment refers to aligning the array substrate assembly with the color filter substrate assembly, and connecting the array substrate assembly and the color filter assembly through a sealant. The process by which substrate components are bonded together. In step S10 , the test element 21 has been formed on the provided array substrate assembly; or, in step S30 , the test element 21 can be formed from the conductive layer 60 through a photolithography process, which is not specifically limited in the present application.

In a specific implementation manner of the present application, the method for manufacturing a display motherboard is used to form the display motherboard 100 a shown in FIG. 4 , and the method for manufacturing a display motherboard may include the following steps.

S10a, providing an array substrate assembly, where the array substrate assembly includes a first substrate 111 and a second substrate 23 .

Specifically, an array substrate assembly is provided, the array substrate assembly includes a plurality of array substrates, and the array substrate includes a first substrate 111 , a driving circuit layer 113 , and an insulating layer 115 that are sequentially stacked. The array substrate assembly further includes a second substrate 23, the first substrate 111 is arranged on the same layer as the second substrate 23 and is connected, and part of the first substrate 111 is exposed and at least part of the second substrate 111 is exposed. The substrate 23 is exposed.

In an exemplary embodiment, the first substrate 111 is integrally formed with the second substrate 23 .

S20a, forming a conductive layer 60 on the first substrate 111 and the second substrate 23 .

Specifically, please refer to FIG. 17 . FIG. 17 is a schematic structural diagram corresponding to step S20 a of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application. The conductive layer 60 is formed on the side of the first substrate 111 where the first driving circuit layer 113 is formed, and the conductive layer 60 also covers the second substrate 23 .

In an exemplary embodiment, the material of the conductive layer 60 may include but not limited to: any one or more of metal materials such as platinum, gold, aluminum, copper, titanium, silver, chromium, nickel, etc. This is not specifically limited.

S30a. Form the conductive layer into a plurality of test traces 4 and a plurality of conductive traces 24, and form an accommodating space between the test traces 4 and the conductive traces 24, wherein the accommodating The space includes a first groove a and a second groove b, the test wiring 4 and the first groove a are located on the first substrate 111, the conductive wiring 24 and the second groove Groove b is located on the second substrate 23 .

In the implementation manner of the present application, please refer to FIG. 18 . FIG. 18 is a schematic flowchart of step S30a of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application. The step S30a may specifically include the following steps.

S31a, forming the conductive layer 60 into a plurality of test traces 4 and a plurality of conductive traces 24 .

Specifically, please refer to FIG. 19 . FIG. 19 is a schematic structural diagram corresponding to step S31 a of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application. The conductive layer 60 is formed into a plurality of the test traces 4 and a plurality of the conductive traces 24 through a photolithography process. Wherein, the photolithography process includes processes such as exposure and development.

In an exemplary embodiment, the plurality of test traces 4 located on the first substrate 111 are arranged at intervals, and the plurality of conductive traces 24 located on the second substrate 23 are arranged at intervals . One test wire 4 is opposite to one conductive wire 24 , and a plurality of test wires 4 and a plurality of conductive wires 24 can be distributed axially symmetrically along the cutting line Q.

S32a, forming part of the resistor assembly 70 on the side of the first substrate 111 on which the test wiring 4 is formed and on the side of the second substrate 23 on which the conductive wiring 24 is formed, the The test wire 4 , the conductive wire 24 and the resistor assembly 70 surround each other to form the accommodating space 80 .

Specifically, please refer to FIG. 20 , which is a schematic structural diagram corresponding to step S32 a of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application. Part of the resistance assembly 70 is formed on the side of the first substrate 111 where the test wiring 4 is formed and the side of the second substrate 23 where the conductive wiring 24 is formed. 70 includes a plurality of first resistance elements 18 and a plurality of second resistance elements 26, the test trace 4, the conductive trace 24, part of the first resistance element 18 and part of the second resistance element 26 are in phase to form the accommodating space 80 .

In an exemplary embodiment, two parts of the first resistance element 18 and the test wiring 4 form the first groove a, and two parts of the second resistance element 26 and the conductive The wires 24 surround the second groove b.

In an exemplary embodiment, there may be multiple accommodating spaces 80 .

S40a, filling the accommodating space 80 with the conductive solution 41 .

Specifically, please refer to FIG. 21 . FIG. 21 is a schematic structural diagram corresponding to step S40 a of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application. The accommodating space 80 is filled with a conductive solution 41, and the conductive solution 41 is respectively connected to the test wiring 4 and the conductive wiring 24, so as to connect the test wiring 4 and the conductive wiring 24. electrical connection.

S50a, forming part of the resistor assembly 70 on a side of the conductive solution 41 facing away from the first substrate 111 and facing away from the second substrate 23 .

Specifically, please refer to FIG. 4 , the resistance assembly 70 includes a plurality of first resistance elements 18 and a plurality of second resistance elements 26 , forming a part on the side of the conductive solution 41 facing away from the first substrate 111 The first resistance element 18 forms part of the second resistance element 26 on the side of the conductive solution 41 facing away from the second substrate 23 .

It can be understood that the partial resistance assembly 70 formed in step S30a and the partial resistance assembly 70 formed in step 50a constitute the complete resistance assembly 70 . Correspondingly, the part of the first resistance element 18 formed in step S30a and the part of the first resistance element 18 formed in step 50a constitute the complete first resistance element 18, and the part of the second resistance formed in step S30a The element 26 and the part of the second resistance element 26 formed in step 50 a form a complete second resistance element 26 .

In another specific implementation manner of the present application, the method for manufacturing a display motherboard is used to form the display motherboard 100b shown in FIG. 12 , and the method for manufacturing a display motherboard may include the following steps.

S10b, providing an array substrate assembly, where the array substrate assembly includes a first substrate 111 and a second substrate 23 . Wherein, part of the first substrate 111 is located in the first flat area 201a, a part of the first substrate 111 is located in the first recessed area 201b, and the first substrate located in the first flat area 201a The thickness of the bottom 111 is greater than the thickness of the first substrate 111 located in the first recessed region 201b. Part of the second substrate 23 is located in the second flat area 20a, another part of the second substrate 23 is located in the second recessed area 20b, and the second substrate located in the second flat area 20a 23 is thicker than the thickness of the second substrate 23 located in the second recessed region 20b.

S20b, forming a conductive layer 60 on the first substrate 111 and the second substrate 23 .

Specifically, FIG. 22 is a schematic structural diagram corresponding to step S20b of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application. A conductive layer 60 is formed on the first substrate 111 and the second substrate 23, wherein a part of the conductive layer 60 is located in the first flat area 201a and the second flat area 20a, and another A part is located in the first recessed area 201b and the second recessed area 20b, and the height of the conductive layer 60 located in the first recessed area 201b and the second recessed area 20b is lower than that located in the first recessed area 201b and the second recessed area 20b. The height of the flat area 201a and the second flat area 20a.

S30b. Form the conductive layer 60 into a plurality of test lines 4 and a plurality of conductive lines 24, and connect the first substrate 111, the second substrate 23, the test lines 4 and the An accommodating space 80 is formed between the conductive wires 24, wherein the accommodating space 80 includes a first groove a and a second groove b, and the test wire 4 and the first groove a are located in the On the first substrate 111 , the conductive wiring 24 and the second groove b are located on the second substrate 23 .

Specifically, FIG. 23 is a schematic structural diagram corresponding to step S30b of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application. The conductive layer 60 is formed into a plurality of the test traces 4 and a plurality of the conductive traces 24 through a photolithography process, and the first substrate 111 and the test traces 4 form the first recess Groove a, the second substrate 23 and the conductive traces 24 enclose the second groove b.

In an exemplary embodiment, part of the test wiring 4 is located in the first flat area 201a, another part of the test wiring 4 is located in the first recessed area 201b, and is located in the first flat area 201a. The height of the test wire 4 is higher than the height of the test wire 4 located in the first recessed area 201b. Part of the conductive wiring 24 is located in the second flat area 20a, another part of the conductive wiring 24 is located in the second recessed area 20b, and the conductive wiring 24 is located in the second flat area 20a The height is higher than the height of the conductive wires 24 located in the second recessed area 20b.

In an exemplary embodiment, the first groove a is located in the first recessed area 201b, and the second groove b is located in the second recessed area 20b.

S40b, filling the accommodating space 80 with the conductive solution 41 .

Specifically, FIG. 24 is a schematic structural diagram corresponding to step S40b of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application. The accommodating space 80 is filled with a conductive solution 41, and the conductive solution 41 is respectively connected to the test wiring 4 and the conductive wiring 24, so as to connect the test wiring 4 and the conductive wiring 24. electrical connection.

In an exemplary embodiment, the conductive solution 41 is located in the first recessed area 201b and the second recessed area 20b.

S50b, forming all the resistor components 70 on the side of the conductive solution 41 facing away from the first substrate 111 and the second substrate.

Specifically, FIG. 25 is a schematic structural diagram corresponding to step S50b of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application. The resistor assembly 70 includes a plurality of first resistor elements 18 and a plurality of second resistor elements 26, on the side of the conductive solution 41 facing away from the first substrate 111 and the test wiring 4 facing away from all The first resistance element 18 is formed on one side of the first substrate 111, and on the side of the conductive solution 41 facing away from the second substrate 23 and the conductive wiring 24 is facing away from the second substrate. One side of the bottom 23 forms the second resistance element 26 .

In an exemplary embodiment, part of the first resistive element 18 is located in the first flat region 201a, another part of the first resistive element 18 is located in the first recessed region 201b, and is located in the first flat region 201a. The height of the first resistance element 18 is higher than the height of the first resistance element 18 located in the first recessed region 201b. Part of the second resistance element 26 is located in the second flat area 20a, another part of the second resistance element 26 is located in the second recessed area 20b, and the second resistor located in the second flat area 20a The height of the element 26 is higher than that of the second resistor element 26 located in the second recessed region 20b.

In an exemplary embodiment, the first resistive element 18 is integrally formed with the second resistive element 26 .

To sum up, the manufacturing method of the display motherboard provided by the embodiment of the present application includes: providing an array substrate assembly, the array substrate assembly including the first substrate 111 and the second substrate 23; forming the conductive layer into multiple A test wire 4 and a plurality of conductive wires 24, an accommodating space is formed between the test wire 4 and the conductive wire 24; a conductive solution 41 is filled in the accommodating space; The side of the line 4 facing away from the first substrate 111 and the side of the conductive wiring 24 facing away from the second substrate 23 form a part of a resistance component or a resistance component, and the resistance component covers the conductive solution 41. Therefore, by filling the accommodating space with the conductive solution 41, when the display motherboard is cut, the conductive solution 41 in the accommodating space flows out, and the test wiring 4 shrinks in the first The substrate 111, the conductive adhesive tape will not be connected to a plurality of the test wires 4, and the test wires 4 will not be short-circuited, which avoids poor display of the display panel and improves the performance of the display panel. reliability. Moreover, when the display motherboard is not cut, the test wire 4 is electrically connected to the conductive wire 24 through the conductive solution 41, and then the test wire can receive a test electrical signal to test the display panel.

In the description of this specification, reference to the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific examples" or "some examples" etc. The specific features, structures, materials or features described in the manner or example are included in at least one embodiment or example of the present application. In this specification, exemplary expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

It should be understood that the application of the present application is not limited to the above examples, and those skilled in the art can make improvements or changes based on the above descriptions, and all these improvements and changes should belong to the protection scope of the appended claims of the present application. Those skilled in the art can understand that all or part of the processes of the above embodiments are realized, and equivalent changes made according to the claims of the present application still fall within the scope of the present application.

Claims (10)

1. The display panel comprises a display area and a binding area arranged on one side of the display area, and is characterized by comprising an array substrate, wherein the array substrate comprises a first substrate, and a part of the first substrate is positioned in the binding area;

The display panel further comprises a plurality of test wires and a plurality of first resistor elements, wherein the test wires are arranged on one side of the first substrate, are positioned in the binding area and are electrically connected with the array substrate, the first resistor elements cover the test wires on the first substrate, a first groove is formed by surrounding the first resistor elements, the test wires and the first substrate, and an opening of the first groove faces to one side of the binding area opposite to the display area; wherein,,

the first groove is used for filling conductive solution, and after the display panel is formed, the conductive solution in the first groove flows out.

2. The display panel of claim 1, further comprising a plurality of insulating elements filled in the first grooves to insulate a surface of the test traces facing away from the display area and to support the first resistive elements.

3. The display panel of claim 1, wherein the first resistive element further comprises a chamfered end, the chamfered end being an end of the first resistive element opposite the display area; wherein,,

The bevel of the chamfer end is inclined towards the direction of the display area when the test wire points to the direction of the first resistance element; or,

and the bevel of the chamfer end is inclined towards the direction of the display area when the first resistance element points to the direction of the test wiring.

4. The display panel of claim 1, wherein the bonding region further comprises a first flat region and a plurality of first recessed regions, wherein the plurality of first recessed regions are arranged at intervals, a part of the peripheral side of each of the first recessed regions is wrapped by the first flat region, and a side of the first recessed region opposite to the display region exposes the first flat region;

the first groove is positioned in the first concave region, and the highest point of the side wall of the first groove is smaller than or equal to the height of the surface of the first substrate positioned in the first flat region facing the test wire.

5. A display device comprising a backlight module and the display panel according to any one of claims 1-4, wherein the display panel is disposed on a light emitting side of the backlight module.

6. A display motherboard, characterized by comprising a test assembly and a plurality of display panels according to any one of claims 1-4, wherein the test assembly comprises a second substrate, a plurality of conductive traces and a plurality of second resistance elements, wherein the second substrate is connected with the first substrate and arranged in the same layer, the conductive traces are arranged in the same layer and at intervals with the test traces, and the second resistance elements cover the conductive traces partially on the second substrate and are connected with the first resistance elements and arranged in the same layer; the second substrate, the conductive trace and the second resistor element are enclosed to form a second groove, and an opening of the second groove faces to an opening of the first groove and is communicated with the first groove; wherein,,

The first groove and the second groove are filled with conductive solution, and the conductive solution is respectively in contact with the test wire and the conductive wire so as to electrically connect the test wire and the conductive wire.

7. The display motherboard of claim 6, wherein said binding region further comprises a first flat region and a plurality of first recessed regions, wherein a plurality of said first recessed regions are disposed at intervals, a portion of the peripheral side of each of said first recessed regions is surrounded by said first flat region, and a side of said first recessed region facing away from said display region exposes said first flat region;

the first groove is positioned in the first concave region, and the highest point of the side wall of the first groove is smaller than or equal to the height of the surface of the first substrate positioned in the first flat region facing the test wire.

8. The display motherboard of claim 7, wherein said test assembly further comprises a second flat region and a plurality of second recessed regions, a plurality of said second recessed regions being disposed at intervals, a portion of a peripheral side of each of said second recessed regions being surrounded by said second flat region, one side of said second recessed region being connected to an exposed side of said first recessed region;

The second groove is positioned in the second concave region, and the highest point of the side wall of the second groove is smaller than or equal to the height of the surface of the second substrate positioned in the second flat region facing the conductive wire.

9. The display mother panel according to any one of claims 6 to 8, wherein the conductive solution includes a conductive material having a mass ratio of 90% to 98% and an auxiliary material having a mass ratio of 2% to 10%, the conductive material being for conduction, the auxiliary material being for increasing fluidity of the conductive solution.

10. A method for manufacturing a display mother board according to any one of claims 6 to 9, the method comprising:

providing an array substrate assembly, wherein the array substrate assembly comprises a first substrate and a second substrate;

forming a conductive layer on the first substrate and the second substrate;

forming a plurality of test wires and a plurality of conductive wires on the conductive layer, and forming a containing space between the test wires and the conductive wires, wherein the containing space comprises a first groove and a second groove, the test wires and the first groove are positioned on the first substrate, and the conductive wires and the second groove are positioned on the second substrate;

Filling a conductive solution in the accommodating space;

at least part of a resistor assembly is formed on one side of the test wire, which is opposite to the first substrate, and one side of the conductive wire, which is opposite to the second substrate, so that the resistor assembly covers the conductive solution, wherein the resistor assembly comprises a first resistor element and a second resistor element, the first resistor element is positioned on the test wire, and the second resistor element is positioned on the conductive wire.

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