CN116248087A - Method and circuit for avoiding burr generation - Google Patents
Method and circuit for avoiding burr generation Download PDFInfo
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- CN116248087A CN116248087A CN202310504848.7A CN202310504848A CN116248087A CN 116248087 A CN116248087 A CN 116248087A CN 202310504848 A CN202310504848 A CN 202310504848A CN 116248087 A CN116248087 A CN 116248087A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/013—Modifications of generator to prevent operation by noise or interference
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The present application relates to the field of clock signal generation, and more particularly to a method and circuit for avoiding glitch generation. The clock output circuit is applied to the clock output circuit and comprises the steps of generating a conduction control signal by utilizing the cooperation of a first enabling signal and a clock signal; generating a clock output signal without burrs in a specified period associated with the conduction control signal by utilizing the coordination of the clock signal, the first enabling signal and the conduction control signal; the clock output signal is consistent with the frequency of the clock signal. The clock chip has the effect of avoiding burrs of the first clock signal output by the clock chip and the last clock signal which is turned off.
Description
Technical Field
The present application relates to the field of clock signal generation, and more particularly, to a method and circuit for avoiding glitch generation.
Background
Currently, in a clock chip, the period of the first clock signal and the last clock signal that are turned off and output by the clock chip must be complete, no glitch (jitter) can occur, otherwise, erroneous judgment can occur at the receiving end. That is, when the enable signal EN is not synchronized with the clock signal, a glitch (glitch) is caused in the output clock signal.
Disclosure of Invention
In order to avoid burrs of output signals of a clock chip, the application provides a method for avoiding burrs and a circuit for avoiding burrs.
The method for avoiding burr generation adopts the following technical scheme:
in a first aspect, a method for avoiding glitch generation is provided, applied to a clock output circuit, including:
generating a conduction control signal by utilizing the coordination of the first enabling signal and the clock signal;
generating a clock output signal without burrs in a specified period associated with the conduction control signal by utilizing the coordination of the clock signal, the first enabling signal and the conduction control signal; the clock output signal is consistent with the frequency of the clock signal.
Preferably, the generating the on control signal by using the first enable signal and the clock signal includes:
obtaining a second enabling signal by using the first enabling signal and the delay signal of the first enabling signal as the input of the exclusive-or gate;
the second enable signal and the clock signal are used as the input of the first AND gate to obtain the conduction control signal.
Preferably, the obtaining the second enable signal using the first enable signal and the delay signal of the first enable signal as the input of the exclusive or gate includes:
the delay time length of the delay signal of the first enabling signal relative to the first enabling signal is longer than half period of the clock signal.
Preferably, the generating, by using the clock signal, the first enable signal, and the on control signal in combination, a clock output signal free of glitches in a specified period associated with the on control signal includes:
generating a third enabling signal by utilizing the coordination of the conduction control signal and the first enabling signal;
using the third enabling signal and the clock signal as the input of the second AND gate to obtain the clock output signal without burrs when the third enabling signal is conducted; the first enable signal causes the third enable signal to become high level in the specified period after becoming high level, and the first enable signal causes the third enable signal to become low level in the specified period after becoming low level.
Preferably, the specified period is three clock cycles of the clock signal; said obtaining said clock output signal free of burrs when the third enable signal is on comprises:
using the first enabling signal as a first trigger signal of a first D trigger, and using the conduction control signal as a clock control input of the first D trigger;
using the output of the first D trigger as a second trigger signal of a second D trigger, and using a conduction control signal as a clock control input of the second D trigger;
using the output of the second D trigger as a third trigger signal of a third D trigger, and using the inverted output signal of the on control signal as a clock control input of the third D trigger;
and using the output of the third D trigger and the clock signal as the input of the second AND gate to obtain a clock output signal without burrs.
In a second aspect, a circuit for avoiding glitch generation is provided for use in a clock output, comprising:
the conduction control module is used for generating a conduction control signal by utilizing the coordination of the first enabling signal and the clock signal;
the clock output module is used for generating a clock output signal without burrs in a specified period related to the conduction control signal by utilizing the cooperation of the clock signal, the first enabling signal and the conduction control signal; the clock output signal is consistent with the frequency of the clock signal.
Preferably, the conduction control module includes:
a delay circuit for delaying the first enable signal to output;
an exclusive-or gate for delaying output of the first enable signal and taking the first enable signal as input to obtain a second enable signal;
and the first AND gate is used for taking the second enabling signal and the clock signal as inputs to obtain a conduction control signal.
Preferably, the delay circuit makes the delay time of the delay signal of the first enabling signal relative to the delay time of the first enabling signal be longer than half period of the clock signal.
Preferably, the clock output module includes:
the appointed delay module is used for generating a third enabling signal by utilizing the coordination of the conduction control signal and the first enabling signal;
the output module is used for utilizing the third enabling signal and the clock signal as the input of the second AND gate to obtain the clock output signal without burrs when the third enabling signal is conducted; the first enable signal causes the third enable signal to become high level in the specified period after becoming high level, and the first enable signal causes the third enable signal to become low level in the specified period after becoming low level.
Preferably, the specified delay module includes:
the first D trigger is used for utilizing the first enabling signal as a first trigger signal of the first D trigger and utilizing the conduction control signal as a clock control input of the first D trigger;
the second D trigger is used for utilizing the output of the first D trigger as a second trigger signal of the second D trigger and utilizing a conduction control signal as a clock control input of the second D trigger;
a third D flip-flop for using the output of the second D flip-flop as a third trigger signal of the third D flip-flop and using an inverted output signal of the on control signal as a clock control input of the third D flip-flop;
and the inverter is used for inverting the conduction control signal and then taking the inverted conduction control signal as the clock control input of the third D trigger.
In summary, the present application includes at least one of the following beneficial technical effects:
1. the first clock signal and the last clock signal which are closed and output by the clock chip are prevented from generating burrs;
2. the problem that the consumed power increases along with the increase of the clock frequency under the condition that the output of the clock chip is free of burrs is avoided.
Drawings
FIG. 1 is an exemplary diagram of the occurrence of burrs in the prior art;
FIG. 2 is a method step diagram of a method of avoiding glitch generation;
FIG. 3 is a diagram of method steps for generating a turn-on control signal;
FIG. 4 is a diagram of method steps for generating a glitch-free clock output signal for a specified period associated with a turn-on control signal;
FIG. 5 is a diagram of method steps for obtaining the clock output signal without glitches when the third enable signal EN_Trig is on;
FIG. 6 is a logic block diagram of a circuit that avoids glitch generation;
fig. 7 is a configuration diagram of the conduction control module;
FIG. 8 is a diagram of a clock output module configuration;
FIG. 9 is a diagram of a specified delay module configuration;
FIG. 10 is a complete circuit diagram of a clock output circuit without burr generation;
fig. 11 is a timing diagram of a circuit that avoids glitch generation.
Reference numerals illustrate: 1. a circuit for avoiding burr generation; 11. a conduction control module; 12. a clock output module; 121. designating a delay module; 122. and an output module.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to fig. 1 to 11 and the embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
In the prior art, the clock signal CLK is required to be output when the enable signal EN is at a high level. However, as shown in fig. 1, when the enable signal EN is at a high level, the clock signal CLK is also at a high level, and the output CLKOUT is subjected to glitch; that is, a case occurs in which the high-level period is shorter than the high-level period of the clock signal CLK. The occurrence of burrs can cause the problems of misjudgment and the like in the subsequent places where the clock output signal CLKOUT is used. In view of this, the present invention proposes the following solution.
The method for avoiding burr generation adopts the following technical scheme:
in a first aspect, as shown in fig. 2, there is provided a method for avoiding generation of glitches, applied to a clock output circuit, including:
s1: generating a conduction control signal by using the first enable signal EN and the clock signal CLK in cooperation; if only the first enable signal EN is used for controlling the output CLKOUT of the clock signal, a glitch (glotch) situation may occur; accordingly, in the present invention, the conduction control signal for conduction is generated by the cooperation of the first enable signal EN and the clock signal CLK.
S2: generating a clock output signal without burrs in a specified period associated with the conduction control signal by utilizing the cooperation of the clock signal CLK, the first enable signal EN and the conduction control signal; the clock output signal CLKOUT is consistent with the frequency of the clock signal CLK. In this embodiment, the clock output signal CLKOUT without burrs needs to be generated, and the 3 signals need to be matched to generate the clock output signal CLKOUT; the generation of burrs is avoided.
Preferably, as shown in fig. 3, the generating the on control signal by using the first enable signal EN in cooperation with the clock signal CLK includes:
s11: obtaining a second enable signal Vdet_en by using the first enable signal EN and a delay signal of the first enable signal as inputs of an exclusive OR gate XOR;
s12: the on control signal is obtained using the second enable signal vdet_en AND the clock signal CLK as inputs to the first AND gate AND 1. The turn-on control signal is used for turn-on of the subsequent circuit so that the clock signal CLK can pass through the subsequent circuit, thereby realizing the glitch-free clock output signal CLKOUT.
Preferably, the obtaining the second enable signal vdet_en using the first enable signal EN and the delay signal of the first enable signal as inputs of the Xor gate Xor includes:
the delay time of the delay signal of the first enable signal EN with respect to the first enable signal EN is longer than a half period of the clock signal CLK. If the delay period is not long enough, i.e., less than half a period of the clock signal CLK, the output clock signal output CLKOUT still exhibits glitches. If the delay time is longer than half a period of the clock signal CLK, no glitch occurs in the subsequent clock output signal CLKOUT. In this embodiment, for safety reasons, a delay period of at least 3 clock cycles or more is used.
Preferably, as shown in fig. 4, the generating the clock output signal CLKOUT having no glitch in a specified period associated with the on control signal by using the clock signal CLK, the first enable signal EN and the on control signal in cooperation includes:
s21: generating a third enable signal EN_Trig by matching the conduction control signal with the first enable signal EN;
s22: obtaining said clock output signal CLKOUT free of glitches when the third enable signal en_trig is on, using the third enable signal en_trig AND the clock signal CLK as inputs to the second AND gate AND 2; the first enable signal EN makes the third enable signal en_trig high during the designated period after being high, and the first enable signal EN makes the third enable signal en_trig low during the designated period after being low.
Preferably, as shown in fig. 5, the specified period is three clock cycles of the clock signal CLK; the obtaining the clock output signal CLKOUT that is free of glitches when the third enable signal en_trig is on includes:
s221: using the first enabling signal as a first trigger signal of a first D trigger, and using the conduction control signal as a clock control input of the first D trigger;
s222: using the output of the first D trigger as a second trigger signal of a second D trigger, and using a conduction control signal as a clock control input of the second D trigger;
s223: using the output of the second D trigger as a third trigger signal of a third D trigger, and using the inverted output signal of the on control signal as a clock control input of the third D trigger;
s224: and using the output of the third D trigger and the clock signal as the input of the second AND gate to obtain a clock output signal without burrs. The first D flip-flop, the second D flip-flop, and the third D flip-flop are edge flip-flops, and may be level flip-flops. The clock signal can be either an edge signal or a level signal of the clock control input.
In a second aspect, as shown in fig. 6, there is provided a circuit 1 for avoiding generation of glitches, for use in a clock output, comprising:
the conduction control module 11 is configured to generate a conduction control signal by using the first enable signal EN in cooperation with the clock signal;
a clock output module 12, configured to generate a clock output signal without glitches in a specified period associated with the on control signal by using the clock signal CLK, the first enable signal EN, and the on control signal in cooperation; the clock output signal is consistent with the frequency of the clock signal.
Preferably, as shown in fig. 7, the conduction control module 11 includes:
a Delay circuit Delay for delaying and outputting the first enable signal EN;
an exclusive-or gate Xor for obtaining the second enable signal vdet_en by taking the first enable signal and the first enable signal EN as inputs;
the first AND gate AND1 is used for taking the second enable signal EN AND the clock signal CLK as inputs to obtain a conduction control signal.
Preferably, the Delay circuit Delay makes the Delay time of the first enable signal EN longer than half a period of the clock signal relative to the Delay time of the first enable signal EN.
Preferably, as shown in fig. 8, the clock output module 12 includes:
a specified delay module 121, configured to generate a third enable signal en_trig by using the on control signal and the first enable signal EN in cooperation;
an output block 122 for obtaining said clock output signal CLKOUT without glitches when the third enable signal en_trig is on, using the third enable signal en_trig AND the clock signal CLK as inputs to the second AND gate AND 2; the first enable signal EN makes the third enable signal en_trig high during the designated period after being high, and the first enable signal EN makes the third enable signal en_trig low during the designated period after being low.
Preferably, as shown in fig. 9, the specified delay module 121 includes:
the first D trigger D1 is used for taking the first enable signal EN as a first trigger signal of the first D trigger and taking the conduction control signal as a clock control input of the first D trigger;
a second D flip-flop D2 for using the output of the first D flip-flop as a second trigger signal of the second D flip-flop and using the on control signal as a clock control input of the second D flip-flop;
a third D flip-flop D3 for using the output of the second D flip-flop as a third trigger signal of the third D flip-flop and using an inverted output signal of the on control signal as a clock control input of the third D flip-flop;
and the inverter INV is used for inverting the conduction control signal and then taking the inverted conduction control signal as the clock control input of the third D trigger.
As shown in fig. 10, a complete circuit diagram of the clock output circuit of the present invention without the generation of burrs.
As shown in fig. 11, a timing diagram of the circuit for avoiding glitch generation of the present invention is shown. As is clear from fig. 10, the clock output signal CLKOUT obtained after the clock signal CLK and the first enable signal EN are input to the present circuit has no glitch generation. Also, it can be seen that the third enable signal en_trig changes from low level to high level after 3 clock cycles after the first enable signal EN changes from low level to high level; after the first enable signal EN changes from the high level to the low level, the third enable signal en_trig changes from the high level to the low level after 3 clock cycles. This is 3 clock cycles because the clock output module has 3D flip-flops. When the clock output module has 4D flip-flops, the third enable signal en_trig changes from low level to high level or from high level to low level by 4 clock cycles later than the first enable signal EN.
Due to the presence of the on-control module 11, too fast transitions of the clock output module 12 following the clock signal CLK are avoided. That is, the clock output signal CLKOUT is output only in the case where the third enable signal en_trig is at a high level. The presence of the on control module 11 reduces the power consumption of the circuit for a clock signal without a glitch output considerably. In practical applications, like a reset signal, a lock signal of a phase-locked loop, and a powerdown signal can be used as an enable signal to detect and be used for integrity control of an output clock signal, and especially in the clock chip with up to 20 paths of outputs, huge power consumption can be saved.
In summary, the present application includes at least one of the following beneficial technical effects:
1. the first clock signal and the last clock signal which are closed and output by the clock chip are prevented from generating burrs;
2. the problem that the consumed power increases along with the increase of the clock frequency under the condition that the output of the clock chip is free of burrs is avoided.
The foregoing description of the preferred embodiments of the present application is not intended to limit the scope of the application, in which any feature disclosed in this specification (including abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. That is, each feature is one example only of a generic series of equivalent or similar features, unless expressly stated otherwise.
Claims (10)
1. A method for avoiding glitch generation for a clock output circuit, comprising:
generating a conduction control signal by utilizing the coordination of the first enabling signal and the clock signal;
generating a clock output signal without burrs in a specified period associated with the conduction control signal by utilizing the coordination of the clock signal, the first enabling signal and the conduction control signal; the clock output signal is consistent with the frequency of the clock signal.
2. The method of claim 1, wherein generating the turn-on control signal using the first enable signal in conjunction with the clock signal comprises:
obtaining a second enabling signal by using the first enabling signal and the delay signal of the first enabling signal as the input of the exclusive-or gate;
the second enable signal and the clock signal are used as the input of the first AND gate to obtain the conduction control signal.
3. The method according to claim 2, wherein obtaining the second enable signal using the first enable signal and the delayed signal of the first enable signal as inputs to the exclusive or gate comprises:
the delay time length of the delay signal of the first enabling signal relative to the first enabling signal is longer than half period of the clock signal.
4. The method of claim 1, wherein generating the glitch-free clock output signal for the specified period associated with the on control signal using the clock signal, the first enable signal, and the on control signal in combination comprises:
generating a third enabling signal by utilizing the coordination of the conduction control signal and the first enabling signal;
using the third enabling signal and the clock signal as the input of the second AND gate to obtain the clock output signal without burrs when the third enabling signal is conducted; the first enable signal causes the third enable signal to become high level in the specified period after becoming high level, and the first enable signal causes the third enable signal to become low level in the specified period after becoming low level.
5. The method of claim 4, wherein the specified period is three clock cycles of the clock signal; said obtaining said clock output signal free of burrs when the third enable signal is on comprises:
using the first enabling signal as a first trigger signal of a first D trigger, and using the conduction control signal as a clock control input of the first D trigger;
using the output of the first D trigger as a second trigger signal of a second D trigger, and using a conduction control signal as a clock control input of the second D trigger;
using the output of the second D trigger as a third trigger signal of a third D trigger, and using the inverted output signal of the on control signal as a clock control input of the third D trigger;
and using the output of the third D trigger and the clock signal as the input of the second AND gate to obtain a clock output signal without burrs.
6. A circuit for avoiding glitch generation for use in a clock output, comprising:
the conduction control module is used for generating a conduction control signal by utilizing the coordination of the first enabling signal and the clock signal;
the clock output module is used for generating a clock output signal without burrs in a specified period related to the conduction control signal by utilizing the cooperation of the clock signal, the first enabling signal and the conduction control signal; the clock output signal is consistent with the frequency of the clock signal.
7. The circuit of claim 6, wherein the turn-on control module comprises:
a delay circuit for delaying the first enable signal to output;
an exclusive-or gate for delaying output of the first enable signal and taking the first enable signal as input to obtain a second enable signal;
and the first AND gate is used for taking the second enabling signal and the clock signal as inputs to obtain a conduction control signal.
8. The circuit of claim 7, wherein the delay circuit is configured such that a delay time of the delay signal of the first enable signal relative to the first enable signal is greater than half a period of the clock signal.
9. The circuit of claim 6, wherein the clock output module comprises:
the appointed delay module is used for generating a third enabling signal by utilizing the coordination of the conduction control signal and the first enabling signal;
the output module is used for utilizing the third enabling signal and the clock signal as the input of the second AND gate to obtain the clock output signal without burrs when the third enabling signal is conducted; the first enable signal causes the third enable signal to become high level in the specified period after becoming high level, and the first enable signal causes the third enable signal to become low level in the specified period after becoming low level.
10. The circuit of claim 9, wherein the specified delay module comprises:
the first D trigger is used for utilizing the first enabling signal as a first trigger signal of the first D trigger and utilizing the conduction control signal as a clock control input of the first D trigger;
the second D trigger is used for utilizing the output of the first D trigger as a second trigger signal of the second D trigger and utilizing a conduction control signal as a clock control input of the second D trigger;
a third D flip-flop for using the output of the second D flip-flop as a third trigger signal of the third D flip-flop and using an inverted output signal of the on control signal as a clock control input of the third D flip-flop;
and the inverter is used for inverting the conduction control signal and then taking the inverted conduction control signal as the clock control input of the third D trigger.
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| CN202310504848.7A CN116248087B (en) | 2023-05-08 | 2023-05-08 | Method and circuit for avoiding burr generation |
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| CN116248087B (en) | 2023-08-29 |
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