CN115133914A - Circuit for preventing output glitch in clock generating circuit - Google Patents
Circuit for preventing output glitch in clock generating circuit Download PDFInfo
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- CN115133914A CN115133914A CN202210768598.3A CN202210768598A CN115133914A CN 115133914 A CN115133914 A CN 115133914A CN 202210768598 A CN202210768598 A CN 202210768598A CN 115133914 A CN115133914 A CN 115133914A
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- 238000005070 sampling Methods 0.000 claims abstract description 30
- 230000002265 prevention Effects 0.000 claims abstract description 7
- 239000003990 capacitor Substances 0.000 claims description 10
- 238000004891 communication Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 101150110971 CIN7 gene Proteins 0.000 description 2
- 101150110298 INV1 gene Proteins 0.000 description 2
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 101100286980 Daucus carota INV2 gene Proteins 0.000 description 1
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a circuit for preventing output burrs in a clock generation circuit, and relates to the technical field of integrated circuits. The circuit comprises a burr prevention sub-circuit and a delay sub-circuit which are connected with a clock generation circuit, wherein a clock enabling signal is connected with the clock generation circuit through the delay sub-circuit, and the clock generation circuit outputs a sampling clock to the burr prevention sub-circuit; the anti-burr circuit comprises a D trigger, a NOR gate device and a first phase inverter; the clock enabling signal is connected to the D trigger through the first inverter and provides an enabling signal for the D trigger; the sampling clock is respectively connected to the input ends of a D trigger and a NOR gate device, the output end of the D trigger is connected to the other input end of the NOR gate device, and the output end of the NOR gate device outputs a clock signal. According to the technical scheme, the delay sub-circuit is added, and the burr is prevented in the last period of the clock signal through the burr preventing sub-circuit.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a circuit for preventing output burrs in a clock generation circuit.
Background
In recent decades, wireless communication technology and microelectronic technology have been developed vigorously, and research on CMOS communication systems is not actively carried out. The phase-locked loop is used as a key component of the front end of a wireless system, the starting speed of the communication system is directly determined by the locking speed and the clock quality of the phase-locked loop, and the requirements on the performance of the phase-locked loop are higher in the time division multiple access and spread spectrum frequency hopping communication system. At present, more and more electronic products have more increased requirements on chips, and under the conditions that the functions are more complicated and the integration level is higher, the small-area high-performance CMOS circuit design becomes inevitable, and the market prospect is huge.
With the application of chip systems becoming more and more complex, the requirements on clock generation circuits (oscillators, crystal drives, phase-locked loops, etc.) become higher and higher, so that not only is the clock performance required to be good during normal operation, but also other modules of the system are required not to be affected under the condition of turning off. In the normal working process of the clock, if the enable signal is suddenly turned off, the output of the clock generation circuit is pulled to be low; but since it is not known when the clock output will be pulled low, it may happen that the last clock pulse width is clipped part of the way to output glitches. As shown in fig. 1.
In the prior art, in order to solve the output glitch problem, the last output clock is generally swallowed by performing digital processing, but the digital logic is complex, the implementation difficulty is high, and the workload of research and development personnel is increased; there is also an influence of avoiding output glitch from the application level, but this cannot actually solve the output glitch problem.
Disclosure of Invention
The invention mainly aims to provide a circuit for preventing output glitch in a clock generation circuit, aiming at preventing the glitch in clock output.
In order to achieve the above object, the present invention provides a circuit for preventing output glitch in a clock generation circuit, including an anti-glitch sub-circuit connected to the clock generation circuit and a delay sub-circuit, a clock enable signal is connected to the clock generation circuit through the delay sub-circuit, and the clock generation circuit outputs a sampling clock to the anti-glitch sub-circuit; the anti-burr circuit comprises a D trigger, a NOR gate device and a first phase inverter; the clock enabling signal is connected to the D trigger through the first inverter and provides a control signal for the D trigger; the sampling clock is respectively connected to the input ends of a D trigger and a NOR gate device, the output end of the D trigger is connected to the other input end of the NOR gate device, and the output end of the NOR gate device outputs a clock signal; when the clock enable signal is in a high level, the D trigger does not work, and the clock signal output by the circuit is the sampling clock output by the clock generation circuit; when the clock enabling signal is changed from a high level to a low level, the D trigger is switched on, receives a sampling clock and outputs the high level to the NOR gate device, meanwhile, the clock generating circuit sends the sampling clock to the NOR gate device, and after logical operation is carried out on the NOR gate device, a clock signal is output to a subsequent circuit.
Preferably, the delay sub-circuit is an RC delay circuit.
Preferably, the delay sub-circuit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a capacitor; the grid electrodes of the first PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube receive a clock enabling signal, the source electrode of the first PMOS tube is connected to a power supply voltage, the drain electrode of the first PMOS tube is connected to the source electrode of the second PMOS tube, the drain electrode of the second PMOS tube is connected to the drain electrode of the first NMOS tube and one end of a capacitor, the other end of the capacitor is grounded, the source electrode of the first NMOS tube is connected to the drain electrode of the second NMOS tube, and the source electrode of the second NMOS tube is grounded; the grid electrodes of the third PMOS tube, the fourth PMOS tube, the third NMOS tube and the fourth NMOS tube are connected to the drain electrode of the second PMOS tube, the source electrode of the third PMOS tube is connected to a power supply voltage, the drain electrode of the third PMOS tube is connected to the source electrode of the fourth PMOS tube, the drain electrode of the fourth PMOS tube is connected to the drain electrode of the third NMOS tube and a clock generation circuit, the source electrode of the third NMOS tube is connected to the drain electrode of the fourth NMOS tube, and the source electrode of the fourth NMOS tube is grounded.
Preferably, a second inverter is further disposed between the output terminal of the clock generation circuit and the glitch preventing sub-circuit.
Preferably, the delay time of the delay sub-circuit is greater than one period of the sampling clock.
According to the technical scheme, the delay sub-circuit is added between the clock enabling signal and the clock generating circuit, when the clock enabling signal is low, the clock enabling signal can still keep a high level for a period of time after passing through the delay sub-circuit, and at the moment, the clock generating circuit can still continue to output the sampling clock; meanwhile, the D trigger works and outputs high level to the NOR gate device, and after the NOR gate device performs logic operation, a clock signal is output to a subsequent circuit, so that no burr is generated in the last period of the clock signal.
Drawings
FIG. 1 is a prior art clock signal with output glitches;
FIG. 2 is a schematic diagram of a circuit for preventing output glitch in a clock generation circuit according to an embodiment of the present invention;
FIG. 3 illustrates a clock signal without glitches output by an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of a delay sub-circuit according to an embodiment of the present invention;
fig. 5 is a schematic circuit diagram according to an embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The invention is further described below with reference to the accompanying drawings.
The invention provides a circuit for preventing output glitch in a clock generation circuit, which avoids the situation that an enable signal is suddenly turned off in the normal working process of a clock, the output of the clock generation circuit is pulled to be low, and the output glitch is possibly caused by the fact that a part of the last clock pulse width is eaten away.
As shown in fig. 2, the circuit for preventing output glitch in a clock generation circuit according to the present invention includes a glitch prevention sub-circuit and a delay sub-circuit connected to the clock generation circuit, wherein a clock enable signal CK _ EN is connected to the clock generation circuit through the delay sub-circuit, and the clock generation circuit outputs a sampling clock to the glitch prevention sub-circuit; the anti-glitch circuit comprises a D flip-flop D1, a NOR gate device Nor and a first inverter INV 1; the clock enable signal CK _ EN is connected to a D flip-flop D1 through the first inverter INV1, and provides a control signal for the D flip-flop D1; the sampling clock is respectively connected with the input ends of a D flip-flop D1 and a NOR gate device Nor, the output end of the D flip-flop D1 is connected with the other input end of the NOR gate device Nor, and the output end of the NOR gate device Nor outputs a clock signal CKOUT; when the clock enable signal CK _ EN is at a high level, the D flip-flop D1 does not operate, and the clock signal CKOUT output by the circuit is the sampling clock output by the clock generation circuit; when the clock enable signal CK _ EN changes from a high level to a low level, the D flip-flop D1 is turned on, receives a sampling clock and outputs the high level to the Nor gate device Nor, and the clock generation circuit sends the sampling clock to the Nor gate device Nor, and outputs a clock signal CKOUT to a subsequent circuit after performing logic operation by the Nor gate device Nor.
According to the technical scheme, the delay sub-circuit is additionally arranged between the clock enabling signal CK _ EN and the clock generating circuit, when the clock enabling signal CK _ EN is low, the clock enabling signal CK _ EN can keep a high level for a period of time after passing through the delay sub-circuit, and at the moment, the clock generating circuit can continue to output the sampling clock; meanwhile, the D flip-flop D1 starts to operate, receives the sampling clock and outputs a high level to the Nor device Nor, and after the Nor device Nor receives the sampling clock and the high level sent by the D flip-flop D1 and performs logic operation, the Nor device Nor outputs the clock signal CKOUT to a subsequent circuit, so that a glitch does not occur in the last cycle of the clock signal CKOUT, as shown in fig. 3.
Specifically, when the clock enable signal CK _ EN is high, the clock generation circuit normally outputs the sampling clock to the Nor device Nor, the D flip-flop D1 does not operate, and the Nor device Nor normally outputs the sampling clock. When the clock enable signal CK _ EN is low, the D trigger D1 is switched on and outputs a high level to the NOR gate device Nor; meanwhile, if the D flip-flop D1 outputs a high level, a clock rising edge needs to be input, and in the embodiment of the present invention, the clock enable signal CK _ EN is input to the clock generation circuit in a delayed manner through the delay sub-circuit, so that the clock generation circuit can also maintain a working state, output a sampling clock to the D flip-flop D1 and the Nor device Nor, and start working of the D flip-flop D1; meanwhile, the Nor gate device Nor receives the sampling clock and the high level sent by the D trigger D1 to perform Nor logic operation, so that the output can be pulled low, no glitch occurs in the last period, and no influence is caused on the application of the next-stage system.
Preferably, the delay sub-circuit is an RC delay circuit. In other embodiments, the delay sub-circuit may also be implemented by other delay circuits disclosed in the art, such as a monostable delay circuit or a precision long delay circuit.
Preferably, as shown in fig. 4, the delay sub-circuit includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, and a capacitor C; the gates of the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1 and the second NMOS transistor N2 receive a clock enable signal CK _ EN, the source of the first PMOS transistor P1 is connected to a power voltage VDD, the drain of the first PMOS transistor P1 is connected to the source of the second PMOS transistor P2, the drain of the second PMOS transistor P2 is connected to the drain of the first NMOS transistor N1 and one end of a capacitor C, the other end of the capacitor C is grounded VSS, the source of the first NMOS transistor N1 is connected to the drain of the second NMOS transistor N2, and the source of the second NMOS transistor N2 is grounded VSS; the gates of the third PMOS transistor P3, the fourth PMOS transistor P4, the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected to the drain of the second PMOS transistor P2, the source of the third PMOS transistor P3 is connected to the power voltage VDD, the drain of the third PMOS transistor P3 is connected to the source of the fourth PMOS transistor P4, the drain of the fourth PMOS transistor P4 is connected to the drain of the third NMOS transistor N3 and the clock generation circuit, the source of the third NMOS transistor N3 is connected to the drain of the fourth NMOS transistor N4, and the source of the fourth NMOS transistor N4 is grounded VSS.
Specifically, the first PMOS transistor P1 and the second PMOS transistor P2 form a resistor R in the delay sub-circuit, the delay time of the delay sub-circuit can be adjusted by adjusting the size of the resistor R or the capacitor C, and a worker can design different delay times according to the size of the clock frequency, so as to meet the clock output of different frequencies. When the clock enable signal CK _ EN changes from high level to low level, the clock enable signal CK _ EN with low level is sent to the clock generation circuit in a lagging mode through the delay sub-circuit, and therefore the effect of delaying power failure is achieved.
Preferably, the delay time of the delay sub-circuit is greater than one period of the sampling clock. When the D flip-flop D1 receives a high level input by the first inverter INV1, it starts to operate; then, when the D flip-flop D1 receives the rising edge signal of the sampling clock, a high level is output. Therefore, in order to ensure that the D flip-flop D1 outputs a high level correctly after the enable signal is low, the sampling clock needs to output a rising edge at least once.
In the actual working process, the clock generation circuit can comprise a crystal oscillator, an OSC (oscillator, phase locked loop) and a PLL (phase locked loop) and other clock generation circuits, the frequency is from several MHz to several GHz, even higher and lower, a plurality of clock cycles can be output in a short time, and a common delay circuit can meet the requirement.
In a specific embodiment, as shown in fig. 5, a second inverter INV2 is further disposed between the output end of the clock generation circuit and the glitch prevention sub-circuit. The inverter is arranged at the output end of the clock generation circuit, so that the input and the output in the embodiment of the invention can keep the same phase, and the invention is convenient for project engineering implementation.
It should be understood that the above is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures or equivalent flow transformations made by the present specification and drawings, or applied directly or indirectly to other related technical fields, are included in the scope of the present invention.
Claims (5)
1. A circuit for preventing output glitch in a clock generation circuit is characterized by comprising a glitch prevention sub-circuit and a delay sub-circuit which are connected with the clock generation circuit, wherein a clock enabling signal is connected with the clock generation circuit through the delay sub-circuit, and the clock generation circuit outputs a sampling clock to the glitch prevention sub-circuit;
the anti-burr circuit comprises a D trigger, a NOR gate device and a first phase inverter; the clock enabling signal is connected to the D trigger through the first inverter and provides a control signal for the D trigger; the sampling clock is respectively connected to the input ends of a D trigger and a NOR gate device, the output end of the D trigger is connected to the other input end of the NOR gate device, and the output end of the NOR gate device outputs a clock signal;
when the clock enable signal is in a high level, the D trigger does not work, and the clock signal output by the circuit is the sampling clock output by the clock generation circuit; when the clock enable signal is changed from high level to low level, the D trigger is switched on, receives a sampling clock and outputs high level to the NOR gate device, meanwhile, the clock generation circuit sends the sampling clock to the NOR gate device, and after logical operation is carried out on the NOR gate device, a clock signal is output to a subsequent circuit.
2. The circuit of claim 1, wherein the delay sub-circuit is an RC delay circuit.
3. The circuit for preventing output glitch in a clock generation circuit of claim 1, wherein the delay sub-circuit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a capacitor;
the grid electrodes of the first PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube receive a clock enabling signal, the source electrode of the first PMOS tube is connected to a power supply voltage, the drain electrode of the first PMOS tube is connected to the source electrode of the second PMOS tube, the drain electrode of the second PMOS tube is connected to the drain electrode of the first NMOS tube and one end of a capacitor, the other end of the capacitor is grounded, the source electrode of the first NMOS tube is connected to the drain electrode of the second NMOS tube, and the source electrode of the second NMOS tube is grounded;
the grid electrodes of the third PMOS tube, the fourth PMOS tube, the third NMOS tube and the fourth NMOS tube are connected to the drain electrode of the second PMOS tube, the source electrode of the third PMOS tube is connected to a power supply voltage, the drain electrode of the third PMOS tube is connected to the source electrode of the fourth PMOS tube, the drain electrode of the fourth PMOS tube is connected to the drain electrode of the third NMOS tube and a clock generation circuit, the source electrode of the third NMOS tube is connected to the drain electrode of the fourth NMOS tube, and the source electrode of the fourth NMOS tube is grounded.
4. The circuit for preventing output glitch in a clock generation circuit of claim 1, wherein a second inverter is further provided between the output terminal of the clock generation circuit and the glitch preventing sub-circuit.
5. The circuit of claim 1, wherein the delay time of the delay sub-circuit is greater than one cycle of the sampling clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210768598.3A CN115133914A (en) | 2022-06-30 | 2022-06-30 | Circuit for preventing output glitch in clock generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210768598.3A CN115133914A (en) | 2022-06-30 | 2022-06-30 | Circuit for preventing output glitch in clock generating circuit |
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| CN115133914A true CN115133914A (en) | 2022-09-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202210768598.3A Pending CN115133914A (en) | 2022-06-30 | 2022-06-30 | Circuit for preventing output glitch in clock generating circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116248087A (en) * | 2023-05-08 | 2023-06-09 | 核芯互联科技(青岛)有限公司 | Method and circuit for avoiding burr generation |
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2022
- 2022-06-30 CN CN202210768598.3A patent/CN115133914A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116248087A (en) * | 2023-05-08 | 2023-06-09 | 核芯互联科技(青岛)有限公司 | Method and circuit for avoiding burr generation |
| CN116248087B (en) * | 2023-05-08 | 2023-08-29 | 核芯互联科技(青岛)有限公司 | Method and circuit for avoiding burr generation |
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