CN114039581B - Clock switching circuit - Google Patents
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- CN114039581B CN114039581B CN202111320632.2A CN202111320632A CN114039581B CN 114039581 B CN114039581 B CN 114039581B CN 202111320632 A CN202111320632 A CN 202111320632A CN 114039581 B CN114039581 B CN 114039581B
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- 102100029469 WD repeat and HMG-box DNA-binding protein 1 Human genes 0.000 description 10
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- HCUOEKSZWPGJIM-YBRHCDHNSA-N (e,2e)-2-hydroxyimino-6-methoxy-4-methyl-5-nitrohex-3-enamide Chemical compound COCC([N+]([O-])=O)\C(C)=C\C(=N/O)\C(N)=O HCUOEKSZWPGJIM-YBRHCDHNSA-N 0.000 description 6
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
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Abstract
The invention relates to the technical field of clock switching, and discloses a clock switching circuit which comprises a first clock input end, a second clock input end, a switching signal input end, a control unit, a first feedback unit, a second feedback unit and a clock selection unit; the first clock input end is respectively and electrically connected with the first feedback unit and the clock selection unit, and the second clock input end is respectively and electrically connected with the second feedback unit and the clock selection unit; the switching signal input end is electrically connected with the control unit, when the clock needs to be switched, the first feedback unit or the second feedback unit can stop the transmission of the current clock signal at two continuous level transition moments in the current period of the clock signal and enable the clock signal to start to be ready for transmission, and when the clock signal needs to be transmitted, the level transition moment of the clock signal to be switched is used as a transmission starting point, so that the integrity of the current transmission clock signal is ensured, and burrs are avoided when the clock is switched.
Description
Technical Field
The invention relates to the technical field of clock switching, in particular to a clock switching circuit.
Background
With the progress of integrated circuit manufacturing process, the technology node has been extended to 5-3nm, and the power consumption of the chip becomes an important factor affecting the success of the chip. At present, a plurality of clock sources with different frequencies are configured in a chip when the chip is designed, so that the chip can select corresponding clock sources according to different task loads during actual use, and the power consumption of the chip is controlled.
Existing clock switching circuits in chips often employ multiplexers to select the appropriate clock at different frequencies of clock sources. However, as shown in fig. 1, when the multiplexer is used to select the clock signal, the current clock signal is incomplete and the next clock signal is glitched, so that the cycle integrity of the clock cannot be guaranteed, and these problems may cause serious circuit functional errors.
Disclosure of Invention
In view of the shortcomings of the background technology, the invention provides a clock switching circuit, and aims to solve the technical problem that the clock switching circuit in the existing chip can have incomplete clock switching and burr due to the adoption of a multiplexer, so that the normal use of the chip is affected.
In order to solve the technical problems, the invention provides the following technical scheme: a clock switching circuit comprises a first clock input end, a second clock input end, a switching signal input end, a control unit, a first feedback unit, a second feedback unit and a clock selection unit;
The first clock input end is respectively and electrically connected with the first feedback unit and the clock selection unit, and the second clock input end is respectively and electrically connected with the second feedback unit and the clock selection unit; the switching signal input end is electrically connected with the control unit;
The control unit sends a first stop signal to the first feedback unit when the signal at the switching signal input end is changed from a first state to a second state; after the signal at the switching signal input end is changed from the first state to the second state, the first feedback unit sends a first clock stop signal to the clock selection unit at a first level transition time of the clock signal at the first clock input end, and the first feedback unit sends a first start signal to the control unit at a second level transition time of the clock signal at the first clock input end; the clock selection unit stops outputting a clock signal after receiving the first clock stop signal; the control unit receives the first starting signal and then sends a second starting signal to the second feedback unit; after the second feedback unit receives the second start signal, the second feedback unit sends a clock second start signal to the clock selection unit at a first level transition moment of the clock signal at the second clock input end, and the clock selection unit starts to output the clock signal at the second clock input end after receiving the clock second start signal;
the control unit sends a second stop signal to the second feedback unit when the signal at the switching signal input end is changed from the second state to the first state; after the signal at the switching signal input end is changed from the second state to the first state, the second feedback unit sends a second clock stop signal to the clock selection unit at a first level transition time of the clock signal at the second clock input end, and the second feedback unit sends a third start signal to the control unit at a second level transition time of the clock signal at the second clock input end; the clock selection unit stops outputting a clock signal after receiving the second clock stop signal; the control unit receives the third starting signal and then sends a fourth starting signal to the first feedback unit, after the first feedback unit receives the fourth starting signal, the first feedback unit sends a clock-starting signal to the clock selection unit at the first level conversion moment of the clock signal at the first clock input end, and the clock selection unit starts to output the clock signal at the first clock input end after receiving the clock-starting signal.
In some embodiments, the first state is a low state and the second state is a high state.
In one embodiment, after the signal at the switching signal input terminal is changed from the first state to the second state, a first level transition time of the clock signal at the first clock input terminal of the first feedback unit refers to a time when the clock signal at the first clock input terminal is transitioned from a high level to a low level, and a second level transition time of the clock signal at the first clock input terminal of the first feedback unit refers to a time when the clock signal at the first clock input terminal is transitioned from a low level to a high level; after the second feedback unit receives the second start signal, a first level transition time of the clock signal at the second clock input end of the second feedback unit refers to a time when the clock signal at the second clock input end is transitioned from a high level to a low level;
After the signal at the switching signal input terminal is changed from the second state to the first state, the first level transition time of the clock signal at the second clock input terminal of the second feedback unit refers to the time when the clock signal at the second clock input terminal is transitioned from the high level to the low level, and the second level transition time of the clock signal at the second clock input terminal of the second feedback unit refers to the time when the clock signal at the second clock input terminal is transitioned from the low level to the high level; after the first feedback unit receives the fourth start signal, a first level transition time of the clock signal at the first clock input end of the first feedback unit refers to a time when the clock signal at the first clock input end is transitioned from a high level to a low level.
In a certain embodiment, the control unit includes a first and gate, a second and gate, and a first inverter, the switching signal input terminal is electrically connected to the input terminal of the first inverter and the first input terminal of the second and gate, the output terminal of the first inverter is electrically connected to the first input terminal of the first and gate, the second input terminal of the first and gate is electrically connected to the first clock start signal output terminal of the second feedback unit, the second input terminal of the second and gate is electrically connected to the second clock start signal output terminal of the first feedback unit, the output terminal of the first and gate is electrically connected to the first feedback unit, and the output terminal of the second and gate is electrically connected to the second feedback unit.
In a certain embodiment, the first feedback unit includes a first negative edge trigger, a first positive edge trigger and a first nor gate, where a clock end of the first negative edge trigger and a clock end of the first positive edge trigger are respectively electrically connected with the first clock input end, an input end of the first negative edge trigger is electrically connected with the control unit, a first stop signal and a first clock start signal sent by the control unit are received, an output end of the first negative edge trigger is respectively electrically connected with the input end of the first positive edge trigger, a first input end of the first nor gate and the clock selection unit, an output end of the first positive edge trigger is electrically connected with the second input end of the first nor gate, and an output end of the first nor gate is electrically connected with the control unit and sends a second clock start signal to the control unit.
In an embodiment, the second feedback unit includes a second negative edge trigger, a second positive edge trigger and a second nor gate, where a clock end of the second negative edge trigger and a clock end of the second positive edge trigger are respectively electrically connected with the second clock input end, an input end of the second negative edge trigger is electrically connected with the control unit, a second stop signal and a clock second start signal sent by the control unit are received, an output end of the second negative edge trigger is respectively electrically connected with an input end of the second positive edge trigger, a first input end of the second nor gate and the clock selection unit, an output end of the second positive edge trigger is electrically connected with a second input end of the second nor gate, and an output end of the second nor gate is electrically connected with the control unit and sends a clock first start signal to the control unit.
In a certain embodiment, the clock selecting unit includes a third and gate, a fourth and gate, and a first or gate, where a first input end of the third and gate is electrically connected to the first clock input end, a second input end of the third and gate is electrically connected to the first feedback unit, receives a first clock stop signal and a clock one start signal sent by the first feedback unit, an output end of the third and gate is electrically connected to the first input end of the first or gate, a first input end of the fourth and gate is electrically connected to the second clock input end, a second input end of the fourth and gate is electrically connected to the second feedback unit, receives a second clock stop signal and a clock two start signal sent by the second feedback unit, an output end of the fourth and gate is electrically connected to the second input end of the first or gate, and an output end of the second or gate outputs a clock signal.
Compared with the prior art, the invention has the following beneficial effects: when the clock signal to be switched is required to be transmitted, the level switching time of the clock signal to be switched is used as a transmission starting point, so that the integrity of the clock signal currently transmitted during clock switching is ensured, burrs are avoided, and clock switching can be realized in one clock period.
Drawings
FIG. 1 is a schematic diagram of a switching waveform of a conventional clock switching circuit;
FIG. 2 is a block diagram of the present invention in an embodiment;
FIG. 3 is a circuit diagram of the present invention in an embodiment;
Fig. 4 is a waveform diagram of the present invention when switching clocks.
Detailed Description
The invention will now be described in further detail with reference to the accompanying drawings. The drawings are simplified schematic representations which merely illustrate the basic structure of the invention and therefore show only the structures which are relevant to the invention.
As shown in fig. 2, a clock switching circuit includes a first clock input terminal CLK1, a second clock input terminal CLK2, a switching signal input terminal SEL, a control unit 1, a first feedback unit 2, a second feedback unit 3, and a clock selection unit 4;
The first clock input end is respectively and electrically connected with the first feedback unit and the clock selection unit, and the second clock input end is respectively and electrically connected with the second feedback unit and the clock selection unit; the switching signal input end is electrically connected with the control unit; wherein the first clock input terminal CLK1 is configured to input a first clock signal, the second clock input terminal CLK2 is configured to input a second clock signal, and the switching signal input terminal SEL is configured to input a switching control signal
The control unit 1 sends a first stop signal to the first feedback unit 2 when the signal at the switching signal input terminal SEL changes from a first state to a second state, wherein the first state to the second state means that the low state is changed to the high state; after the signal at the switching signal input terminal SEL is changed from the first state to the second state, the first feedback unit 2 sends a first clock stop signal to the clock selection unit 4 at a first level transition timing of the clock signal at the first clock input terminal CLK1, and the first feedback unit 2 sends a first start signal to the control unit 1 at a second level transition timing of the clock signal at the first clock input terminal CLK 1; the clock selection unit 4 stops outputting the clock signal after receiving the first clock stop signal; the control unit 1 sends a second starting signal to the second feedback unit 3 after receiving the first starting signal; after the second feedback unit 3 receives the second start signal, the second feedback unit 3 sends a second clock start signal to the clock selection unit 4 at the first level transition time of the clock signal at the second clock input end CLK2, and the clock selection unit 4 starts to output the clock signal at the second clock input end after receiving the second clock start signal; in actual use, the present invention can be implemented by this section to switch the output clock signal from the first clock signal at the first clock input CLK1 to the second clock signal at the second clock input CLK 2.
The control unit 1 sends a second stop signal to the second feedback unit 3 when the signal at the switching signal input terminal SEL changes from a second state to a first state, wherein the second state to the first state means that the high state changes to the low state; after the signal at the switching signal input SEL is changed from the second state to the first state, the second feedback unit 3 sends a second clock stop signal to the clock selection unit 4 at a first level transition instant of the clock signal at the second clock input CLK2, and the second feedback unit 3 sends a third start signal to the control unit 1 at a second level transition instant of the clock signal at the second clock input; the clock selection unit 4 stops outputting the clock signal after receiving the second clock stop signal; after receiving the third start signal, the control unit 1 sends a fourth start signal to the first feedback unit 1, after the first feedback unit 1 receives the fourth start signal, the first feedback unit 2 sends a clock one start signal to the clock selection unit 4 at a first level transition time of the clock signal at the first clock input end CLK1, and the clock selection unit 4 starts to output the clock signal at the first clock input end CLK1 after receiving the clock one start signal; in actual use, the present invention can be implemented by this section to switch the output clock signal from the first clock signal at the second clock input CLK2 to the second clock signal at the first clock input CLK 1.
In this embodiment, the present invention starts to switch the clock signal outputted by the present invention from the first clock signal at the first clock input terminal CLK1 to the second clock signal at the second clock input terminal CLK2 when the signal of the switching signal input terminal SEL is switched from the low level to the high level, and starts to switch the clock signal outputted by the present invention from the first clock signal at the second clock input terminal CLK2 to the second clock signal at the first clock input terminal CLK1 when the signal of the switching signal input terminal SEL is switched from the high level to the low level. In some embodiment, the switching of the clock signal output by the present invention from the first clock signal at the first clock input terminal CLK1 to the second clock signal at the second clock input terminal CLK2 may be started when the signal of the switching signal input terminal SEL transitions from the high level to the low level, and the switching of the clock signal output by the present invention from the first clock signal at the second clock input terminal CLK2 to the second clock signal at the first clock input terminal CLK1 may be started when the signal of the switching signal input terminal SEL transitions from the low level to the high level.
Specifically, as shown in fig. 3, the control unit 1 includes a first AND gate AND1, a second AND gate AND2, AND a first inverter INV1, the switching signal input terminal SEL is electrically connected to the input terminal of the first inverter INV1 AND the first input terminal of the second AND gate AND2, respectively, the output terminal of the first inverter INV1 is electrically connected to the first input terminal of the first AND gate AND1, the second input terminal of the first AND gate AND1 is electrically connected to the clock-start signal output terminal of the second feedback unit 3, the second input terminal of the second AND gate AND2 is electrically connected to the clock-two start signal output terminal of the first feedback unit 2, the output terminal of the first AND gate AND1 is electrically connected to the first feedback unit 1, AND the output terminal of the second AND gate AND2 is electrically connected to the second feedback unit 3.
The first feedback unit 2 includes a first negative edge trigger D1, a first positive edge trigger D2, and a first NOR gate NOR1, where a clock end of the first negative edge trigger D1 and a clock end of the first positive edge trigger D2 are electrically connected to the first clock input CLK1, an input end of the first negative edge trigger D1 is electrically connected to the control unit 1, a first stop signal and a clock-start signal sent by the control unit 1 are received, an output end of the first negative edge trigger D1 is electrically connected to an input end of the first positive edge trigger D2, a first input end of the first NOR gate NOR1, and the clock selection unit 4, respectively, an output end of the first positive edge trigger D2 is electrically connected to a second input end of the first NOR gate NOR1, and an output end of the first NOR gate NOR1 is electrically connected to the control unit 1, and a clock-two start signal is sent to the control unit 1.
The second feedback unit 3 includes a second negative edge trigger D3, a second positive edge trigger D4, and a second NOR gate NOR2, where a clock end of the second negative edge trigger D3 and a clock end of the second positive edge trigger D4 are electrically connected to the second clock input CLK2, respectively, an input end of the second negative edge trigger D3 is electrically connected to the control unit 1, receives a second stop signal and a clock second start signal sent by the control unit 1, and an output end of the second negative edge trigger D3 is electrically connected to an input end of the second positive edge trigger D4, a first input end of the second NOR gate NOR2, and the clock selection unit 4, respectively, an output end of the second positive edge trigger D4 is electrically connected to a second input end of the second NOR gate NOR2, and an output end of the second NOR gate NOR2 is electrically connected to the control unit 1, and sends a clock first start signal to the control unit 1.
The clock selection unit 4 includes a third AND gate AND3, a fourth AND gate AND4, AND a first OR gate OR1, where a first input terminal of the third AND gate AND3 is electrically connected to the first clock input terminal CLK1, a second input terminal of the third AND gate AND3 is electrically connected to the first feedback unit 2, receives the first clock stop signal AND the clock one start signal transmitted by the first feedback unit 2, an output terminal of the third AND gate AND3 is electrically connected to the first input terminal of the first OR gate OR1, a first input terminal of the fourth AND gate AND3 is electrically connected to the second clock input terminal CLK2, a second input terminal of the fourth AND gate AND4 is electrically connected to the second feedback unit 3, receives the second clock stop signal AND the clock two start signal transmitted by the second feedback unit 3, AND an output terminal of the fourth AND gate AND4 is electrically connected to the second input terminal of the first OR gate OR1, AND an output terminal of the second OR gate OR1 outputs the clock signal.
In this embodiment, the first negative edge trigger D1, the first positive edge trigger D2, the second negative edge trigger D3, and the second positive edge trigger D4 are all D triggers.
The switching flow of the circuit in fig. 3 is as follows:
the clock signal output from the output of the second OR gate OR1 is switched from the clock signal of the second clock input CLK2 to the clock signal of the first clock output CLK1 as follows:
Before the selection signal of the switching signal input terminal SEL changes, the output terminal of the second OR gate OR1 outputs the clock signal of the second clock input terminal CLK2, AND at this time, the second feedback signal output by the second NOR gate NOR2 is in a low level state, AND acts together with the selection signal on the first negative edge register D1, so that the first negative edge register D1 inputs a low level signal to the third AND gate AND3, AND the first OR gate OR1 does not output the clock signal of the first clock output terminal CLK 1;
The selection signal of the switching signal input terminal SEL changes from high level to low level, acts on the second AND gate AND2, emits a second stop signal of low level, changes into a second clock stop signal after synchronization of the second negative edge trigger D3, AND inputs the second clock stop signal to the fourth AND gate AND4, so that the first OR gate OR1 does not output the clock signal of the second clock output terminal CLK2, AND at this time, half period of the clock signal of the second clock input terminal CLK2 passes;
The second positive edge register D4 synchronizes the control signal again at the positive edge of the clock signal at the second clock input CLK2, AND the output control signal is nor-operated with the second clock stop signal after being synchronized with the second negative edge register, AND sends the second clock control feedback signal to the first AND gate AND1 at the next positive edge of the clock signal at the second clock input CLK 2.
The second clock control feedback signal is in a high level state, AND acts as a first AND gate AND1 together with the selection signal at the switching signal input terminal SEL, the first AND gate AND1 inputs a high level fourth start signal to the first negative edge flip-flop, AND after the fourth start signal is synchronized by the first negative edge flip-flop D1, the negative edge of the clock signal at the first clock input terminal CLK1 is transferred to the third AND gate AND3, so that the first OR gate OR1 starts to output the clock signal at the first clock input terminal CLK 1.
The waveform diagram of the clock signal output at the output end of the second OR gate OR1 is shown in fig. 4, wherein CLK1 is the clock waveform at the first clock input end CLK1, CLK2 is the clock waveform at the second clock input end CLK2, SEL is the waveform at the switching signal input end SEL, the clock-negative edge output is the waveform of the output signal of the output end of the first negative edge flip-flop, the clock-positive edge output is the waveform of the output signal of the output end of the first positive edge flip-flop, the clock-control feedback is the waveform of the output signal of the output end of the first NOR gate NOR1, the clock-negative edge output is the waveform of the output signal of the output end of the second negative voltage transformation flip-flop D3, and CKOUT is the waveform of the clock signal output at the output end of the first OR gate OR 1.
In fig. 4, when SEL changes from low to high, a first negative edge flip-flop D1 outputs a first clock stop signal of low level at a time point when the first high level of CLK1 is changed to low level, i.e., a broken line corresponding to 1, an output terminal of the first OR gate OR1 does not output a clock signal at the first clock input terminal CLK1, a first start signal of high level is input to the second AND gate AND2 from the first positive edge register D2 at a time point when the first low level of CLK1 is changed to high level, i.e., a broken line corresponding to 3, a first start signal of high level is input to the fourth AND gate AND4 at a time point when the first OR gate OR1 starts outputting a clock signal at the second clock input terminal CLK 2. As can be seen from fig. 4, the clock signal switching according to the present invention can be completed within one cycle of the clock signal, and the cycle of the current clock signal is complete during switching, and no glitch is generated.
The clock signal output from the output of the second OR gate OR1 is switched from the clock signal at the first clock input CLK1 to the clock signal at the second clock output CLK2 as follows:
Before the selection signal of the switching signal input terminal SEL changes, the output terminal of the second OR gate OR1 outputs the clock signal at the first clock input terminal CLK1, at which time the second feedback signal output by the first NOR gate NOR1 is in a low state, the second negative edge register D3 is applied to the select signal in one pass, so that the second negative edge register D3 inputs a low level signal to the fourth AND gate AND4, AND the first OR gate OR1 does not output the clock signal of the second clock output terminal CLK 2.
The selection signal of the switching signal input terminal SEL changes from low level to high level, acts on the first AND gate AND1, AND emits a first stop signal, AND after being synchronized by the first negative edge trigger D1DE, the first stop signal becomes a first clock stop signal AND is input to the third AND gate AND3, so that the first OR gate OR1 does not output the clock signal of the first clock output terminal CLK1, AND at this time, half period of the clock signal of the first clock input terminal CLK1 passes.
The first positive edge register D2 synchronizes the control signal again at the positive edge of the clock signal at the first clock input CLK1, AND the output control signal is nor-operated with the first clock stop signal after being synchronized with the first negative edge register, AND sends the first clock control feedback signal to the second AND gate AND2 at the next positive edge of the clock signal at the first clock input CLK 1.
The first clock control feedback signal is in a high level state, AND acts as a second AND gate AND2 together with the selection signal at the switching signal input terminal SEL, the second AND gate AND2 inputs a high level second start signal to the second negative edge flip-flop D3, AND after the second start signal is synchronized by the second negative edge flip-flop D3, the negative edge of the clock signal at the second clock input terminal CLK2 is transferred to the fourth AND gate AND4, so that the first OR gate OR1 starts to output the clock signal at the second clock input terminal CLK 2.
Specifically, in the present embodiment, since the output terminal of the first AND gate AND1 is electrically connected to the input terminal of the first negative edge flip-flop D1, the output terminal of the first negative edge flip-flop D1 is electrically connected to the input terminal of the first positive edge flip-flop D2, after the signal at the switching signal input terminal SEL changes from the first state to the second state, the first level transition timing of the clock signal at the first clock input terminal CLK1 by the first feedback unit 2 refers to the timing at which the clock signal at the first clock input terminal CLK1 transitions from the high level to the low level, AND the second level transition timing of the clock signal at the first clock input terminal CLK1 by the first feedback unit 2 refers to the timing at which the clock signal at the first clock input terminal CLK1 transitions from the low level to the high level; in an embodiment, after the positions of the first negative edge trigger D1 and the first positive edge trigger D2 in the first feedback unit 2 are interchanged, the first level transition time in this section of content may be the time when the low level transitions to the high level, and the second level transition time is the time when the high level transitions to the low level, where the position of the second negative edge trigger D3 in the second matching unit also needs to be interchanged with the position of the second positive edge trigger D4.
Specifically, in this embodiment, after the second feedback unit 3 receives the second start signal, the first level transition time of the clock signal at the second clock input terminal CLK2 of the second feedback unit 3 refers to a time when the clock signal at the second clock input terminal transitions from a high level to a low level, AND at this time, the output terminal of the first AND gate AND1 is electrically connected to the input terminal of the first negative edge flip-flop D1; in an embodiment, the first level transition time in this paragraph is a time when the low level transitions to the high level, and the positions of the first negative edge flip-flop D1 and the first positive edge flip-flop D2 in the first feedback unit 2 need to be interchanged.
In summary, when the clock is required to be switched in actual use, the first feedback unit 1 or the second feedback unit 2 can stop the transmission of the current clock signal at two continuous level transition moments in the current period of the clock signal and enable the clock signal to be ready to be transmitted, and when the clock signal to be switched is required to be transmitted, the level transition moment of the clock signal to be switched is taken as a transmission starting point, so that the integrity of the current transmitted clock signal is ensured, burrs are avoided, and the clock switching can be realized in one clock period.
The present invention has been made in view of the above-described circumstances, and it is an object of the present invention to provide a portable electronic device capable of performing various changes and modifications without departing from the scope of the technical spirit of the present invention. The technical scope of the present invention is not limited to the description, but must be determined according to the scope of claims.
Claims (7)
1. The clock switching circuit is characterized by comprising a first clock input end, a second clock input end, a switching signal input end, a control unit, a first feedback unit, a second feedback unit and a clock selection unit;
The first clock input end is respectively and electrically connected with the first feedback unit and the clock selection unit, and the second clock input end is respectively and electrically connected with the second feedback unit and the clock selection unit; the switching signal input end is electrically connected with the control unit;
the control unit sends a first stop signal to the first feedback unit when the signal at the switching signal input end is changed from a first state to a second state; after the signal at the switching signal input end is changed from the first state to the second state, the first feedback unit sends a first clock stop signal to the clock selection unit at a first level transition time of the clock signal at the first clock input end, and the first feedback unit sends a first start signal to the control unit at a second level transition time of the clock signal at the first clock input end; the clock selection unit stops outputting a clock signal after receiving the first clock stop signal; the control unit receives the first starting signal and then sends a second starting signal to the second feedback unit; after the second feedback unit receives the second start signal, the second feedback unit sends a clock second start signal to the clock selection unit at a first level transition moment of the clock signal at the second clock input end, and the clock selection unit starts to output the clock signal at the second clock input end after receiving the clock second start signal;
the control unit sends a second stop signal to the second feedback unit when the signal at the switching signal input end is changed from the second state to the first state; after the signal at the switching signal input end is changed from the second state to the first state, the second feedback unit sends a second clock stop signal to the clock selection unit at a first level transition time of the clock signal at the second clock input end, and the second feedback unit sends a third start signal to the control unit at a second level transition time of the clock signal at the second clock input end; the clock selection unit stops outputting a clock signal after receiving the second clock stop signal; the control unit receives the third starting signal and then sends a fourth starting signal to the first feedback unit, after the first feedback unit receives the fourth starting signal, the first feedback unit sends a clock-starting signal to the clock selection unit at the first level conversion moment of the clock signal at the first clock input end, and the clock selection unit starts to output the clock signal at the first clock input end after receiving the clock-starting signal.
2. The clock switching circuit of claim 1, wherein the first state is a low state and the second state is a high state.
3. The clock switching circuit of claim 1, wherein after the signal at the switching signal input terminal changes from the first state to the second state, a first level transition timing of the clock signal at the first clock input terminal by the first feedback unit means a timing at which the clock signal at the first clock input terminal transitions from a high level to a low level, and a second level transition timing of the clock signal at the first clock input terminal by the first feedback unit means a timing at which the clock signal at the first clock input terminal transitions from a low level to a high level; after the second feedback unit receives the second start signal, a first level transition time of the clock signal at the second clock input end of the second feedback unit refers to a time when the clock signal at the second clock input end is transitioned from a high level to a low level;
After the signal at the switching signal input terminal is changed from the second state to the first state, the first level transition time of the clock signal at the second clock input terminal of the second feedback unit refers to the time when the clock signal at the second clock input terminal is transitioned from the high level to the low level, and the second level transition time of the clock signal at the second clock input terminal of the second feedback unit refers to the time when the clock signal at the second clock input terminal is transitioned from the low level to the high level; after the first feedback unit receives the fourth start signal, a first level transition time of the clock signal at the first clock input end of the first feedback unit refers to a time when the clock signal at the first clock input end is transitioned from a high level to a low level.
4. The clock switching circuit according to claim 1, wherein the control unit comprises a first and gate, a second and gate, and a first inverter, the switching signal input terminal is electrically connected to an input terminal of the first inverter and a first input terminal of the second and gate, an output terminal of the first inverter is electrically connected to a first input terminal of the first and gate, a second input terminal of the first and gate is electrically connected to a clock-start signal output terminal of the second feedback unit, a second input terminal of the second and gate is electrically connected to a clock-second start signal output terminal of the first feedback unit, an output terminal of the first and gate is electrically connected to the first feedback unit, and an output terminal of the second and gate is electrically connected to the second feedback unit.
5. The clock switching circuit according to claim 1, wherein the first feedback unit includes a first negative edge trigger, a first positive edge trigger, and a first nor gate, the clock end of the first negative edge trigger and the clock end of the first positive edge trigger are respectively electrically connected to the first clock input end, the input end of the first negative edge trigger is electrically connected to the control unit, a first stop signal and a first clock start signal sent by the control unit are received, the output end of the first negative edge trigger is respectively electrically connected to the input end of the first positive edge trigger, the first input end of the first nor gate, and the clock selection unit, the output end of the first positive edge trigger is electrically connected to the second input end of the first nor gate, and the output end of the first nor gate is electrically connected to the control unit, and sends a second clock start signal to the control unit.
6. The clock switching circuit according to claim 1, wherein the second feedback unit includes a second negative edge trigger, a second positive edge trigger, and a second nor gate, the clock end of the second negative edge trigger and the clock end of the second positive edge trigger are respectively electrically connected to the second clock input end, the input end of the second negative edge trigger is electrically connected to the control unit, the second stop signal and the clock second start signal sent by the control unit are received, the output end of the second negative edge trigger is respectively electrically connected to the input end of the second positive edge trigger, the first input end of the second nor gate, and the clock selection unit, the output end of the second positive edge trigger is electrically connected to the second input end of the second nor gate, and the output end of the second nor gate is electrically connected to the control unit, and sends a clock first start signal to the control unit.
7. The clock switching circuit according to claim 1, wherein the clock selecting unit includes a third and gate, a fourth and gate, and a first or gate, the first input terminal of the third and gate is electrically connected to the first clock input terminal, the second input terminal of the third and gate is electrically connected to the first feedback unit, the first clock stop signal and the first clock start signal sent by the first feedback unit are received, the output terminal of the third and gate is electrically connected to the first input terminal of the first or gate, the first input terminal of the fourth and gate is electrically connected to the second clock input terminal, the second input terminal of the fourth and gate is electrically connected to the second feedback unit, the second clock stop signal and the second clock start signal sent by the second feedback unit are received, the output terminal of the fourth and gate is electrically connected to the second input terminal of the first or gate, and the output terminal of the first or gate outputs the clock signal.
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| CN202111320632.2A CN114039581B (en) | 2021-11-09 | 2021-11-09 | Clock switching circuit |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63169814A (en) * | 1987-01-07 | 1988-07-13 | Tokyo Electric Co Ltd | Frequency switching circuit |
| TW480821B (en) * | 2001-05-29 | 2002-03-21 | Realtek Semiconductor Corp | Multiphase switching circuit with bidirectional switch and without false signal |
| US6873183B1 (en) * | 2003-05-12 | 2005-03-29 | Xilinx, Inc. | Method and circuit for glitchless clock control |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004054350A (en) * | 2002-07-16 | 2004-02-19 | Sony Corp | Clock switching circuit |
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- 2021-11-09 CN CN202111320632.2A patent/CN114039581B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63169814A (en) * | 1987-01-07 | 1988-07-13 | Tokyo Electric Co Ltd | Frequency switching circuit |
| TW480821B (en) * | 2001-05-29 | 2002-03-21 | Realtek Semiconductor Corp | Multiphase switching circuit with bidirectional switch and without false signal |
| US6873183B1 (en) * | 2003-05-12 | 2005-03-29 | Xilinx, Inc. | Method and circuit for glitchless clock control |
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