CN115941382A - Flow control method and device for SPI communication, terminal equipment and storage medium - Google Patents

Abstract

The invention discloses a flow control method, device, terminal equipment and storage medium for SPI communication. The method is applied to a flow control system including a master device and a slave device for SPI communication. The communication channel comprises an SPI interface and two GPIO pins associated with the SPI interface; the method includes: carrying out data transmission through the communication channel between the master device and the slave device; when the slave device sends data to the master device, the The second GPIO pin is set to the first state, and sends an interrupt signal to the master device; the master device initiates transmission after receiving the interrupt signal, and receives the data sent from the slave device; when the slave device detects the first GPIO pin When it changes from high level to low level, it is judged that the data frame transmission is completed. The present invention uses fewer GPIO pins, saves chip hardware resources, and master-slave devices can send data at any time, realize data response and retransmission mechanism, ensure real-time performance and reliability of data, and reduce CPU overhead.

Description

A flow control method, device, terminal equipment and storage medium for SPI communication

technical field

The present invention relates to the field of communication technology, in particular to a flow control method, device, terminal equipment and storage medium for SPI communication.

Background technique

According to the principle of SPI communication, in each Clock cycle, the SPI device will send and receive a bit-sized data (whether it is a master device or a slave device), which means that the device has a bit-sized data exchanged. Since the clock is provided by the master device, the slave device cannot actively send data. If the slave device wants to send data at any time, the master device must use the polling method to continuously initiate transmission, and most of the time the bus is invalid data, resulting in additional CPU overhead for the master device. When the master device and the slave device do not have a fixed frame length, the slave device does not know whether the data collection is completed. In addition, SPI has no specified flow control, and there is no response mechanism to confirm whether data is received, or more GPIO pins are used to realize flow control and response, and the cost is relatively high.

Contents of the invention

The technical problem to be solved by the present invention is to provide a flow control method, device, terminal equipment and storage medium for SPI communication, use less GPIO pins, save chip hardware resources, and the master and slave devices can send data at any time to realize The data response and retransmission mechanism ensures the real-time and reliability of the data and reduces the extra overhead of the CPU.

In order to achieve the above object, an embodiment of the present invention provides a flow control method for SPI communication, which is applied to a flow control system for SPI communication. The flow control system includes a master device and at least one slave device, and the master device and the The communication channel between the slave devices includes an SPI interface and two GPIO pins associated with the SPI interface; wherein, the first GPIO pin is the input of the slave device, and the CS pin in the SPI interface The pin is connected; the second GPIO pin is the output of the slave device, which is connected with the master device, and the flow control method of the SPI communication includes:

performing data transmission between the master device and the slave device through the communication channel;

When the slave device sends data to the master device, the second GPIO pin is set to a first state, and an interrupt signal is sent to the master device;

The master device initiates transmission after receiving the interrupt signal, and receives the data sent from the slave device;

When the slave device detects that the first GPIO pin changes from a high level to a low level, it is determined that the data frame transmission is completed.

As an improvement of the above solution, when the slave device sends data to the master device, the interface transmission length of the slave device is set to a maximum frame length, and the interface transmission length of the master device is set to a minimum frame length.

As an improvement of the above solution, when the slave device detects that the first GPIO pin changes from high level to low level, it is determined that the data frame transmission is completed, and then it also includes:

judging whether the data frame returned from the master device is valid;

If it is valid, then judge the category of the data frame returned from the master device; if it is a request frame, put the data frame returned by the master device into the receiving buffer of the slave device, and generate the response of the request frame frame, put into the sending buffer of the slave device; if it is a response frame, then set the response flag bit, and carry out the transmission of the next frame of data;

If it is invalid, it will directly enter the response waiting, and when the response is received, the sent data frame will be removed from the sending buffer of the slave device, and the next frame of data will be transmitted.

As an improvement of the above solution, when the master device initiates transmission, the sending buffer of the master device is cyclically detected;

When there is a data frame to be sent in the sending buffer of the master device, the data frame to be sent is taken out with a preset frame length, and the SPI interface is called to send the data frame to be sent to the slave device.

As an improvement of the above solution, the calling of the SPI interface sends the data frame to be sent to the slave device, and then further includes:

The master device receives the data frame returned from the slave device, and judges whether the returned data frame is valid;

If it is valid, it will process the valid data frame, and enter the response waiting after the processing is completed;

If it is invalid, it will directly enter the response waiting;

Retransmission is initiated when the response waits for a timeout, and the data frame to be sent is removed from the sending buffer of the master device when the response is received, and the next frame of data is transmitted.

As an improvement of the above solution, the processing of the effective data frame specifically includes:

judging whether the length of the valid data frame is not greater than the preset frame length;

If not, initiate a second transmission to receive the remaining unreceived data;

If so, then judge the category of the valid data frame;

If the valid data frame is a request frame, then put the valid data frame into the receiving buffer of the master device, generate a response frame of the request frame, and put it into the sending buffer of the master device;

If the valid data frame is a response frame, the response flag bit is set to transmit the next frame of data.

As an improvement of the above scheme, the length of the valid data frame is the sum of the length of the frame header, the length of the data and the length of the check area.

The embodiment of the present invention also provides a flow control device for SPI communication, which is applied to the flow control system of SPI communication. The flow control system includes a master device and at least one slave device, and the master device and the slave device The communication channel comprises an SPI interface and two GPIO pins associated with the SPI interface; wherein, the first GPIO pin is the input of the slave device and is connected to the CS pin in the SPI interface; the second Two GPIO pins are the output of the slave device, connected with the master device, and the flow control device of the SPI communication includes:

a transmission module, configured to perform data transmission between the master device and the slave device through the communication channel;

An interrupt module, configured to set the second GPIO pin to a first state and send an interrupt signal to the master device when the slave device sends data to the master device;

A receiving module, configured for the master device to initiate transmission after receiving the interrupt signal, and receive data sent from the slave device;

The detection module is configured to determine that the data frame transmission is completed when the slave device detects that the first GPIO pin changes from a high level to a low level.

An embodiment of the present invention also provides a terminal device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, the above-mentioned The flow control method of the SPI communication described in any one.

An embodiment of the present invention also provides a computer-readable storage medium, the computer-readable storage medium includes a stored computer program, wherein, when the computer program is running, the device where the computer-readable storage medium is located is controlled to perform any of the above tasks. A flow control method of the SPI communication.

Compared with the prior art, the beneficial effect of the flow control method, device, terminal device and storage medium of the SPI communication provided by the embodiment of the present invention is that: through the communication channel between the master device and the slave device, two communication channels with SPI are added. The GPIO pins associated with the interface, wherein the first GPIO pin is the input of the slave device and is connected to the CS pin in the SPI interface; the second GPIO pin is the output of the slave device and is connected to the master device. Perform data transmission between the master device and the slave device through the communication channel; when the slave device sends data to the master device, set the second GPIO pin to the first state, and send the data to the master device Interrupt signal; the master device initiates transmission after receiving the interrupt signal, and receives data sent from the slave device; when the slave device detects that the first GPIO pin changes from a high level to a low level , to determine that the data frame transmission is complete. The embodiment of the present invention uses fewer GPIO pins, which saves chip hardware resources. The master and slave devices can send data at any time, realize the data response and retransmission mechanism, ensure the real-time performance and reliability of the data, and reduce the extra overhead of the CPU. .

Description of drawings

Fig. 1 is the flow diagram of a preferred embodiment of the flow control method of a kind of SPI communication provided by the present invention;

Fig. 2 is the structural representation of a preferred embodiment of the flow control system of a kind of SPI communication provided by the present invention;

Fig. 3 is a schematic flow diagram of a slave device initiating transmission in a flow control method of SPI communication provided by the present invention;

Fig. 4 is a schematic flow diagram after the master device receives the transfer request from the device in the flow control method of a kind of SPI communication provided by the present invention;

Fig. 5 is a schematic flow diagram of a master device initiating a transmission in a flow control method for SPI communication provided by the present invention;

Fig. 6 is a schematic flow diagram of a master device processing valid data frames in a flow control method for SPI communication provided by the present invention;

Fig. 7 is the structural representation of effective data frame in the flow control method of a kind of SPI communication provided by the present invention;

Fig. 8 is a schematic structural diagram of a preferred embodiment of a flow control device for SPI communication provided by the present invention;

Fig. 9 is a schematic structural diagram of a preferred embodiment of a terminal device provided by the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

Please refer to FIG. 1 . FIG. 1 is a schematic flowchart of a preferred embodiment of a flow control method for SPI communication provided by the present invention. The flow control method of the SPI communication is applied to the flow control system of the SPI communication, the flow control system includes a master device and at least one slave device, and the communication channel between the master device and the slave device includes an SPI interface and Two GPIO pins associated with the SPI interface; wherein, the first GPIO pin is the input of the slave device, connected with the CS pin in the SPI interface; the second GPIO pin is the slave The output of the device is connected with the master device, and the flow control method of the SPI communication includes:

S1, performing data transmission between the master device and the slave device through the communication channel;

S2. When the slave device sends data to the master device, set the second GPIO pin to a first state, and send an interrupt signal to the master device;

S3. The master device initiates transmission after receiving the interrupt signal, and receives data sent from the slave device;

S4. When the slave device detects that the first GPIO pin changes from a high level to a low level, determine that the data frame transmission is completed.

Specifically, please refer to FIG. 2 . FIG. 2 is a schematic structural diagram of a preferred embodiment of an SPI communication flow control system provided by the present invention. The flow control system for SPI communication in the embodiment of the present invention includes a master device and at least one slave device, and the communication channel between the master device and the slave device includes an SPI interface and two GPIO pins associated with the SPI interface. Wherein, the first GPIO pin is the input of the slave device, and is connected with the CS pin in the SPI interface. The second GPIO pin is the output of the slave device, which is connected to the master device. The SPI interface includes MOSI, MISO, SCLK and CS signal lines. Among them, SCLK, MOSI, and CS signals are all controlled and generated by the master device, and SCLK is a clock signal for synchronizing data. MOSI is the master device output slave device input signal, the master device transmits data to the slave device through this signal line. CS is a chip select signal, which is used to select a slave device and is active at low level. The MISO signal is generated by the slave device, and the master device reads the data of the slave device through the signal line. The signals of MOSI and MISO are only valid when CS is low, and MOSI and MISO transmit one bit of data in each clock cycle of SCLK. In the embodiment of the present invention, data transmission is performed between the master device and the slave device through a communication channel. When the slave device actively sends data to the master device, the second GPIO pin is set to the first state, and an interrupt signal is sent to the master device. Wherein, the first state means that GPIO2 is set from a high level (the default state is a high level) to a low level and then to a high level, because the master device uses a falling edge to trigger an interrupt. After receiving the interrupt signal, the master device initiates the transmission and receives the data sent from the slave device. If the master device does not initiate a transfer, the slave device will always block. When the slave device detects that the first GPIO pin changes from a high level to a low level, it is determined that the data frame transmission is completed.

It should be noted that in SPI communication, the SPI master device sends the SPI slave device to the SPI slave device through the SCLK line at the frequency supported by the slave device, which means that the slave device cannot actively send data to the master device. The slave device sends or the slave device actively informs the master device of the arrival of data through an IO port. Therefore, in the embodiment of the present invention, two GPIO pins associated with the SPI interface are added to the communication channel between the master device and the slave device.

The embodiment of the present invention uses fewer GPIO pins to realize the flow control of SPI communication, the master device uses one GPIO pin, and the slave device uses two GPIO pins, the hardware structure is simple, and chip hardware resources are saved. The slave device uses the maximum frame length for transmission, and the master device judges whether to perform secondary transmission by detecting the data length in the frame header. Therefore, the master and slave devices do not need to use a fixed frame length to send and receive data, and the transmission frame length is determined by the actual data length to be transmitted each time, avoiding additional clock overhead. The slave device uses the GPIO interrupt to notify the master device to start transmission, the slave device can actively send data at any time, and the master device does not need to receive data in a loop, which reduces the CPU resource usage. The master-slave device can send and receive data at any time and process the received data when sending, realizing full-duplex transmission of valid data and greatly improving the communication rate of SPI. Both the master and slave devices implement the software response retransmission mechanism to ensure the correctness of each data transmission and reception.

In another preferred embodiment, when the slave device sends data to the master device, the interface transmission length of the slave device is set to a maximum frame length, and the interface transmission length of the master device is set to a minimum frame length.

Specifically, since the master device may initiate multiple calls, and the slave device does not know how long each transmission will be, it is necessary to set the interface transmission length of the slave device to the maximum frame length, and the interface transmission length of the master device to the minimum frame length long.

In yet another preferred embodiment, when the slave device detects that the first GPIO pin changes from a high level to a low level, it is determined that the data frame transmission is completed, and then it also includes:

judging whether the data frame returned from the master device is valid;

If it is valid, then judge the category of the data frame returned from the master device; if it is a request frame, put the data frame returned by the master device into the receiving buffer of the slave device, and generate the response of the request frame frame, put into the sending buffer of the slave device; if it is a response frame, then set the response flag bit, and carry out the transmission of the next frame of data;

If it is invalid, it will directly enter the response waiting, and when the response is received, the sent data frame will be removed from the sending buffer of the slave device, and the next frame of data will be transmitted.

Specifically, please refer to Fig. 3 and Fig. 4, Fig. 3 is a schematic flow chart of a flow control method for SPI communication provided by the present invention, and Fig. 4 is a flow control method for SPI communication provided by the present invention Schematic diagram of the process after the master device receives the transfer request from the slave device. When the slave device actively sends data to the master device, it takes out the data frame to be sent from the send buffer of the slave device, sets the second GPIO pin to the first state, sends an interrupt signal to the master device, and notifies the master device to initiate the transmission. After receiving the interrupt signal, the master device initiates the transmission and receives the data sent from the slave device. In the receiving state, when the slave device detects that the first GPIO pin changes from high level to low level, it determines that the data frame transmission is completed, exits the receiving state, and processes the received data. Determine whether the data frame returned from the master device is valid. If valid, judge the type of the data frame returned from the master device. If it is a request frame, put the data frame returned by the master device into the receive buffer of the slave device, generate a response frame of the request frame, and put it into the send buffer of the slave device. If it is a response frame, set the response flag bit to transmit the next frame of data. If it is invalid, it will directly enter the response waiting, and when the response is received, the sent data frame will be removed from the sending buffer of the slave device, and the next frame of data will be transmitted.

It should be noted that, unlike the master device processing the received valid data frame, the slave device does not need to perform secondary transmission, and can judge whether the entire data frame transmission is completed through the state of GPIO1.

The embodiment of the present invention uses fewer GPIO pins, which saves chip hardware resources. The master and slave devices can send data at any time, realize the data response and retransmission mechanism, ensure the real-time performance and reliability of the data, and reduce the extra overhead of the CPU. .

In yet another preferred embodiment, when the master device initiates transmission, the sending buffer of the master device is cyclically detected;

When there is a data frame to be sent in the sending buffer of the master device, the data frame to be sent is taken out with a preset frame length, and the SPI interface is called to send the data frame to be sent to the slave device.

Specifically, please refer to FIG. 5 . FIG. 5 is a schematic flowchart of a master device initiating transmission in a flow control method for SPI communication provided by the present invention. When the master device initiates transmission, the sending task continuously checks the send buffer of the master device in a loop. When there are data frames to be sent in the sending buffer of the master device, the data frame to be sent is taken out with the preset frame length sLen, and the SPI interface is called to send the data frame to be sent to the slave device.

In yet another preferred embodiment, the calling the SPI interface to send the data frame to be sent to the slave device, and then also include:

The master device receives the data frame returned from the slave device, and judges whether the returned data frame is valid;

If it is valid, it will process the valid data frame, and enter the response waiting after the processing is completed;

If it is invalid, it will directly enter the response waiting;

Retransmission is initiated when the response waits for a timeout, and the data frame to be sent is removed from the sending buffer of the master device when the response is received, and the next frame of data is transmitted.

Specifically, please refer to FIG. 6 . FIG. 6 is a schematic flowchart of a master device processing valid data frames in a flow control method for SPI communication provided by the present invention. When there are data frames to be sent in the sending buffer of the master device, the data frame to be sent is taken out with the preset frame length, and after calling the SPI interface to send the data frame to be sent to the slave device, the master device receives the data frame returned from the slave device and judges the return Is the data frame valid. If the data frame returned from the device is valid, it will process the valid data frame, and enter the response waiting after the processing is completed. If the data frame returned from the device is invalid, it will directly enter the response waiting. If the response waits for timeout, retransmission is initiated, and when the response is received, the data frame to be sent is removed from the sending buffer of the master device, and the next frame of data is transmitted.

In yet another preferred embodiment, the processing of valid data frames specifically includes:

judging whether the length of the valid data frame is not greater than the preset frame length;

If not, initiate a second transmission to receive the remaining unreceived data;

If so, then judge the category of the valid data frame;

If the valid data frame is a request frame, then put the valid data frame into the receiving buffer of the master device, generate a response frame of the request frame, and put it into the sending buffer of the master device;

If the valid data frame is a response frame, the response flag bit is set to transmit the next frame of data.

Specifically, when processing the valid data frame, the master device obtains the length rLen of the frame data from the frame header of the received data, and judges whether the length rLen of the valid data frame is not greater than the preset frame length sLen. If the length rLen of the valid data frame is greater than the preset frame length sLen, it means that there are still unreceived data frames sent from the device, and it is necessary to call the SPI interface again to initiate a second transmission to complete the reception of the remaining data. If the length rLen of the valid data frame is not greater than the preset frame length sLen, it means that all the data frames sent by the slave device have been received in this call, and the type of the valid data frame is further judged by the frame header information. If the valid data frame is a request frame, put the valid data frame into the receiving buffer of the master device, generate a response frame of the request frame, and put it into the sending buffer of the master device. If the valid data frame is a response frame, it indicates that the last request frame of the master device has received a response, and the next frame of data can be transmitted.

As a preferred solution, the length of the effective data frame is the sum of the length of the frame header, the length of the data and the length of the check area.

Specifically, please refer to FIG. 7, which is a schematic structural diagram of a valid data frame in a flow control method for SPI communication provided by the present invention. The effective data frame in the embodiment of the present invention includes a frame header, data and check area. Among them, the frame header includes identifier, sequence number and total length. The identifier identifies the data type of this frame, which can be a request frame sent from the master device to the slave device, a request frame sent from the slave device to the master device, a response frame sent from the master device to the slave device, and a response frame sent from the slave device to the master device. Sequence number, each request frame sent has a unique sequence number, and the corresponding response frame is consistent with its sequence number. Total length = frame header length + data length + check area length.

Correspondingly, the present invention also provides a flow control device for SPI communication, which can realize all the processes of the flow control method for SPI communication in the above embodiments.

Please refer to FIG. 8 . FIG. 8 is a schematic structural diagram of a preferred embodiment of a flow control device for SPI communication provided by the present invention. The flow control device of the SPI communication is applied to the flow control system of the SPI communication, the flow control system includes a master device and at least one slave device, and the communication channel between the master device and the slave device includes an SPI interface and Two GPIO pins associated with the SPI interface; wherein, the first GPIO pin is the input of the slave device, connected with the CS pin in the SPI interface; the second GPIO pin is the slave The output of the equipment is connected with the main equipment, and the flow control device of the SPI communication includes:

A transmission module 801, configured to perform data transmission between the master device and the slave device through the communication channel;

An interrupt module 802, configured to set the second GPIO pin to a first state and send an interrupt signal to the master device when the slave device sends data to the master device;

A receiving module 803, configured for the master device to initiate transmission after receiving the interrupt signal, and receive data sent from the slave device;

The detection module 804 is configured to determine that the data frame transmission is completed when the slave device detects that the first GPIO pin changes from a high level to a low level.

Preferably, when the slave device sends data to the master device, the interface transmission length of the slave device is set to a maximum frame length, and the interface transmission length of the master device is set to a minimum frame length.

Preferably, when the slave device detects that the first GPIO pin changes from high level to low level, it is determined that the data frame transmission is completed, and then it also includes:

judging whether the data frame returned from the master device is valid;

If it is valid, then judge the category of the data frame returned from the master device; if it is a request frame, put the data frame returned by the master device into the receiving buffer of the slave device, and generate the response of the request frame frame, put into the sending buffer of the slave device; if it is a response frame, then set the response flag bit, and carry out the transmission of the next frame of data;

If it is invalid, it will directly enter the response waiting, and when the response is received, the sent data frame will be removed from the sending buffer of the slave device, and the next frame of data will be transmitted.

Preferably, when the master device initiates a transmission, the sending buffer of the master device is cyclically detected;

When there is a data frame to be sent in the sending buffer of the master device, the data frame to be sent is taken out with a preset frame length, and the SPI interface is called to send the data frame to be sent to the slave device.

Preferably, the calling the SPI interface to send the data frame to be sent to the slave device, and then also include:

The master device receives the data frame returned from the slave device, and judges whether the returned data frame is valid;

If it is valid, it will process the valid data frame, and enter the response waiting after the processing is completed;

If it is invalid, it will directly enter the response waiting;

Retransmission is initiated when the response waits for a timeout, and the data frame to be sent is removed from the sending buffer of the master device when the response is received, and the next frame of data is transmitted.

Preferably, the processing of valid data frames specifically includes:

judging whether the length of the valid data frame is not greater than the preset frame length;

If not, initiate a second transmission to receive the remaining unreceived data;

If so, then judge the category of the valid data frame;

If the valid data frame is a request frame, then put the valid data frame into the receiving buffer of the master device, generate a response frame of the request frame, and put it into the sending buffer of the master device;

If the valid data frame is a response frame, the response flag bit is set to transmit the next frame of data.

Preferably, the length of the effective data frame is the sum of the frame header length, data length and check area length.

In specific implementation, the working principle, control process and technical effects of the flow control device for SPI communication provided by the embodiment of the present invention are the same as those of the flow control method for SPI communication in the above embodiment, and will not be repeated here.

Please refer to FIG. 9 . FIG. 9 is a schematic structural diagram of a preferred embodiment of a terminal device provided by the present invention. The terminal device includes a processor 901, a memory 902, and a computer program stored in the memory 902 and configured to be executed by the processor 901. When the processor 901 executes the computer program, any of the above implementations can be realized. The flow control method of the SPI communication described in the example.

Preferably, the computer program can be divided into one or more modules/units (such as computer program 1, computer program 2, ...), and the one or more modules/units are stored in the memory 902, And be executed by the processor 901 to complete the present invention. The one or more modules/units may be a series of computer program instruction segments capable of accomplishing specific functions, and the instruction segments are used to describe the execution process of the computer program in the terminal device.

The processor 901 can be a central processing unit (Central Processing Unit, CPU), and can also be other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), Field-Programmable Gate Array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., the general-purpose processor can be a microprocessor, or the processor 901 can also be It is any conventional processor, and the processor 901 is the control center of the terminal equipment, and uses various interfaces and lines to connect various parts of the terminal equipment.

The memory 902 mainly includes a program storage area and a data storage area, wherein the program storage area can store an operating system, an application program required by at least one function, etc., and the data storage area can store related data and the like. In addition, the memory 902 can be a high-speed random access memory, or a non-volatile memory, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card and a flash memory Card (Flash Card), etc., or the memory 902 may also be other volatile solid-state storage devices.

It should be noted that the above-mentioned terminal device may include, but not limited to, a processor and a memory. Those skilled in the art can understand that the schematic structural diagram in FIG. 9 is only an example of the above-mentioned terminal device, and does not constitute a limitation on the above-mentioned terminal device. More or fewer components than shown, or combinations of certain components, or different components may be included.

An embodiment of the present invention also provides a computer-readable storage medium, the computer-readable storage medium includes a stored computer program, wherein, when the computer program is running, the device where the computer-readable storage medium is located is controlled to perform any of the above tasks. A flow control method for SPI communication described in an embodiment.

The embodiment of the present invention provides a flow control method, device, terminal device and storage medium for SPI communication, by adding two GPIO pins associated with the SPI interface through the communication channel between the master device and the slave device, wherein, The first GPIO pin is the input of the slave device and is connected to the CS pin in the SPI interface; the second GPIO pin is the output of the slave device and is connected to the master device. Perform data transmission between the master device and the slave device through the communication channel; when the slave device sends data to the master device, set the second GPIO pin to the first state, and send the data to the master device Interrupt signal; the master device initiates transmission after receiving the interrupt signal, and receives the data sent from the slave device; when the slave device detects that the first GPIO pin changes from high level to low level , to determine that the data frame transmission is complete. The embodiment of the present invention uses fewer GPIO pins, which saves chip hardware resources. The master and slave devices can send data at any time, realize the data response and retransmission mechanism, ensure the real-time performance and reliability of the data, and reduce the extra overhead of the CPU. .

It should be noted that the system embodiments described above are only illustrative, and the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physically separated. A unit can be located in one place, or it can be distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in the drawings of the system embodiments provided by the present invention, the connection relationship between modules indicates that they have communication connections, which can be implemented as one or more communication buses or signal lines. It can be understood and implemented by those skilled in the art without creative effort.

The above description is a preferred embodiment of the present invention, and it should be pointed out that for those skilled in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications are also considered Be the protection scope of the present invention.

Claims (10)

1. a flow control method of SPI communication, it is characterized in that, be applied to the flow control system of SPI communication, described flow control system comprises master equipment and at least one slave equipment, between described master equipment and described slave equipment The communication channel includes an SPI interface and two GPIO pins associated with the SPI interface; wherein, the first GPIO pin is the input of the slave device and is connected to the CS pin in the SPI interface; the second The GPIO pin is the output of the slave device, connected with the master device, and the flow control method of the SPI communication includes: performing data transmission between the master device and the slave device through the communication channel; When the slave device sends data to the master device, the second GPIO pin is set to a first state, and an interrupt signal is sent to the master device; The master device initiates transmission after receiving the interrupt signal, and receives the data sent from the slave device; When the slave device detects that the first GPIO pin changes from a high level to a low level, it is determined that the data frame transmission is completed. 2. the flow control method of SPI communication as claimed in claim 1, is characterized in that, when described slave device sends data to described master device, the interface transmission length of described slave device is set as maximum frame length, and described master device The interface transmission length of the device is set to the minimum frame length. 3. the flow control method of SPI communication as claimed in claim 2, is characterized in that, when described from equipment detection described first GPIO pin changes from high level to low level, judges that data frame transmission is completed, Then also include: judging whether the data frame returned from the master device is valid; If it is valid, then judge the category of the data frame returned from the master device; if it is a request frame, put the data frame returned by the master device into the receiving buffer of the slave device, and generate the response of the request frame frame, put into the sending buffer of the slave device; if it is a response frame, then set the response flag bit, and carry out the transmission of the next frame of data; If it is invalid, it will directly enter the response waiting, and when the response is received, the sent data frame will be removed from the sending buffer of the slave device, and the next frame of data will be transmitted. 4. the flow control method of SPI communication as claimed in claim 3, is characterized in that, when described main equipment initiates transmission, the transmission buffer of described main equipment is detected circularly; When there is a data frame to be sent in the sending buffer of the master device, the data frame to be sent is taken out with a preset frame length, and the SPI interface is called to send the data frame to be sent to the slave device. 5. the flow control method of SPI communication as claimed in claim 4, is characterized in that, described calling described SPI interface sends described data frame to be sent to described from equipment, also comprises afterwards: The master device receives the data frame returned from the slave device, and judges whether the returned data frame is valid; If it is valid, it will process the valid data frame, and enter the response waiting after the processing is completed; If it is invalid, it will directly enter the response waiting; Retransmission is initiated when the response waits for a timeout, and the data frame to be sent is removed from the sending buffer of the master device when the response is received, and the next frame of data is transmitted. 6. the flow control method of SPI communication as claimed in claim 5, is characterized in that, described effective data frame is processed, specifically comprises: judging whether the length of the valid data frame is not greater than the preset frame length; If not, initiate a second transmission to receive the remaining unreceived data; If so, then judge the category of the valid data frame; If the valid data frame is a request frame, then put the valid data frame into the receiving buffer of the master device, generate a response frame of the request frame, and put it into the sending buffer of the master device; If the valid data frame is a response frame, the response flag bit is set to transmit the next frame of data. 7. the flow control method of SPI communication as claimed in claim 6, is characterized in that, the length of described valid data frame is the summation of frame header length, data length and check area length. 8. A flow control device for SPI communication, characterized in that, it is applied to a flow control system for SPI communication, and the flow control system includes a master device and at least one slave device, and the connection between the master device and the slave device The communication channel includes an SPI interface and two GPIO pins associated with the SPI interface; wherein, the first GPIO pin is the input of the slave device and is connected to the CS pin in the SPI interface; the second The GPIO pin is the output of the slave device, connected with the master device, and the flow control device of the SPI communication includes: a transmission module, configured to perform data transmission between the master device and the slave device through the communication channel; An interrupt module, configured to set the second GPIO pin to a first state and send an interrupt signal to the master device when the slave device sends data to the master device; A receiving module, configured for the master device to initiate transmission after receiving the interrupt signal, and receive data sent from the slave device; The detection module is configured to determine that the data frame transmission is completed when the slave device detects that the first GPIO pin changes from a high level to a low level. 9. A terminal device, characterized in that it includes a processor and a memory, a computer program is stored in the memory, and the computer program is configured to be executed by the processor, and the processor executes the computer program When realizing the flow control method of the SPI communication as described in any one of claims 1 to 7. 10. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, wherein when the computer-readable storage medium is executed by the device where the computer-readable storage medium is located, the computer program according to claims 1 to 1 is implemented. The flow control method of the SPI communication described in any one of 7.

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