CN102819512A - Full-duplex communication device based on SPI and method thereof - Google Patents
Full-duplex communication device based on SPI and method thereof Download PDFInfo
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Abstract
The invention relates to a full-duplex communication device based on an SPI (serial peripheral interface) and a method thereof. The device comprises a main component, a slave component, a data line used for the mutual communication between the main component and the slave component, a synchronous clock signal line, a slave component selecting signal line and a signal line which is used for requesting the slave component to receive data by the main component and requesting the main component to receive data by the slave component, and the lines are arranged between the main component and the slave component. The communication method comprises the steps that data are sent simultaneously by the main component and the slave component to each other, data are sent from the main component to the slave component, data are sent from the slave component to the main component, and data frames are used for the communication between the main component and the slave component. According to the full-duplex communication device based on the SPI and the method thereof, a full-duplex communication mode is realized, under the condition that the communication rate is invariable, communication efficiency is improved, system response time is improved, and communication data throughput is increased by one time in an ideal condition; and the integrality and the accuracy of respective data frame when data are sent by both of the SPI communication sides at the same time are guaranteed through data verification and the like.
Description
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Technical field
The present invention relates to a kind of communication device and method thereof, be specifically related to a kind of full-duplex communication devices and methods therefor based on SPI.
Background technology
SPI (Serial Peripheral Interface--Serial Peripheral Interface (SPI)) bus system is a kind of synchronous serial Peripheral Interface, and it can make MCU and various peripherals communicate with exchange message with serial mode.4 lines of the general use of SPI: clock cable (CLK), main frame input/slave output data line MISO, main frame output/slave input data line MOSI and the effective slave selection wire of low level CS; Because SPI only takies four lines on the pin of chip, practiced thrift the pin of chip, simultaneously for saving the space on the layout of PCB; Provide convenience; Simultaneously, data rate is also than comparatively fast, and top speed can reach several Mbps.Use and the fast characteristic of data rate from this being simple and easy to just; This communication protocol that present increasing chip is integrated, SPI communication at present is commonly the half-duplex operation mode, and this communication mode is limited in phase same rate, the data volume of being sent in the unit interval; Can cause a large amount of communication delays like this; Consume the communication resource, cause system response time to reduce, and then have influence on user's use.Even some SPI Communication Realization full-duplex communication, but also have the current control do not have appointment, do not have acknowledgement mechanism to confirm whether to receive shortcomings such as data.
Summary of the invention
To the problems referred to above that present SPI communication exists, technical matters to be solved by this invention provides a kind of high efficiency full-duplex communication device and communication means method thereof based on SPI, realizes with following technical scheme:
A kind of full-duplex communication device based on SPI, comprise main device with from device, and be arranged on main device and signal wire from being used for main device between the device and intercoming mutually from device.
Said signal wire comprises: data line MISO and MOSI, and synchronizing clock signals line CLK selects signal wire CS from device, and the main device request receives the signal wire M_REQ of data from device, and receives data signal line S_REQ from device request main device; Said signal wire M_REQ is controlled by main device, is connected in the I/O mouth of main device and between the down trigger mouth of device, and said signal wire S_REQ is by from device control, is connected in between the down trigger mouth of the I/O mouth of device and main device.
A kind of communication means based on the said device of claim 1, comprise main device and the step, main device of sending data to the other side simultaneously from device to send the step of data from device, from the device to the main device, send step and the main device of data with from the employed Frame of communicating by letter between the device; Said Frame data structure comprises the commencing signal represented by the User Defined special character, be used to represent number of frames, the data length that is used to represent these frame data length, the data content of the cycle counter of current transmission frame number, the integrality that is used to detect data and accuracy proof test value, be used to represent to receive successful acknowledge character ACK.
Concrete, said main device with comprise to the step that the other side sends data simultaneously from device:
(1) after main device and the data that are ready to send separately from device, drags down the level of M_CRQ and S_CRQ signal wire simultaneously, trigger the other side and interrupt;
(2) main device receives from the S_CRQ that device sends and has no progeny, and main device is through synchronizing clock signals line CLK tranmitting data register signal;
(3) main device sends the main device data through MOSI, sends from device data through MISO from device synchronization; When byte send finish after, draw high the level of signal wire S_CRQ from device, main device and handle the byte that receives from device respectively;
(4) if do not send from frame data of device and to finish, the then level of degrade signal line S_CRQ, repeating step (2) and (3) then again;
(5) main device or from device after data send to finish, if in setting-up time, do not receive the other side's ack signal, then resend these frame data; Then waits pending data to send to finish afterwards again through one to delay to the other side when predetermined and reply ack signal if receive the other side's ack signal and be in the data transmit status this moment; If it is overtime to be in the idle and predetermined time delay of data transmission this moment, then need not to wait for, send ack signal immediately.
Concrete, said main device comprises to the step of sending data from device:
When (1) main device need send data to from device, the level triggers of degrade signal line M_CRQ was interrupted from device;
(2) from device is received, have no progeny and at first judge oneself state, if be in the data transmit status at this moment from device, the data of then waiting for current byte are sent and are accomplished; If being in idle condition at this moment from device then prepares to receive data, interrupt from device degrade signal line S_REQ level triggers main device;
(3) main device is received behind the signal of device signal line S_CRQ, through synchronizing clock signals line CLK tranmitting data register signal, sends data to from device through data line MOSI again; From drawing high the level of signal wire S_CRQ after device is received data, if receiving, a frame do not finish, then repeated execution of steps (2) and (3);
(4) receive frame data from device after, verification through the back return ack signal and draw high the S_CRQ signal by data line MISO; Main device receives the level of drawing high M_CRQ behind the ack signal.
Concrete, saidly comprise to the step that main device sends data from device:
(1) when device need send data to main device; At first judge oneself state; As be in the then level triggers main device interruption of degrade signal line S_CRQ of idle condition from device, wait for that then triggering main device again after current byte data reception finishes interrupts if be in data receiving state this moment;
(2) main device passes through synchronizing clock signals line CLK tranmitting data register signal after receiving signal wire S_CRQ signal, sends data to main device from device through data line MISO simultaneously; A byte data is sent to finish and is afterwards drawn high the level of signal wire S_CRQ from device, before frame data do not send and do not finish, and repeated execution of steps (1) and (2);
(3) after main device was received frame data, verification was returned ack signal through the back by data line MOSI;
(4) receive the ack signal that main device returns from device, draw high the level of signal wire S_CRQ; Main device is drawn high the level of signal wire M_CRQ more then.
Further; When the proof test value that receives when main device or from device and the proof test value of internal calculation are inconsistent; Then corresponding main device or do not send ack signal from device, corresponding main device or do not receive that from device ack signal then resends corresponding Frame by the method for above-mentioned correspondence in setting-up time.
Further; Main device is to from device transmission data the time; In setting-up time, do not receive from the signal of device signal line S_CRQ behind the main device degrade signal line M_CRQ level, then main device resends these frame data according to main device to the method for sending data from device.
Further; When from the device to the main device, sending data; Behind device degrade signal line S_CRQ level, in setting-up time, do not receive the CLK clock signal of main device, then resend these frame data by the method for from the device to the main device, sending data from device.
Concrete; The said step that resends corresponding Frame and resend these frame data is: finish the transmission of this secondary data; With these frame data receiving unit deletions, and main device and state from device reset to original state, prepare to resend data.
Preferably, main device is used to add up the error counter that frame data send errors number with being provided with from device, when the numerical value of error counter during greater than preset threshold, then these frame data is abandoned, simultaneously the generation error report information.
In sum; The present invention has following remarkable beneficial effect: the communication mode of full duplex has been realized in (1); Under the constant situation of traffic rate, improve communication efficiency, promoted system response time, the data throughout of communicating by letter under the perfect condition is promoted one times; (2), guarantee the two integrality and the accuracys of Frame separately sent out when sending data simultaneously of SPI communication through the transmitting-receiving of data check and ack signal.
Description of drawings
Fig. 1 be main device with from device communication interface synoptic diagram;
Fig. 2 sends schematic diagram data simultaneously for main device with from device;
Fig. 3 is that main device is to sending schematic diagram data from device;
Fig. 4 is for to send schematic diagram data from device to main device;
Fig. 5 is for the main device of adding fault-tolerant design and from the device communication scheme.
Embodiment
Below will combine accompanying drawing and embodiment that the present invention is explained in further detail for the ease of it will be appreciated by those skilled in the art that.
The present invention has disclosed a kind of full-duplex communication device based on SPI, and is as shown in Figure 1, comprise main device with from device, and be arranged on main device and signal wire from being used for main device between the device and intercoming mutually from device.Said signal wire comprises: data line MISO and MOSI, and synchronizing clock signals line CLK selects signal wire CS from device, and the main device request receives the signal wire M_REQ of data from device, and receives data signal line S_REQ from device request main device.
Signal wire M_REQ is connected in the I/O mouth of main device and between the down trigger mouth of device, by main device control, signal wire S_REQ is connected in between the down trigger mouth of the I/O mouth of device and main device, by controlling from device.
Simultaneously; The present invention has also disclosed a kind of communication means based on said apparatus, comprise main device and the step, main device of sending data to the other side simultaneously from device to send the step of data from device, from the device to the main device, send step and the main device of data with from the employed Frame of communicating by letter between the device; Said Frame data structure comprises the commencing signal represented by the User Defined special character, be used to represent number of frames, the data length that is used to represent these frame data length, the data content of the cycle counter of current transmission frame number, the integrality that is used to detect data and accuracy proof test value, be used to represent to receive successful acknowledge character ACK.
As shown in Figure 2, main device and comprise from the step of sending data to the other side simultaneously between the device:
(1) after main device and the data that are ready to send separately from device, drags down the level of M_CRQ and S_CRQ signal wire simultaneously, trigger the other side and interrupt;
(2) main device receives from the S_CRQ that device sends and has no progeny, and main device is through synchronizing clock signals line CLK tranmitting data register signal;
(3) main device sends the main device data through MOSI, sends from device data through MISO from device synchronization; When byte send finish after, draw high the level of signal wire S_CRQ from device, main device and handle the byte that receives from device respectively;
(4) if do not send from frame data of device and to finish, the then level of degrade signal line S_CRQ, repeating step (2) and (3) then again;
(5) main device or from device after data send to finish, if in setting-up time, do not receive the other side's ack signal, then resend these frame data; If receive the other side's ack signal and be in the data transmit status this moment and reply ack signal through after the predetermined time delay (Tframe_delay) to the other side again after then waiting pending data to send to finish; If it is overtime to be in the idle and predetermined time delay (Tframe_delay) of data transmission this moment, then need not to wait for, send ack signal immediately.
So far, main device with send frame data to the other side simultaneously from device and finish.
Main device as shown in Figure 3 comprises to the step of sending data from device:
When (1) main device need send data to from device, the level triggers of degrade signal line M_CRQ was interrupted from device;
(2) from device is received, have no progeny and at first judge oneself state, if be in the data transmit status at this moment from device, the data of then waiting for current byte are sent and are accomplished; If being in idle condition at this moment from device then prepares to receive data, interrupt from device degrade signal line S_REQ level triggers main device;
(3) main device is received behind the signal of device signal line S_CRQ, through synchronizing clock signals line CLK tranmitting data register signal, sends data to from device through data line MOSI simultaneously; From drawing high the level of signal wire S_CRQ after device is received data, after handling the byte that has received from device, if if a frame does not receive to finish, then repeated execution of steps (2) and (3);
(4) if main device continue to send data (that is to say data are sent finish) in a time cycle, receive these frame data from device this moment after, verification is returned ack signal and is drawn high the S_CRQ signal by data line MISO through the back; Draw high M_CRQ after main device receives ack signal simultaneously.
As shown in Figure 4, the step of from the device to the main device, sending data comprises:
(1) when device need send data to main device; At first judge oneself state; As be in the then level triggers main device interruption of degrade signal line S_CRQ of idle condition from device, wait for that then triggering main device again after current byte data reception finishes interrupts if be in data receiving state this moment;
(2) main device passes through synchronizing clock signals line CLK tranmitting data register signal after receiving the S_CRQ signal, sends data to main device from device through data line MISO simultaneously; A byte data is sent the back that finishes and is drawn high S_CRQ from device, before frame data do not send and finish, and repeated execution of steps (1) and (2);
(3) after main device was received frame data, verification was returned ack signal through the back by data line MOSI;
(4) receive the ack signal that main device returns from device, draw high the level of signal wire S_CRQ; Main device is drawn high the level of signal wire M_CRQ more then.
For guaranteeing the integrality of data in the communication process; When the proof test value that receives when main device or from device and the proof test value of internal calculation are inconsistent; Then corresponding main device or do not send ack signal from device, corresponding main device or do not receive that from device ack signal then resends corresponding Frame according to the method for above-mentioned correspondence in setting-up time.
In order further to guarantee the integrality of data in the communication process, two kinds of situation in addition also need resend these frame data:
Main device is to sending data step from device; In setting-up time, do not receive from the signal of device signal line S_CRQ behind the main device degrade signal line M_CRQ level, then main device then resends these frame data according to main device to the method for sending data from device.
From the device to the main device, send data step, behind device degrade signal line S_CRQ level, in setting-up time, do not receive the CLK clock signal of main device, then resend these frame data by the method for from the device to the main device, sending data.
Present embodiment with main device to send data instance from device; As shown in Figure 5; After main device has sent data; Tbyte_Timeout (send the maximum delay that perhaps receives a byte time delay) does not receive the S_CRQ signal from device in the time, then main device need resend these frame data.
The step that resends corresponding Frame and resend these frame data is: finish the transmission of this secondary data, with the deletion of these frame data receiving unit, and main device and state from device reset to original state, prepare to resend data.
For process frames of data is better sent wrong problem; Main device of the present invention is used to add up the error counter that frame data send errors number with being provided with from device; When the numerical value of error counter during greater than preset threshold; Then these frame data are abandoned, simultaneously the generation error report information.
It is to be noted; No matter main device still will send data from device, all must trigger main frame by the S_CRQ from device earlier and interrupt, then by device output CLK clock signal; And with the sending of data, and the M_CRQ signal of main device only representes that main frame need send data.
The foregoing description need to prove for the preferred version that the present invention realizes, conceives under the prerequisite not breaking away from the present invention, and any conspicuous replacement and subtle change are all within protection scope of the present invention.
Claims (10)
1. full-duplex communication device based on SPI, comprise main device with from device, and be arranged on main device with from being used for main device between the device and, it is characterized in that from the signal wire that device intercoms mutually:
Said signal wire comprises: data line MISO and MOSI, and synchronizing clock signals line CLK selects signal wire CS from device, and the main device request receives the signal wire M_REQ of data from device, and receives data signal line S_REQ from device request main device;
Said signal wire M_REQ is controlled by main device, is connected in the I/O mouth of main device and between the down trigger mouth of device, and said signal wire S_REQ is by from device control, is connected in between the down trigger mouth of the I/O mouth of device and main device.
2. duplex communication method based on SPI is characterized in that: comprise main device and the step, main device of sending data to the other side simultaneously from device to send the step of data from device, from the device to the main device, send step and the main device of data with from the employed Frame of communicating by letter between the device;
Said Frame data structure comprises the proof test value of the commencing signal of the sign that is begun to send as data by the User Defined special character, the number of frames, the data length that is used to represent these frame data length, the data content that are used to represent the cycle counter of current transmission frame number, the integrality that is used to detect data and accuracy and is used to represent to receive successful acknowledge character ACK.
3. the duplex communication method based on SPI according to claim 2 is characterized in that: said main device with comprise to the step that the other side sends data simultaneously from device:
(1) after main device and the data that are ready to send separately from device, drags down the level of M_CRQ and S_CRQ signal wire simultaneously, trigger the other side and interrupt;
(2) main device receives from the S_CRQ that device sends and has no progeny, and main device is through synchronizing clock signals line CLK tranmitting data register signal;
(3) main device sends the main device data through MOSI, sends from device data through MISO from device synchronization; When byte send finish after, draw high the level of signal wire S_CRQ from device, main device and handle the byte that receives from device respectively;
(4) if do not send from frame data of device and to finish, the then level of degrade signal line S_CRQ, repeating step (2) and (3) then again;
(5) main device or from device after data send to finish, if in setting-up time, do not receive the other side's ack signal, then resend these frame data; If receive the other side's ack signal and be in this moment the data transmit status then waits pending data to send to finish afterwards again through a setting the time delay to the other side and reply ack signal; If the time delay that is in the data transmission free time and sets is overtime this moment, then need not to wait for, send ack signal immediately.
4. the duplex communication method based on SPI according to claim 2 is characterized in that: said main device comprises to the step of sending data from device:
When (1) main device need send data to from device, the level triggers of degrade signal line M_CRQ was interrupted from device;
(2) from device is received, have no progeny and at first judge oneself state, if be in the data transmit status at this moment from device, the data of then waiting for current byte are sent and are accomplished; If being in idle condition at this moment from device then prepares to receive data, interrupt from device degrade signal line S_REQ level triggers main device;
(3) main device is received behind the signal of device signal line S_CRQ, through synchronizing clock signals line CLK tranmitting data register signal, sends data to from device through data line MOSI again; From drawing high the level of signal wire S_CRQ after device is received data, if receiving, a frame do not finish, then repeated execution of steps (2) and (3);
(4) receive frame data from device after, verification through the back return ack signal and draw high the S_CRQ signal by data line MISO; Main device receives the level of drawing high M_CRQ behind the ack signal.
5. the duplex communication method based on SPI according to claim 2 is characterized in that: saidly comprise to the step that main device sends data from device:
(1) when device need send data to main device; At first judge oneself state; As be in the then level triggers main device interruption of degrade signal line S_CRQ of idle condition from device, wait for that then triggering main device again after current byte data reception finishes interrupts if be in data receiving state this moment;
(2) main device passes through synchronizing clock signals line CLK tranmitting data register signal after receiving signal wire S_CRQ signal, sends data to main device from device through data line MISO simultaneously; A byte data is sent to finish and is afterwards drawn high the level of signal wire S_CRQ from device, before frame data do not send and do not finish, and repeated execution of steps (1) and (2);
(3) after main device was received frame data, verification was returned ack signal through the back by data line MOSI;
(4) receive the ack signal that main device returns from device, draw high the level of signal wire S_CRQ; Main device is drawn high the level of signal wire M_CRQ more then.
6. according to the described duplex communication method of claim 3-5 based on SPI; It is characterized in that: when the proof test value that receives when main device or from device and the proof test value of internal calculation are inconsistent; Then corresponding main device or do not send ack signal from device, corresponding main device or do not receive that from device ack signal then resends corresponding Frame according to method corresponding described in the claim 3-5 in setting-up time.
7. the duplex communication method based on SPI according to claim 4; It is characterized in that: in setting-up time, do not receive from the signal of device signal line S_CRQ behind the main device degrade signal line M_CRQ level, then main device then resends these frame data according to method described in the claim 4.
8. the duplex communication method based on SPI according to claim 5; It is characterized in that: behind the level of device degrade signal line S_CRQ; In setting-up time, do not receive the CLK clock signal of main device, then resend these frame data according to method described in the claim 5.
9. according to the described duplex communication method based on SPI of claim 6-8, it is characterized in that: the said step that resends corresponding Frame and resend these frame data is:
Finish the transmission of this secondary data,, and main device and state from device reset to original state, prepare to resend data these frame data receiving unit deletions.
10. the duplex communication method based on SPI according to claim 9; It is characterized in that: main device is used to add up the error counter that frame data send errors number with being provided with from device; When the numerical value of error counter during greater than preset threshold; Then these frame data are abandoned, simultaneously the generation error report information.
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| CN103744814A (en) * | 2014-01-06 | 2014-04-23 | 深圳市芯海科技有限公司 | High speed communication method by two lines |
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| WO2016046361A1 (en) * | 2014-09-26 | 2016-03-31 | Valeo Systemes Thermiques | Transmission of synchronous data via a serial data bus, in particular a spi bus |
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