KR20050080704A - Apparatus and method of inter processor communication - Google Patents

Abstract

The present invention is to perform communication, i.e., Inter Processor Communication (IPC), between processors existing on the same system, and does not add a load according to data reception to a processor by using Peripheral Component Interconnection Direct Memory Access (PCI DMA). It provides an interprocessor data transfer device and method that can use the PCI bus as an Ethernet interface without having to.

Description

Apparatus and method for transferring data between processors {APPARATUS AND METHOD OF INTER PROCESSOR COMMUNICATION}

The present invention relates to an apparatus and method for transmitting data between processors existing on the same system, and more particularly, to an apparatus and method for transmitting data between processors using PCI.

Nowadays, the system has a trend of having multiple processors instead of a single processor. In particular, systems such as core or edge-class high-capacity routers may be used to properly distribute various services (eg, L2 / L3 forwarding, MPLS, QOS, VLAN, etc.) modules. Use two or more processes, including MPUs (processors with ARM, PPC, MIPS-based cores and various peripherals) that manage the entire system, and processors for specific purposes (e.g. network processors, etc.) It became. As such, as a plurality of processors are used in one system, communication between the processors becomes necessary. (In the past, each processor has a network interface, such as 82559ER, for each processor for IPC (Inter Processor Communication). The data is transmitted through this process. In the past, a pseudo network device driver that uses a Peripheral Component Interconnect (PCI) bus as an Ethernet interface has been used as one of the methods for IPC. In this case, the PCI bus is a local bus that directly connects the central processing unit (CPU) and peripheral devices to provide a data path for transferring data at high speed.

Most modern embedded processors are basically PCI controllers that meet the PCI2.1 specification or higher as peripherals. We have developed a pseudo network device driver that can be used as:

Conventionally, there are two techniques for using IPC as an Ethernet interface through a PCI bus between two or more embedded processors.

First, a PCI controller is controlled between two processors to directly transfer data to be transferred between processors through the PCI bus. This method allows a processor, which is a PCI bus master, to copy data directly to the target processor's synchronous dynamic random access memory (SDRAM) via the PCI address value of the target processor and to send message signal interrupt (MSI) or polling ( Polling) has a structure to inform.

Secondly, the PCI controller is controlled between two or more processors, but the application stage is a pseudo network device driver method for transmitting data by using an IP and a socket interface allocated to each processor.

However, the above-described prior arts have the following problems, respectively.

The first is that application developers must control the PCI bus directly in order to pass data between each processor, so they must have a good knowledge of the processor infrastructure (eg, PCI, SDRAM, OS, device drivers, etc.). do. As a result, software developers are less likely to have consistent coding and efficiency when developing applications that require IPC.

The second technique, compared with the first technique, has a structure of a pseudo network device driver, which allows an application to conveniently transfer data using IP and socket interfaces. However, when the second technology is applied, the processor directly transmits data, and thus, when receiving a large amount of data, the processor cannot perform other tasks, resulting in performance limitations. Also, among two or more processors, data is transmitted only between a master processor and a target processor, and thus data transmission and reception between arbitrary processors is impossible, and only 1: N communication is possible.

Therefore, in order to solve these problems, a new data transmission apparatus that enables data transmission between many-to-many (N: N) processors without incurring coding coherence and efficiency in application development and increased processor load, and You need a way.

Accordingly, it is an object of the present invention to provide an interprocessor data transfer apparatus and method that does not cause coding coherence and efficiency degradation in application development.

Another object of the present invention is to provide an interprocessor data transmission apparatus and method capable of performing data transmission without using a processor resource.

Still another object of the present invention is to provide an interprocessor data transmission apparatus and method capable of performing data transfer between many to many processors.

The present invention uses a pseudo network device driver technology that allows a Peripheral Communication Interface (PCI) bus to be used as an Ethernet interface, and uses a PCI DMA (Direct Memory Access) to receive the data. It is possible to reduce the added load.

Such an apparatus of the present invention is a data transmission apparatus for performing communication between processors existing on the same system, comprising: a processor information storage device storing characteristic information of a processor existing on the system, and a transmission to a counterpart processor; A buffer for storing the data to be transmitted, an interrupt unit for transmitting a signal indicating that there is data to be transmitted to the counterpart processor, and information about a buffer in which the data to be transmitted is stored, and the counterpart processor transmits the direct memory access (DMA). An inter-processor data transmission device including a Peripheral Component Interconnect (PCI) controller to receive data stored in the buffer through the controller.

In addition, the method of the present invention is a data transmission method for performing communication between processors existing on the same system, when data to be transmitted is generated, a first process of storing the data to be transmitted in a buffer, and data to be transmitted. A second step of informing the counterpart processor to transmit the data to the counterpart processor; transmitting information about a buffer in which the data to be transmitted is stored to the counterpart processor through a PCI bus, and transmitting the data to the counterpart processor via DMA. A data transfer method between processors including a third process is performed.

According to another aspect of the present invention, there is provided a data transmission method for performing communication between processors existing on the same system, the method comprising: a first process of being notified of characteristic information of all processors connected through PCI on the system; A second step of receiving a signal indicating that there is data to be transmitted from an arbitrary processor, a third step of obtaining information on a processor to transmit the data using the processor characteristic information, and the PCI bus through the PCI bus; And a fourth process of acquiring information on the buffer in which the data is stored from the processor, and a fifth process of receiving the data through DMA using the information obtained in the fourth process. .

The processor to which the present invention is applied as described above is PCI spec. It is preferred to include a PCI bus of 2.1 or higher, volatile memory for use as a packet buffer, and interrupt lines for signaling.

The processor uses SDRAM (Synchronous Dynamic Random Access Memory) or SRAM (Static RAM) as the memory for the packet buffer, and Message Signal Interrupt (MSI) or hardware interrupt line ( Hardware Interrupt Line can be used.

Here, SDRAM (Synchronous Dynamic Random Access Memory) is a memory device that operates by directly receiving the main clock used by the central processing unit (CPU). It provides a 64-bit data bus and each RAM operates in synchronization with each other. So it runs much faster than conventional RAM. In other words, since the CPU and the storage location proceed synchronously, no waiting time for accessing the storage location is required, and the storage location can be accessed at high speed from the CPU.

SRAM (static RAM) is one of the classifications of RAM, which is a semiconductor memory device, according to a data storage method. Since static RAM does not require refreshing, access is much faster than dynamic RAM. In general, static RAM is reserved for use in the cache.

Memory Direct Access (DMA) is a method in which data transfers are made directly between memory and input / output devices using a direct memory access controller (DMA Controller) (DMAC) and not through a central processing unit (CPU). With direct memory access (DMA), data transfers occur at high speeds and no program delay occurs in the processor. In the present invention, the PCI controller performs the function of DMAC.

Hereinafter, the present invention will be described with reference to the drawings.

1 is a diagram illustrating a configuration of an apparatus for performing data transfer between processors and a data flow in the apparatus according to the present invention.

As shown in FIG. 1, in order to carry out the present invention, each processor 100 and 120 may include a protocol stack 102 or 122, an LPC driver 104 or 124, an MSI 106 or 126, a PCI DMA 108 or 128, SDRAMs 110 and 130 are provided. In addition, a processor information storage device 140 for storing information of each processor is provided.

The protocol stack 102 of processor 1 100 supports each application running on the processor. The LPC driver 104 performs an overall process for communicating with other processors. The LPC driver 104 stores data to be transmitted to another processor, which is received from an application for communication between processors, in the SDRAM 110 and a partner to transmit data from the processor information storage 140 in which information of each processor is stored. It reads the processor's information and informs the partner processor that there is data to send according to the read information. This data is passed directly to the partner processor via the PCI DMA 108. The MSI 106 performs a function of notifying the counterpart processor that will send data that there is a message to send. The PCI DMA 108 informs the counterpart processor of information such as the address of a memory (for example, SDRAM) in which data to be transmitted is stored so that the counterpart processor directly reads the memory through the DMA.

Hereinafter, an operation according to the present invention will be described.

In the following description of the present invention, processor 1 100 becomes a sender for transmitting data, and processor 2 120 becomes a receiver for receiving data.

(1) Prior to data transfer, the system performs an initialization process. A processor that becomes a PCI initiator for each processor performs initialization for each target processor. In general, the PCI initiator may perform initialization using a mailbox register and SDRAM. When performing initialization, the PCI initiator collects property information of all processors connected through the PCI bus and registers the information in the processor information storage 140 with a predetermined data structure. Examples of the processor characteristic information include a processor ID, a packet buffer address, and an IP. In general, the PCI initiator announces through the PCI mailbox register so that each processor knows the data structure created above.

(2) The application of the processor 1 (100) transmits a message to a destination network interface (the target processor in the present invention) through a socket system call provided by the OS. The message generated by the application is transferred to the packet buffer (eg, SDRAM) of the pseudo network device driver through the OS system call (2-1) and generates a packet descriptor (2-2). Processor 1 100 sets a lock to processor 2 120 (generally sets the corresponding field of processor 2 to 1). This informs that processor 1 100 has started transmitting data to processor 2 120 (2-3). If processor 2 does not release this lock (meaning that processor 2 has not yet completed its reception) and processor 1 (100) attempts to transmit again, it is treated as a write fail and the processor 1 (100) The application or protocol stack 102 retransmits until successful.

(3) Processor 1 (100) notifies Processor 2 (120) that there is a message to transmit via MSI (or H / W interrupt line) 106 (3-1). Processor 2 (120) receiving an interrupt from processor 1 (100) knows which processor sent the interrupt to send a message (3-2). This process is performed through MSI's BIT MAP check or processor ID check. Here, the bitmap (BITMAP) refers to an indexing method based on bits.

(4) Processor 2 (120) reads the packet descriptor of processor 1 (100) over the PCI bus (4-1, 4-2), sets up its PCI DMA 128 and performs DMA transfers. Starts (4-3, 4-4) Data reception is performed by reading data directly from memory, not through the processor via DMA, so that the processor can process other tasks.

(5) Processor 2 (120) receives DMA completion interrupt (5-1) from PCI DMA 128 when data reception through DMA is completed (Process Processor 1 (100)) to Processor 2 (120). It releases the locked lock and makes the state of the packet descriptor of the processor 1 100 free so that another message can be received from the processor 1 100 (5-2).

(6) Data is received to a destination application via the OS / protocol stack 122 of processor 2 120.

These processes are summarized as follows.

First, the initialization is performed to collect and store processor characteristic information such as processor ID, packet buffer address, and IP of each processor and notify each processor.

Second, the processor (for example, processor 1) 100 to transmit data stores a message to be transmitted in a packet buffer (generally implemented using SDRAM) 110 and indicates a packet descriptor (e.g., its storage location). packet descriptor).

Third, the processor 1 100 notifies the counterpart processor (for example, the processor 2) 120 to which data is to be transmitted by using an MSI or H / W interrupt line.

Fourth, upon receiving an interrupt indicating that there is data to be transmitted from processor 1 (100), processor 2 (120) reads the packet descriptor of processor 1 (100) via the PCI bus, and accordingly the packet buffer 110 through DMA. Processor 1 100 receives the data by reading the data to be transmitted.

Fifth, when the DMA transfer is completed, it notifies the processor 1 (100).

Sixth, data reception is completed by transmitting data read from the packet buffer 110 to the application through the protocol stack 122.

By applying the present invention as described above it is possible to perform the IPC using a PCI controller embedded in the processor as a peripheral device. Application developers can use it in the same way over the PCI bus as they use the socket system call to send data through a network driver on an operating system (such as linux). In other words, it can be seen that the lower physical interface is replaced by the PCI controller in the MAC / PHY chip, and abstracted to the application developer so that only the system call of the OS can be used. In the case of network equipment, data can be transmitted and received using a unified system call (eg, socket, etc.) provided by the OS between applications. By using the PCI DMA built into the PCI controller when receiving data, the processor load when receiving data can be reduced, and accordingly, CPU time can be allocated to other tasks to perform other tasks during data reception. The processor characteristic information can be used to receive data transmitted by any processor connected to the PCI bus.

On the other hand, the specific device and OS environment, etc. mentioned while describing the present invention are only intended to help the understanding of the present invention, and the present invention is not limited thereto.

Applying the present invention, since a separate hardware device for the IPC is not required, the effect of cost reduction and equipment size reduction occurs. The application developer can perform data transmission using only the system call of the OS, thereby reducing the development period. Software can be written consistently using a unified system call provided by the operating system between applications. Performance limitations can be overcome by reducing the load on the processor when receiving data. By enabling communication between any of the processors connected by the PCI bus, data transfer is possible between N: N, that is, between multiple processors, rather than 1: N.

1 is a diagram illustrating a configuration of an apparatus for performing data transfer between processors and a data flow in the apparatus according to the present invention.

Claims (13)

In the data transmission apparatus for performing communication between processors existing on the same system, A processor information storage device for storing characteristic information of a processor existing on the system; A buffer for storing data to be sent to the partner processor, An interrupt unit for transmitting a signal indicating that there is data to be transmitted to the counterpart processor; An interprocessor data transfer device including a Peripheral Component Interconnect (PCI) controller which transmits information of a buffer in which the data to be transmitted is stored and allows a counterpart processor to receive data stored in the buffer through direct memory access (DMA). . The apparatus of claim 1, wherein the processor characteristic information comprises a processor ID, a buffer address, and an IP. The apparatus of claim 1, wherein the processor characteristic information is notified to all processors on the system through a mailbox register. The apparatus of claim 1, wherein the buffer is a synchronous dynamic random access memory (SDRAM). The apparatus of claim 1, wherein the data is stored in the buffer through a system call. The apparatus of claim 1, wherein the PCI controller has a DMA control function. In the data transmission apparatus for performing communication between processors existing on the same system, A processor information storage device for storing characteristic information of a processor existing on the system; An interrupt unit which receives a signal indicating that there is data to be transmitted from an arbitrary processor and determines which processor is the processor using the characteristic information; And a PCI controller for acquiring information for receiving the data to be transmitted by the processor through a PCI bus through a DMA and reading the data directly from the buffer in which the data is to be transmitted through the DMA according to the information. Interprocessor data transfer device. 8. The interprocessor data transfer device of claim 7, wherein the information for receiving data through the DMA is address information of a buffer in which the data is stored. 8. The interprocessor data transfer device of claim 7, wherein the PCI controller outputs a signal informing of the completion of data reception through DMA. In the data transmission method for performing communication between processors existing on the same system, When the data to be transmitted is generated, storing the data to be transmitted in a buffer; A second step of informing a counterpart processor to transmit the data that there is data to transmit; And transmitting, to the counterpart processor, information about a buffer in which the data to be transmitted is stored through a PCI bus, and transmitting the data to the counterpart processor through a DMA. The method of claim 10, wherein the first process is performed using a system call. In the data transmission method for performing communication between processors existing on the same system, A first step of being informed of characteristic information of all processors connected through PCI existing on the system; Receiving a signal indicating that there is data to be transmitted from any processor; A third step of obtaining information about a processor to transmit the data by using the processor characteristic information; A fourth process of obtaining information on a buffer in which the data is stored from the processor through the PCI bus; And a fifth process of receiving the data through DMA using the information obtained in the fourth process. 13. The method of claim 12, further comprising a sixth step of notifying the processor when data reception through the DMA is completed.