CN115881711A - Micro LED display device and preparation method thereof - Google Patents
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Abstract
本申请公开了一种MicroLED显示器件及其制备方法,属于微显示技术领域,该MicroLED显示器件采用两次钝化的工艺,通过第一钝化层保护LED单元的侧壁,避免其产生表面态导致漏电增加;然后直接利用第一钝化层作为掩膜,无需另外设置掩膜即可在金属键合层形成孔槽,金属刻蚀后无需去除掩膜的工艺,不需要考虑去胶工艺对金属键合层的影响,因而键合金属的可选择范围更宽;在形成孔槽后,采用第二钝化层覆盖孔槽的侧壁,从而可以将侧壁暴露的键合金属覆盖,形成电学隔离,减少漏电,进而保障器件性能和可靠性。
The application discloses a Micro LED display device and a preparation method thereof, which belong to the field of micro display technology. The Micro LED display device adopts two passivation processes, and protects the side wall of the LED unit through the first passivation layer to prevent it from generating surface states. Lead to increased leakage; then directly use the first passivation layer as a mask, no additional mask can be used to form holes in the metal bonding layer, no mask removal process is required after metal etching, and there is no need to consider the impact of the deglue process on The influence of the metal bonding layer, so the optional range of the bonding metal is wider; after the hole is formed, the second passivation layer is used to cover the side wall of the hole, so that the bonding metal exposed on the side wall can be covered to form Electrical isolation reduces leakage, thereby ensuring device performance and reliability.
Description
技术领域technical field
本申请属于微显示技术领域,具体涉及一种MicroLED显示器件及其制备方法。The application belongs to the technical field of micro-display, and in particular relates to a Micro-LED display device and a preparation method thereof.
背景技术Background technique
对于应用于AR/VR领域的微型显示LED(MicroLED)来说,其像素密度要求很高,一般像素尺寸要求10um以下,甚至5um以下。为了能够获得这种像素密度的MicroLED,一般制造工艺均采用单片集成的方式来实现,即通过键合的方式(一般为金属键合),将整片外延片与CMOS驱动键合,然后再进行像素化工艺。该方法通过光刻的方式进行LEDLED单元与CMOS驱动的对准,因此精度极高。为了最大程度利用该方法的高精度,金属键合一般事先不做图形,因此,在后续像素化工艺过程中,需要将LED单元之间的金属进行刻蚀,以进行电学隔离,实现单个LED单元独立控制。For micro display LEDs (MicroLEDs) used in the AR/VR field, the pixel density requirements are very high, and the general pixel size is required to be below 10um, or even below 5um. In order to obtain Micro LEDs with this pixel density, the general manufacturing process is realized by monolithic integration, that is, the entire epitaxial wafer is bonded to the CMOS driver by bonding (usually metal bonding), and then Perform pixelation process. In this method, the alignment of the LED unit and the CMOS driver is carried out by photolithography, so the precision is extremely high. In order to maximize the high precision of this method, the metal bonding is generally not patterned in advance. Therefore, in the subsequent pixelization process, the metal between the LED units needs to be etched for electrical isolation to realize a single LED unit. independent control.
在传统的MicroLED工艺中,完成刻蚀后,一般需要去除掩膜,然后再进行后续工艺。在去除掩膜的过程中,不可避免的会对暴露出来的键合金属侧壁造成影响,接触化学物质,如金属与溶液或者气体反应,从而导致整体结构受损,影响产品性能及可靠性。In the traditional Micro LED process, after the etching is completed, the mask generally needs to be removed, and then the subsequent process is performed. In the process of removing the mask, it will inevitably affect the exposed bonding metal sidewall, contact with chemical substances, such as the reaction of metal with solution or gas, resulting in damage to the overall structure and affecting product performance and reliability.
发明内容Contents of the invention
发明目的:本申请实施例提供一种MicroLED显示器件及其制备方法,旨在克服现有MicroLED工艺在去除掩膜的过程中,不可避免的会对暴露出来的键合金属侧壁造成影响,导致整体结构受损,影响产品性能及可靠性的技术问题。Purpose of the invention: The embodiment of the present application provides a MicroLED display device and its preparation method, aiming at overcoming the unavoidable impact on the exposed bonding metal sidewall during the process of removing the mask in the existing MicroLED process, resulting in The overall structure is damaged, which affects the technical problems of product performance and reliability.
技术方案:本申请实施例所述的MicroLED显示器件的制备方法,包括:Technical solution: The preparation method of the Micro LED display device described in the embodiment of the present application includes:
提供驱动基板、金属键合层和LED单元,所述金属键合层设于所述驱动基板上,多个所述LED单元阵列排布于所述金属键合层上;Provide a driving substrate, a metal bonding layer and an LED unit, the metal bonding layer is arranged on the driving substrate, and a plurality of the LED units are arranged in an array on the metal bonding layer;
形成第一钝化层,所述第一钝化层覆盖所述LED单元;forming a first passivation layer covering the LED unit;
将所述第一钝化层图案化并以所述第一钝化层作为掩膜,在所述金属键合层上形成多个孔或槽,所述孔或槽位于相邻的所述LED单元之间,所述孔或槽的底部暴露所述驱动基板;patterning the first passivation layer and using the first passivation layer as a mask to form a plurality of holes or grooves on the metal bonding layer, the holes or grooves are located adjacent to the LED Between units, the bottom of the hole or groove exposes the drive substrate;
形成第二钝化层,所述第二钝化层覆盖所述第一钝化层并填充所述孔或槽;forming a second passivation layer covering the first passivation layer and filling the holes or slots;
刻蚀所述第一钝化层和所述第二钝化层,以至少暴露所述LED单元的出光面;Etching the first passivation layer and the second passivation layer to expose at least the light-emitting surface of the LED unit;
形成透明电极层,所述透明电极层覆盖所述出光面,并电连接所述LED单元。A transparent electrode layer is formed, and the transparent electrode layer covers the light-emitting surface and is electrically connected to the LED unit.
在一些实施例中,所述LED单元包括通过刻蚀LED外延层形成的台阶结构,所述台阶结构包括第一掺杂型半导体层、第二掺杂型半导体层和位于两者之间的有源层;所述台阶结构至少使相邻的所述LED单元的第二掺杂型半导体层彼此断开且电隔离;In some embodiments, the LED unit includes a stepped structure formed by etching the LED epitaxial layer, and the stepped structure includes a first doped semiconductor layer, a second doped semiconductor layer and an organic layer between them. source layer; the stepped structure at least disconnects and electrically isolates the second doped semiconductor layers of adjacent LED units;
所述出光面位于所述第二掺杂型半导体层上。The light emitting surface is located on the second doped semiconductor layer.
在一些实施例中,有源层具体可以为多量子阱结构,用于限制电子和空穴载流子到量子阱区域,当电子和空穴发生复合后,载流子发生辐射复合后将发射出光子,把电能转化为光能。In some embodiments, the active layer can specifically be a multi-quantum well structure, which is used to confine electron and hole carriers to the quantum well region. When the electrons and holes recombine, the carriers will be emitted after radiative recombination. Photons are emitted to convert electrical energy into light energy.
在一些实施例中,所述LED单元为微型发光二极管。In some embodiments, the LED unit is a micro light emitting diode.
在一些实施例中,所述第一掺杂型半导体层和第二掺杂型半导体层可以包括基于II-VI材料诸如ZnSe或ZnO或III-V材料诸如GaN、AlN、InN、InGaN、GaP、AlInGaP、AlGaAs及其合金的一个或多个层。In some embodiments, the first doped type semiconductor layer and the second doped type semiconductor layer may include materials based on II-VI materials such as ZnSe or ZnO or III-V materials such as GaN, AlN, InN, InGaN, GaP, One or more layers of AlInGaP, AlGaAs and their alloys.
在一些实施例中,所述LED单元的尺寸为0.1~5微米,相邻所述LED单元的间距为1~10微米。In some embodiments, the size of the LED units is 0.1-5 microns, and the distance between adjacent LED units is 1-10 microns.
在一些实施例中,所述提供驱动基板、金属键合层和LED单元,包括:In some embodiments, the providing the driving substrate, the metal bonding layer and the LED unit includes:
提供LED外延层,所述LED外延层设置于衬底上;providing an LED epitaxial layer, the LED epitaxial layer being disposed on a substrate;
在所述驱动基板和/或所述LED外延层上形成所述金属键合层,将所述驱动基板与所述LED外延层键合;forming the metal bonding layer on the driving substrate and/or the LED epitaxial layer, and bonding the driving substrate and the LED epitaxial layer;
移除所述衬底;removing the substrate;
将所述LED外延层刻蚀成所述台阶结构;etching the LED epitaxial layer into the stepped structure;
所述驱动基板包括多个第一触点,所述第一触点位于相邻的所述LED单元之间。The driving substrate includes a plurality of first contacts, and the first contacts are located between adjacent LED units.
在一些实施例中,在所述金属键合层上形成多个孔或槽时,使所述孔或槽的底部暴露所述第一触点;In some embodiments, when a plurality of holes or grooves are formed on the metal bonding layer, the bottoms of the holes or grooves expose the first contact;
刻蚀所述第一钝化层和所述第二钝化层,以暴露所述LED单元的出光面以及所述第一触点;etching the first passivation layer and the second passivation layer to expose the light-emitting surface of the LED unit and the first contact;
所述透明电极层覆盖所述出光面和所述孔或槽,以电连接所述LED单元的第二掺杂型半导体层与对应的所述第一触点,使所述LED单元通过所述第一触点单独被驱动。The transparent electrode layer covers the light-emitting surface and the hole or groove, so as to electrically connect the second doped semiconductor layer of the LED unit with the corresponding first contact, so that the LED unit passes through the The first contact is driven individually.
在一些实施例中,所述提供驱动基板、金属键合层和LED单元,包括:In some embodiments, the providing the driving substrate, the metal bonding layer and the LED unit includes:
提供LED外延层,所述LED外延层设置于衬底上;providing an LED epitaxial layer, the LED epitaxial layer being disposed on a substrate;
在所述驱动基板和/或所述LED外延层上形成所述金属键合层,将所述驱动基板与所述LED外延层键合;forming the metal bonding layer on the driving substrate and/or the LED epitaxial layer, and bonding the driving substrate and the LED epitaxial layer;
移除所述衬底;removing the substrate;
将所述LED外延层刻蚀成所述台阶结构;etching the LED epitaxial layer into the stepped structure;
所述驱动基板包括多个第一触点,所述第一触点位于所述LED单元的下方,所述金属键合层电连接所述第一触点和所述第一掺杂型半导体层。The driving substrate includes a plurality of first contacts, the first contacts are located under the LED unit, and the metal bonding layer is electrically connected to the first contacts and the first doped semiconductor layer .
在一些实施例中,在所述金属键合层上形成多个孔或槽时,使所述孔或槽间隔且电隔离相邻的所述LED单元下方的金属键合层;In some embodiments, when a plurality of holes or grooves are formed on the metal bonding layer, the holes or grooves are spaced apart and electrically isolated from the metal bonding layer below the adjacent LED units;
刻蚀所述第一钝化层和所述第二钝化层,以暴露所述LED单元的出光面;etching the first passivation layer and the second passivation layer to expose the light-emitting surface of the LED unit;
所述透明电极层覆盖相邻的所述LED单元的所述出光面,以电连接相邻所述LED单元的第二掺杂型半导体层,使所述LED单元通过所述第一触点单独被驱动。The transparent electrode layer covers the light-emitting surface of the adjacent LED unit to electrically connect the second doped semiconductor layer of the adjacent LED unit, so that the LED units are separated by the first contact driven.
在一些实施例中,形成所述第一钝化层,包括:In some embodiments, forming the first passivation layer includes:
依次采用原子层沉积和等离子体化学气相沉积介质材料,形成叠层介质层,所述叠层介质层为所述第一钝化层。The dielectric materials are sequentially deposited by atomic layer deposition and plasma chemical vapor phase to form stacked dielectric layers, and the stacked dielectric layer is the first passivation layer.
在一些实施例中,所述原子层沉积和所述等离子体化学气相沉积交替进行多次,以形成所述叠层介质层。In some embodiments, the atomic layer deposition and the plasma chemical vapor deposition are alternately performed multiple times to form the stacked dielectric layer.
在一些实施例中,所述第一钝化层的材料可选为无机介质材料和/或有机介质材料;和/或,所述无机介质材料选自SiO2、Si3N4、Al2O3中的一种或多种。In some embodiments, the material of the first passivation layer may be an inorganic dielectric material and/or an organic dielectric material; and/or, the inorganic dielectric material is selected from SiO 2 , Si 3 N 4 , Al 2 O One or more of 3 .
在一些实施例中,通过金属刻蚀工艺形成所述孔槽;In some embodiments, the holes are formed by a metal etching process;
在形成所述孔槽时,所述第一钝化层的厚度被减薄至20~300nm。When forming the holes, the thickness of the first passivation layer is reduced to 20-300 nm.
相应的,本申请实施例的MicroLED显示器件,包括:Correspondingly, the MicroLED display device of the embodiment of the present application includes:
驱动基板;drive substrate;
金属键合层,所述金属键合层设于所述驱动基板上,所述金属键合层贯穿地设有多个孔或槽,所述孔或槽的底部暴露所述驱动基板;A metal bonding layer, the metal bonding layer is provided on the driving substrate, the metal bonding layer is provided with a plurality of holes or grooves penetratingly, and the bottom of the holes or grooves exposes the driving substrate;
LED单元,多个所述LED单元阵列排布于所述金属键合层上,所述孔或槽位于相邻的所述LED单元之间;For an LED unit, a plurality of LED units are arranged in an array on the metal bonding layer, and the holes or grooves are located between adjacent LED units;
第一钝化层,所述第一钝化层覆盖所述LED单元,且暴露所述孔或槽;a first passivation layer covering the LED unit and exposing the hole or groove;
第二钝化层,所述第二钝化层覆盖所述第一钝化层并填充所述孔或槽;a second passivation layer covering the first passivation layer and filling the holes or slots;
所述第一钝化层以及所述第二钝化层至少暴露所述LED单元的出光面;The first passivation layer and the second passivation layer at least expose the light-emitting surface of the LED unit;
透明电极层,所述透明电极层覆盖所述出光面,并电连接所述LED单元。A transparent electrode layer, the transparent electrode layer covers the light-emitting surface and is electrically connected to the LED unit.
在一些实施例中,所述LED单元包括通过刻蚀LED外延层形成的台阶结构,所述台阶结构包括第一掺杂型半导体层、第二掺杂型半导体层和位于两者之间的有源层;所述台阶结构至少使相邻的所述LED单元的第二掺杂型半导体层彼此断开且电隔离;In some embodiments, the LED unit includes a stepped structure formed by etching the LED epitaxial layer, and the stepped structure includes a first doped semiconductor layer, a second doped semiconductor layer and an organic layer between them. source layer; the stepped structure at least disconnects and electrically isolates the second doped semiconductor layers of adjacent LED units;
所述出光面位于所述第二掺杂型半导体层上。The light emitting surface is located on the second doped semiconductor layer.
在一些实施例中,所述驱动基板包括多个第一触点,所述第一触点位于相邻的所述LED单元之间。In some embodiments, the driving substrate includes a plurality of first contacts, and the first contacts are located between adjacent LED units.
在一些实施例中,所述孔或槽的底部暴露所述第一触点,所述第一钝化层以及所述第二钝化层还暴露所述第一触点,所述透明电极层覆盖所述出光面和所述孔或槽,以电连接所述LED单元的第二掺杂型半导体层与对应的所述第一触点,使所述LED单元通过所述第一触点单独被驱动。In some embodiments, the bottom of the hole or groove exposes the first contact, the first passivation layer and the second passivation layer also expose the first contact, and the transparent electrode layer Covering the light-emitting surface and the hole or groove, so as to electrically connect the second doped semiconductor layer of the LED unit with the corresponding first contact, so that the LED unit can be separated through the first contact driven.
在一些实施例中,所述驱动基板包括多个第一触点,所述第一触点位于所述LED单元的下方,所述金属键合层电连接所述第一触点和所述第一掺杂型半导体层。In some embodiments, the driving substrate includes a plurality of first contacts, the first contacts are located under the LED unit, and the metal bonding layer is electrically connected to the first contacts and the first contacts. A doped semiconductor layer.
在一些实施例中,所述孔或槽间隔且电隔离相邻的所述LED单元下方的金属键合层;In some embodiments, the holes or grooves are spaced apart from and electrically isolated from the metal bonding layer below the adjacent LED units;
所述透明电极层覆盖相邻的所述LED单元的所述出光面,以电连接相邻所述LED单元的第二掺杂型半导体层,使所述LED单元通过所述第一触点单独被驱动。The transparent electrode layer covers the light-emitting surface of the adjacent LED unit to electrically connect the second doped semiconductor layer of the adjacent LED unit, so that the LED units are separated by the first contact driven.
在一些实施例中,所述第一钝化层为:依次采用原子层沉积和等离子体化学气相沉积形成的叠层介质层。In some embodiments, the first passivation layer is: a laminated dielectric layer formed by sequentially adopting atomic layer deposition and plasma chemical vapor deposition.
在一些实施例中,所述第一钝化层为:交替进行多次原子层沉积和等离子体化学气相沉积形成的叠层介质层。In some embodiments, the first passivation layer is a laminated dielectric layer formed by alternately performing multiple atomic layer deposition and plasma chemical vapor deposition.
在一些实施例中,所述第一钝化层的材料可选为无机介质材料和/或有机介质材料;和/或,所述无机介质材料选自SiO2、Si3N4、Al2O3中的一种或多种。In some embodiments, the material of the first passivation layer may be an inorganic dielectric material and/or an organic dielectric material; and/or, the inorganic dielectric material is selected from SiO 2 , Si 3 N 4 , Al 2 O One or more of 3 .
在一些实施例中,所述第一钝化层的厚度为20~300mm。In some embodiments, the thickness of the first passivation layer is 20-300 mm.
有益效果:与现有技术相比,本申请实施例的MicroLED显示器件的制备方法,包括:提供驱动基板、金属键合层和LED单元,金属键合层设于驱动基板上,多个LED单元阵列排布于金属键合层上;形成第一钝化层,第一钝化层覆盖LED单元;将第一钝化层图案化并以第一钝化层作为掩膜,在金属键合层上形成多个孔或槽,孔或槽位于相邻的LED单元之间,孔或槽的底部暴露驱动基板;形成第二钝化层,第二钝化层覆盖第一钝化层并填充孔或槽;刻蚀第一钝化层和第二钝化层,以至少暴露LED单元的出光面;形成透明电极层,透明电极层覆盖出光面,并电连接LED单元。本申请采用两次钝化的工艺,通过第一钝化层保护LED单元的侧壁,避免其产生表面态导致漏电增加;然后直接利用第一钝化层作为掩膜,无需另外设置掩膜即可在金属键合层形成孔槽,金属刻蚀后无需去除掩膜的工艺,不需要考虑去胶工艺对金属键合层的影响,因而键合金属的可选择范围更宽;在形成孔槽后,采用第二钝化层覆盖孔槽的侧壁,从而可以将侧壁暴露的键合金属覆盖,形成电学隔离,减少漏电,进而保障器件性能和可靠性。Beneficial effects: Compared with the prior art, the preparation method of the Micro LED display device according to the embodiment of the present application includes: providing a driving substrate, a metal bonding layer and an LED unit, the metal bonding layer is provided on the driving substrate, and a plurality of LED units The array is arranged on the metal bonding layer; the first passivation layer is formed, and the first passivation layer covers the LED unit; the first passivation layer is patterned and the first passivation layer is used as a mask, and the metal bonding layer A plurality of holes or grooves are formed on the surface, the holes or grooves are located between adjacent LED units, and the bottom of the holes or grooves exposes the driving substrate; a second passivation layer is formed, and the second passivation layer covers the first passivation layer and fills the holes or groove; etch the first passivation layer and the second passivation layer to at least expose the light-emitting surface of the LED unit; form a transparent electrode layer, the transparent electrode layer covers the light-emitting surface, and electrically connects the LED unit. This application adopts two passivation processes to protect the side wall of the LED unit through the first passivation layer to avoid the increase of leakage caused by the surface state; and then directly use the first passivation layer as a mask without additional mask Grooves can be formed in the metal bonding layer, and there is no need to remove the mask after metal etching, and there is no need to consider the influence of the deglue process on the metal bonding layer, so the optional range of bonding metals is wider; Finally, the second passivation layer is used to cover the sidewall of the hole, so that the exposed bonding metal on the sidewall can be covered to form electrical isolation and reduce leakage, thereby ensuring device performance and reliability.
与现有技术相比,本申请实施例的MicroLED显示器件,包括:驱动基板;金属键合层,金属键合层设于驱动基板上,金属键合层贯穿地设有多个孔或槽,孔或槽的底部暴露驱动基板;LED单元,多个LED单元阵列排布于金属键合层上,孔或槽位于相邻的LED单元之间;第一钝化层,第一钝化层覆盖LED单元,且暴露LED单元的出光面和孔或槽;第二钝化层,第二钝化层覆盖第一钝化层并填充孔或槽;透明电极层,透明电极层覆盖出光面,并电连接LED单元。该显示器件通过第一钝化层保护LED单元的侧壁,通过第二钝化层保护键合金属,使之不会受到工艺的影响,减少漏电,进而保障器件性能和可靠性。Compared with the prior art, the Micro LED display device of the embodiment of the present application includes: a driving substrate; a metal bonding layer, the metal bonding layer is provided on the driving substrate, and the metal bonding layer is provided with a plurality of holes or grooves penetratingly, The drive substrate is exposed at the bottom of the hole or groove; LED unit, a plurality of LED unit arrays are arranged on the metal bonding layer, the hole or groove is located between adjacent LED units; the first passivation layer, the first passivation layer covers LED unit, and expose the light-emitting surface of the LED unit and the hole or groove; the second passivation layer, the second passivation layer covers the first passivation layer and fills the hole or groove; the transparent electrode layer, the transparent electrode layer covers the light-emitting surface, and Electrically connect the LED unit. The display device protects the side wall of the LED unit through the first passivation layer, and protects the bonding metal through the second passivation layer, so that it will not be affected by the process, reduce leakage, and thus ensure device performance and reliability.
附图说明Description of drawings
为了更清楚地说明本申请实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.
图1是本申请第一实施例中MicroLED显示器件的俯视图;FIG. 1 is a top view of the MicroLED display device in the first embodiment of the present application;
图2是本申请第一实施例中MicroLED显示器件的沿A-A线剖面的示意图;Fig. 2 is a schematic diagram of a section along line A-A of the Micro LED display device in the first embodiment of the present application;
图3是本申请第一实施例中驱动基板和LED外延层的剖面示意图;3 is a schematic cross-sectional view of the driving substrate and the LED epitaxial layer in the first embodiment of the present application;
图4是本申请第一实施例中形成金属键合层的剖面示意图;4 is a schematic cross-sectional view of forming a metal bonding layer in the first embodiment of the present application;
图5是本申请第一实施例中键合过程的剖面示意图;5 is a schematic cross-sectional view of the bonding process in the first embodiment of the present application;
图6是本申请第一实施例中形成LED单元的剖面示意图;6 is a schematic cross-sectional view of forming an LED unit in the first embodiment of the present application;
图7是本申请第一实施例中形成LED单元的俯视示意图;7 is a schematic top view of forming an LED unit in the first embodiment of the present application;
图8是本申请第一实施例中形成第一钝化层的剖视示意图;8 is a schematic cross-sectional view of forming a first passivation layer in the first embodiment of the present application;
图9是本申请第一实施例中形成第一钝化层的俯视示意图;9 is a schematic top view of forming a first passivation layer in the first embodiment of the present application;
图10是本申请第一实施例中对第一钝化层图案化形成掩膜的剖视示意图;10 is a schematic cross-sectional view of forming a mask by patterning the first passivation layer in the first embodiment of the present application;
图11是图8所示状态至图10所示状态的俯视示意图;Fig. 11 is a schematic top view from the state shown in Fig. 8 to the state shown in Fig. 10;
图12是本申请第一实施例中在金属键合层形成孔槽的剖视示意图;12 is a schematic cross-sectional view of holes formed in the metal bonding layer in the first embodiment of the present application;
图13是图10所示状态至图12所示状态的俯视示意图;Fig. 13 is a schematic top view from the state shown in Fig. 10 to the state shown in Fig. 12;
图14是本申请第一实施例中形成第二钝化层的剖视示意图;14 is a schematic cross-sectional view of forming a second passivation layer in the first embodiment of the present application;
图15是图12所示状态至图14所示状态的俯视示意图;Fig. 15 is a schematic top view from the state shown in Fig. 12 to the state shown in Fig. 14;
图16是本申请第一实施例中刻蚀第一钝化层和第二钝化层后的剖视示意图;16 is a schematic cross-sectional view after etching the first passivation layer and the second passivation layer in the first embodiment of the present application;
图17是图14所示状态至图16所示状态的俯视示意图;Fig. 17 is a schematic top view from the state shown in Fig. 14 to the state shown in Fig. 16;
图18是图16所示状态至图1所示状态的俯视示意图;Fig. 18 is a schematic top view from the state shown in Fig. 16 to the state shown in Fig. 1;
图19是本申请第二实施例中MicroLED显示器件的剖面示意图;FIG. 19 is a schematic cross-sectional view of a MicroLED display device in the second embodiment of the present application;
图20是本申请第二实施例中对第一钝化层图案化形成掩膜的剖视示意图;20 is a schematic cross-sectional view of forming a mask by patterning the first passivation layer in the second embodiment of the present application;
图21是本申请第二实施例中对第一钝化层图案化形成掩膜的俯视示意图;FIG. 21 is a schematic top view of forming a mask by patterning the first passivation layer in the second embodiment of the present application;
图22是本申请第二实施例中在金属键合层形成孔槽的剖视示意图;22 is a schematic cross-sectional view of forming holes in the metal bonding layer in the second embodiment of the present application;
图23是图20所示状态至图22所示状态的俯视示意图;Fig. 23 is a schematic top view from the state shown in Fig. 20 to the state shown in Fig. 22;
图24是本申请第二实施例中形成第二钝化层的剖视示意图;24 is a schematic cross-sectional view of forming a second passivation layer in the second embodiment of the present application;
图25是本申请第二实施例中刻蚀第一钝化层和第二钝化层后的剖视示意图;25 is a schematic cross-sectional view after etching the first passivation layer and the second passivation layer in the second embodiment of the present application;
图26是图24所示状态至图25所示状态的俯视示意图;Fig. 26 is a schematic top view from the state shown in Fig. 24 to the state shown in Fig. 25;
附图标记:10-驱动基板;100-第一触点;20-LED外延层;200-LED单元;210-第一掺杂型半导体层;220-有源层;230-第二掺杂型半导体层;201-出光面;30-衬底;300-金属键合层;310-孔或槽;400-第一钝化层;410-第一通孔;500-第二钝化层;510-第二通孔;520-第三通孔;600-透明电极层。Reference signs: 10-drive substrate; 100-first contact; 20-LED epitaxial layer; 200-LED unit; 210-first doped semiconductor layer; 220-active layer; 230-second doped type Semiconductor layer; 201-light-emitting surface; 30-substrate; 300-metal bonding layer; 310-hole or groove; 400-first passivation layer; 410-first through hole; 500-second passivation layer; 510 - second through hole; 520 - third through hole; 600 - transparent electrode layer.
具体实施方式Detailed ways
下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述。显然,所描述的实施例仅仅是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Apparently, the described embodiments are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of this application.
在本申请的描述中,需要理解的是,需要特别说明,在本申请的描述中,术语“在…上”、“在…之上”、“在…上面”、“在…上方”的含义应该以最广义的方式解释,意味着包含这些术语的描述解释为“部件可以以直接接触的方式设置在另一部件上,也可以在部件与部件之间存在中间部件或层”。In the description of the present application, it should be understood that special explanation is required. In the description of the present application, the meanings of the terms "on", "on", "on", "above" It should be interpreted in the broadest manner, meaning that descriptions containing these terms are interpreted as "a component may be disposed on another component in direct contact, or there may be an intervening component or layer between components".
此外,为了便于描述,本申请还可能使用诸如“在…下”、“在…下方”、“在…之下”、“在…上”、“在…之上”、“在…上方”、“下部”、“上部”等空间相对术语来描述一个元件或部件与附图中所示的另一元件或部件的关系。除了在图中描述的方位之外,空间相对术语还意图涵盖装置在使用或操作中的不同方位。设备可以以其他方式定向(旋转90°或以其他定向),并且在本申请中使用的空间相对描述语可以被同样地相应地解释。In addition, for the convenience of description, the application may also use words such as "below", "below", "below", "on", "on", "above", Spatially relative terms such as "lower" and "upper" describe the relationship of one element or component to another element or component shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90° or at other orientations) and the spatially relative descriptors used in this application interpreted accordingly.
本申请中所使用的术语“层”是指包括具有一定厚度的区域的材料部分。层可以在整个下层或上层结构上延伸,或者可以在下层或上层结构的局部范围延伸。此外,层可以是均质或不均质连续结构的区域,其厚度小于连续结构的厚度。例如,层可以位于连续结构的顶表面和底表面之间或在其之间的任何一对水平平面之间。层可以水平地、垂直地和/或沿着锥形表面延伸。一层可以包括多层。例如,半导体层可以包括一个或多个掺杂或未掺杂的半导体层,并且可以具有相同或不同的材料。The term "layer" as used in this application refers to a portion of material comprising regions having a certain thickness. A layer may extend over the entire underlying or superstructure, or may extend over a localized extent of the underlying or superstructure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes therebetween. Layers may extend horizontally, vertically and/or along the tapered surface. A layer can include multiple layers. For example, a semiconductor layer may comprise one or more doped or undoped semiconductor layers, and may be of the same or different materials.
本申请的描述中,使用的“微型”LED、“微型”装置是指根据本申请的实施方式的某些装置或结构的描述性尺寸。本文中使用的术语“微型”装置或结构旨在表示100纳米至100微米的规模。然而,应明白,本发明的实施方式不一定限于此,并且实施方式的某些方面可以适用于更大的以及可能更小的尺寸规模。In the description of the present application, the use of "micro" LED, "micro" device refers to the descriptive dimensions of certain devices or structures according to embodiments of the present application. As used herein, the term "micro" device or structure is intended to mean a scale of 100 nanometers to 100 microns. It should be understood, however, that embodiments of the invention are not necessarily so limited, and that certain aspects of the embodiments may be adapted to larger and possibly smaller scales.
申请人注意到,在传统的MicroLED工艺中,一般采用光刻胶或者介质层为掩膜,使用反应离子刻蚀(Reactive ion etching简称RIE)、电感耦合等离子体(InductivelyCoupled Plasma简称ICP)刻蚀或者离子束刻蚀(Ion beam etching简称IBE)等方式来刻蚀金属。因为键合金属一般由多层材料组成,优选的刻蚀方式,是采用一种对各层金属刻蚀速率差异不大的方法来进行,其中IBE使用较多。在这些刻蚀工艺中,一般先完成半导体材料刻蚀,然后完成金属隔离刻蚀后,完成刻蚀后,一般需要去除掩膜,然后再进行介质层沉积,既对半导体侧壁进行钝化,也使刻蚀金属侧壁得到包裹,形成电学隔离。常用的去胶液会跟某些金属进行反应,因此,去除掩膜过程中会对金属键合层产生影响,导致键合金属的可选择范围变窄,不利于获得最佳性能;而采用氧气等离子去胶的方式,也会导致键合金属与氧气发生反应,使之性能发生一定变化。The applicant noticed that in the traditional Micro LED process, photoresist or dielectric layer is generally used as a mask, and reactive ion etching (RIE for short), Inductively Coupled Plasma (ICP for short) etching or Ion beam etching (IBE for short) and other methods are used to etch the metal. Because the bonding metal is generally composed of multiple layers of materials, the preferred etching method is to use a method with little difference in the etching rate of each layer of metal, among which IBE is used more. In these etching processes, the semiconductor material etching is generally completed first, and then the metal isolation etching is completed. After the etching is completed, the mask generally needs to be removed, and then the dielectric layer is deposited to passivate the semiconductor sidewall. It also wraps the etched metal sidewall to form electrical isolation. The commonly used glue remover will react with some metals, therefore, the process of removing the mask will affect the metal bonding layer, resulting in a narrower selection of bonding metals, which is not conducive to obtaining the best performance; and using oxygen The way of plasma degumming will also cause the bonding metal to react with oxygen, causing certain changes in its performance.
有鉴于此,本申请实施例提供一种MicroLED显示器件及其制备方法,以克服上述缺陷的至少一者。In view of this, embodiments of the present application provide a Micro LED display device and a manufacturing method thereof, so as to overcome at least one of the above-mentioned defects.
本申请实施例描述了MicroLED显示器件以及用于制备该器件的方法。本申请的MicroLED显示器件使用Micro-LED(Micro light-emitting diode,微型发光二极管结构),微型发光二极管的尺寸缩小到100纳米至100微米。在Micro-LED中,Micro-LED阵列高度集成,阵列中的Micro-LED的LED单元的距离进一步缩小至5微米量级。Micro-LED的显示方式是将5微米尺寸甚至更小尺寸的Micro-LED连接到驱动基板上,实现对每个Micro-LED放光亮度的精确控制。本申请实施例的制备方法,适用于Micro-LED结构,实现在微小尺寸MicroLED显示器件的制备。The embodiment of the present application describes a Micro LED display device and a method for preparing the device. The Micro LED display device of the present application uses Micro-LED (Micro light-emitting diode, micro-light-emitting diode structure), and the size of the micro-light-emitting diode is reduced to 100 nanometers to 100 micrometers. In Micro-LED, the Micro-LED array is highly integrated, and the distance between the LED units of the Micro-LED in the array is further reduced to the order of 5 microns. The display method of Micro-LED is to connect Micro-LEDs with a size of 5 microns or even smaller to the driving substrate to achieve precise control of the brightness of each Micro-LED. The preparation method of the embodiment of the present application is applicable to the Micro-LED structure to realize the preparation of micro-sized Micro LED display devices.
具体的,请参阅图1、图2以及图19所示,本申请实施例的MicroLED显示器件包括驱动基板10、金属键合层300、LED单元200、第一钝化层400、第二钝化层500以及透明电极层600。其中,金属键合层300设于驱动基板10上,金属键合层300贯穿地设有多个孔或槽,孔或槽的底部暴露驱动基板10;多个LED单元200阵列排布于金属键合层300上,孔或槽位于相邻的LED单元200之间;第一钝化层400覆盖LED单元200,且暴露LED单元200的出光面201和孔或槽;第二钝化层500覆盖第一钝化层400并填充孔或槽;透明电极层600覆盖出光面201,并电连接LED单元200。Specifically, please refer to FIG. 1, FIG. 2 and FIG. 19, the Micro LED display device of the embodiment of the present application includes a driving
可以理解的是,该MicroLED显示器件通过第一钝化层400保护LED单元200的侧壁,通过第二钝化层500保护金属键合层300,使之不会受到工艺的影响,减少漏电,进而能够保障器件性能和可靠性。It can be understood that the Micro LED display device protects the sidewall of the
在一些实施例中,驱动基板10可以包括半导体材料,诸如硅、碳化硅、氮化家、锗、砷化镓、磷化钴。在一些实施例中,驱动基板10可以由非导电材料制成,诸如玻璃、塑料或蓝宝石晶片。在一些实施例中,驱动基板10可以具有在其中形成的驱动电路,并且驱动基板10可以是CMOS(Complementary Metal Oxide Semiconductor,互补金属氧化物半导体)背板或TFT玻璃基板。驱动电路将电信号提供给LED单元200以控制亮度。在一些实施例中,驱动电路可以包括有源矩阵驱动电路,其中,每个单独的LED单元200都相应于独立的驱动器。In some embodiments, the driving
在一些实施例中,LED单元200包括通过刻蚀LED外延层20形成的台阶结构,台阶结构包括第一掺杂型半导体层210、第二掺杂型半导体层230和位于两者之间的有源层220;台阶结构至少使相邻的LED单元200的第二掺杂型半导体层230彼此断开且电隔离;出光面201位于第二掺杂型半导体层230上,具体的出光面201可位于台阶结构的顶端。In some embodiments, the
请参阅图6和图20,第一掺杂型半导体层210设置于金属键合层300上,有源层220设置于第一掺杂型半导体层210背离金属键合层300的一侧,第二掺杂型半导体层230设置于有源层220背离第一掺杂型半导体层210的一侧。6 and 20, the first doped
在一些实施例中,驱动基板10包括多个第一触点100,第一触点100位于相邻的LED单元200之间。In some embodiments, the driving
在一些实施例中,孔或槽具体为孔310,孔310的底部暴露第一触点100,透明电极层600覆盖出光面201和孔310,以电连接LED单元200的第二掺杂型半导体层230与对应的第一触点100,使LED单元200通过第一触点100单独被驱动。In some embodiments, the hole or groove is specifically a
在一些实施例中,相邻LED单元200的第一掺杂型半导体层210彼此断开且电隔离;第一触点100位于LED单元200的下方,金属键合层300电连接第一触点100和第一掺杂型半导体层210。In some embodiments, the first doped
在一些实施例中,孔或槽具体为槽310,槽310间隔且电隔离相邻的LED单元200下方的金属键合层300;透明电极层600覆盖相邻的LED单元200的出光面201和驱动基板10的公共触点,以电连接相邻LED单元200的第二掺杂型半导体层230,使LED单元200通过第一触点100单独被驱动。In some embodiments, the holes or grooves are specifically
具体的,请再次参阅图1和图2,在本申请的第一实施例中,驱动基板10包括多个第一触点100,多个第一触点100阵列排布,且第一触点100位于相邻的LED单元200之间。Specifically, please refer to FIG. 1 and FIG. 2 again. In the first embodiment of the present application, the driving
金属键合层300设于驱动基板10上,用于将LED外延层20键合至驱动基板10上,并且用于电连接各LED单元200的第一掺杂型半导体层210。金属键合层300的键合金属包括Au、Sn、In、Cu或Ti。The
请一并参阅图12和图13,在金属键合层300贯穿地设有多个孔310,多个孔310阵列排布,且孔310位于相邻的LED单元200之间且相对第一触点100设置,孔310的底部暴露驱动基板10并露出对应的第一触点100。在第一实施例中,孔310可以为圆形孔,金属键合层300在孔310处被贯穿,露出侧壁。Please refer to FIG. 12 and FIG. 13 together. A plurality of
多个LED单元200阵列排布于金属键合层300上,以通过金属键合层300与驱动基板10连接成一体,各LED单元200的第一掺杂型半导体层210通过金属键合层300实现相互电连接。A plurality of
第一钝化层400覆盖LED单元200,且第一钝化层400暴露LED单元200的出光面201和孔310,也就是说第一钝化层400至少覆盖LED单元200的侧壁,以对LED单元200的侧壁进行保护,避免其在制备过程中形成表面态。The
第二钝化层500覆盖第一钝化层400和孔310的侧壁,以对金属键合层300刻蚀形成的侧壁进行保护,避免其整体结构受损,进而保证产品的性能和稳定性。The
透明电极层600覆盖出光面201和孔或槽,以电连接LED单元200和驱动基板10的相对应的第一触点100,以使LED单元200通过第一触点100单独被驱动。The
具体的,请参阅图19,在本申请的第二实施例中,驱动基板10包括多个第一触点100,多个第一触点100阵列排布,且第一触点100位于LED单元200的下方,与LED单元200相对设置;另外,驱动基板10还可以包括公共触点(图中未示出),公共触点靠近驱动基板10的边缘设置。Specifically, please refer to FIG. 19. In the second embodiment of the present application, the driving
金属键合层300设于驱动基板10上,用于将LED外延层20键合至驱动基板10上,并且用于电连接LED单元200的第一掺杂型半导体层210和第一触点100。金属键合层300的键合金属包括Au、Sn、In、Cu或Ti。The
请一并参阅图22和图23,在金属键合层300贯穿地设有槽310,槽310可以设置多个,多个槽310阵列排布,且间隔于相邻的LED单元200之间,槽310的底部暴露驱动基板10,槽310也可以为一个通槽。在第二实施例中,槽310为在金属键合层300厚度方向贯穿的沟槽,槽310在金属键合层300上形成间隙,将金属键合层300分隔成阵列排布的多个金属键合部,金属键合部一一对应地设置于LED单元200的下方,相邻金属键合部通过槽310间隔设置。Please refer to FIG. 22 and FIG. 23 together. There are
在第二实施例中,多个LED单元200阵列排布于金属键合层300上,以通过金属键合层300与驱动基板10连接成一体,各LED单元200的第一掺杂型半导体层210通过金属键合层300分隔形成的金属键合部,实现与第一触点100相互电连接。In the second embodiment, a plurality of
第一钝化层400覆盖LED单元200,且第一钝化层400暴露LED单元200的出光面201和槽310,也就是说第一钝化层400至少覆盖LED单元200的侧壁,以对LED单元200的侧壁进行保护,避免其在制备过程中形成表面态。The
第二钝化层500覆盖第一钝化层400和槽310的侧壁,以对金属键合层300刻蚀形成的侧壁进行保护,避免其整体结构受损,进而保证产品的性能和稳定性。The
透明电极层600覆盖各LED单元的出光面201,以电连接各LED单元200的第二掺杂型半导体层230,并且可以将第二掺杂型半导体层230与驱动基板10的公共触点电连接,以使LED单元200通过第一触点100单独被驱动。The
在一些实施例中,第一钝化层400为:依次采用原子层沉积和等离子体化学气相沉积形成的叠层介质层。In some embodiments, the
具体而言,第一钝化层400的材料可选为SiO2,Si3N4,Al2O3等无机介质材料,或者其他可行的有机介质材料。因为介质材料也会同时被离子束刻蚀,因此,介质材料的厚度应该大于在刻蚀工艺中被刻蚀掉的厚度。刻蚀完成后,介质层厚度也即第一钝化层400的厚度剩余20-300nm为佳。在本实施例中,采用原子层沉积(ALD)形成的介质层的致密性非常高,不容易被刻蚀,能够对LED单元200的侧壁形成更好的钝化效果,而采用等离子体化学气相沉积(PECVD)能够对介质层增厚,所形成的叠层介质层能够使最终留下来的介质层,停刻在ALD介质层,使得产品的一致性大幅提升,满足第一钝化层400的厚度要求。Specifically, the material of the
进一步的,在一些实施例中,第一钝化层400为:交替进行多次原子层沉积和等离子体化学气相沉积形成的叠层介质层。例如,可以交替的进行ALD/PECVD/ALD/PECVD的沉积过程,形成符合要求的第一钝化层400。Further, in some embodiments, the
相应的,本申请实施例还提供一种MicroLED显示器件的制备方法,其特征包括:Correspondingly, the embodiment of the present application also provides a method for manufacturing a Micro LED display device, the features of which include:
提供驱动基板10、金属键合层300和LED单元200,金属键合层300设于驱动基板10上,多个LED单元200阵列排布于金属键合层300上;Provide a driving
形成第一钝化层400,第一钝化层400覆盖LED单元200;forming a
将第一钝化层400图案化并以第一钝化层400作为掩膜,在金属键合层300上形成多个孔或槽,孔或槽位于相邻的LED单元200之间,孔或槽的底部暴露驱动基板10;Pattern the
形成第二钝化层500,第二钝化层500覆盖第一钝化层400和孔或槽的侧壁;forming a
刻蚀第一钝化层400和第二钝化层500,以至少暴露LED单元200的出光面201;Etching the
形成透明电极层600,透明电极层600覆盖出光面201,并电连接LED单元200。A
可以理解的是,该制备方法采用两次钝化的工艺,通过第一钝化层400保护LED单元200的侧壁,避免其产生表面态导致漏电增加;然后直接利用第一钝化层400作为掩膜,无需另外设置掩膜即可在金属键合层300形成孔或槽,金属刻蚀后无需去除掩膜的工艺,不需要考虑去胶工艺对金属键合层300的影响,因而键合金属的可选择范围更宽;在形成孔或槽后,采用第二钝化层500覆盖孔或槽的侧壁,从而可以将侧壁暴露的键合金属覆盖,形成电学隔离,减少漏电,进而保障器件性能和可靠性。It can be understood that the preparation method adopts two passivation processes, and protects the sidewall of the
具体的,LED单元200包括通过刻蚀LED外延层20形成的台阶结构,台阶结构包括第一掺杂型半导体层210、第二掺杂型半导体层230和位于两者之间的有源层220;台阶结构至少使相邻的LED单元200的第二掺杂型半导体层230彼此断开且电隔离;出光面201位于第二掺杂型半导体层230上,具体的出光面201位于台阶结构的顶端。Specifically, the
在第一实施例中,请参阅图3,提供驱动基板10、金属键合层300和LED单元200,包括:提供LED外延层20,LED外延层20设置于衬底30上;其中,衬底30是半导体材料,如硅、GaN、SiC等,或者衬底30是非导电材料,如蓝宝石或玻璃;LED外延层一般包括N型掺杂层,P型掺杂层,以及多量子阱层。In the first embodiment, referring to FIG. 3 , a driving
请参阅图4,在驱动基板10和LED外延层20上分别形成金属键合层300,将驱动基板10与LED外延层20键合,露出衬底30。Referring to FIG. 4 , metal bonding layers 300 are respectively formed on the driving
请参阅图5,可以通过干法或者湿法移除键合后晶圆的衬底30。Referring to FIG. 5 , the
请参阅图6和图7,可以通过干法或者湿法,对LED外延层20进行刻蚀,形成台阶结构,即刻蚀出阵列排布的多个LED单元200,LED单元200阵列排布于金属键合层300上,从而,相邻LED单元200的第一掺杂型半导体层210通过金属键合层300彼此电连接;其中,驱动基板10的第一触点100位于相邻的LED单元200之间。Please refer to FIG. 6 and FIG. 7, the
进一步的,请参阅图8和图9所示,采用无机或者有机介质材料,对LED单元200的侧壁进行第一次钝化,形成第一钝化层400,此时第一钝化层400的厚度大于刻蚀金属键合层300后第一钝化层400的厚度,为了匹配后续金属刻蚀工艺,可以对第一钝化层400的材料和厚度进行设计。Further, as shown in FIG. 8 and FIG. 9, the sidewall of the
具体的,第一钝化层400的材料可以选为SiO2,Si3N4,Al2O3等无机介质材料,或者其他可行的有机介质材料,例如,可以为聚酰亚胺、SU-8光刻胶或其他可光图案化的聚合物。常规沉积介质层的方式有等离子体化学气相沉积(PECVD)以及原子层沉积(ALD)等,采用ALD方式沉积的介质层,其致密性非常高,不容易被刻蚀,因此,第一次钝化的材料,可采用多层介质层的结构,比如先用ALD沉积一层介质层(ALD沉积的介质层对于半导体侧壁钝化效果更好),然后用PECVD沉积一层增厚的介质层。当然,也可以多用几对介质层对,作为第一层钝化层,如ALD/PECVD/ALD/PECVD,等等。因为ALD介质层刻蚀速率慢,因此,通过叠层介质层的设计,可以使最终留下来的介质层,停刻在ALD介质层,使得产品的一致性大幅提升。Specifically, the material of the
请参阅图10和图11所示,对第一钝化层400进行图案化,形成贯穿第一钝化层400且阵列排布的多个第一通孔410,第一通孔410相对于第一触点100设置于其上方。10 and 11, the
请参阅图12和图13所示,以第一钝化层400作为掩膜,将金属键合层300刻穿至驱动基板10的表面介质层,形成阵列排布的孔310,孔310的底部露出第一触点100。金属刻蚀工艺可选用常规的离子束刻蚀,或者电感耦合等离子体刻蚀及反应离子刻蚀。在形成孔310过程中,第一钝化层400的厚度被减薄至20~300nm。Please refer to FIG. 12 and FIG. 13 , using the
请参阅图14和图15所示,金属键合层300刻蚀完成后,无需去除掩膜的工艺,直接进行第二次钝化,采用无机或有机介电材料,将孔310暴露的键合金属侧壁覆盖,形成第二钝化层500,对孔310的侧壁进行电学隔离,以免后续金属走线发生短路等情况,同时将反应活性高的金属保护起来,提升后续工艺兼容性。Please refer to FIG. 14 and FIG. 15. After the
请参阅图16和图17所示,将台阶结构的上方以及驱动基板10的第一触点100的介质层进行开孔刻蚀,即刻蚀第一钝化层400和第二钝化层500,形成第二通孔510和第三通孔520,使第二通孔510暴露出第一触点100,第三通孔520暴露出LED单元200的出光面201。Please refer to FIG. 16 and FIG. 17 , the upper part of the step structure and the dielectric layer of the
请参阅图2和图18,沉积透明电极层600,透明电极层600覆盖出光面201和孔310,以电连接LED单元200的第二掺杂型半导体层230与对应的第一触点100,使LED单元200通过第一触点100单独被驱动。其中,透明电极层600采用透明材料,例如可以为ITO。Referring to FIG. 2 and FIG. 18, a
请参阅图19,与第一实施例有所不同,在第二实施例中,提供的驱动基板10的第一触点100位于LED单元200的下方,第一触点100通过金属键合层300和LED单元200的第一掺杂型半导体层210电连接。Please refer to FIG. 19 , different from the first embodiment, in the second embodiment, the
采用无机或者有机介质材料,对LED单元200的侧壁进行第一次钝化,形成第一钝化层400,此时第一钝化层400的厚度大于刻蚀金属键合层300后第一钝化层400的厚度,为了匹配后续金属刻蚀工艺,可以对第一钝化层400的材料和厚度进行设计。Use inorganic or organic dielectric materials to passivate the sidewall of the
具体的,第一钝化层400的材料可以选为SiO2,Si3N4,Al2O3等无机介质材料,或者其他可行的有机介质材料,例如,可以为聚酰亚胺、SU-8光刻胶或其他可光图案化的聚合物。常规沉积介质层的方式有等离子体化学气相沉积(PECVD)以及原子层沉积(ALD)等,采用ALD方式沉积的介质层,其致密性非常高,不容易被刻蚀,因此,第一次钝化的材料,可采用多层介质层的结构,比如先用ALD沉积一层介质层(ALD沉积的介质层对于半导体侧壁钝化效果更好),然后用PECVD沉积一层增厚的介质层。当然,也可以多用几对介质层对,作为第一层钝化层,如ALD/PECVD/ALD/PECVD,等等。因为ALD介质层刻蚀速率慢,因此,通过叠层介质层的设计,可以使最终留下来的介质层,停刻在ALD介质层,使得产品的一致性大幅提升。Specifically, the material of the
进一步的,请参阅图20和图21所示,对第一钝化层400进行图案化,形成贯穿第一钝化层400且阵列排布的多个第一通孔410,在第二实施例中,第一通孔410为通槽结构,该通槽结构间隔相邻的LED单元200上方覆盖的第一钝化层400。Further, as shown in FIG. 20 and FIG. 21, the
请参阅图22和图23所示,以第一钝化层400作为掩膜,将金属键合层300刻穿至驱动基板10的表面介质层,形成阵列排布的槽310。金属刻蚀工艺可选用常规的离子束刻蚀,或者电感耦合等离子体刻蚀及反应离子刻蚀。槽310位于相邻的LED单元200之间,槽310的底部暴露驱动基板10。具体的,槽310为在金属键合层300厚度方向贯穿的沟槽,槽310在金属键合层300上形成间隙,将金属键合层300分隔成阵列排布的多个金属键合部,金属键合部一一对应地设置于LED单元200的下方,相邻金属键合部通过槽310间隔设置。在形成槽310过程中,第一钝化层400的厚度被减薄至20~300nm。Referring to FIG. 22 and FIG. 23 , using the
请参阅图24所示,金属键合层300刻蚀完成后,无需去除掩膜的工艺,直接进行第二次钝化,采用无机或有机介电材料,将槽310暴露的键合金属侧壁覆盖,形成第二钝化层500,对槽310的侧壁进行电学隔离,以免后续金属走线发生短路等情况,同时将反应活性高的金属保护起来,提升后续工艺兼容性。Please refer to FIG. 24 , after the etching of the
请参阅图25和图26所示,将台阶结构的上方以及驱动基板10的公共触点的介质层进行开孔刻蚀,即刻蚀第一钝化层400和第二钝化层500,形成第三通孔520,第三通孔520暴露出LED单元200的出光面201。Please refer to FIG. 25 and FIG. 26, the upper part of the step structure and the dielectric layer of the common contact of the driving
请再次参阅图19,沉积透明电极层600,透明电极层600覆盖各LED单元200的出光面201,以电连接各LED单元200的第二掺杂型半导体层230,并进一步将第二掺杂型半导体层230与驱动基板10的公共触点连接,使LED单元200通过第一触点100单独被驱动。其中,透明电极层600采用透明材料,例如可以为ITO。Please refer to FIG. 19 again, deposit a
在上述实施例中,对各个实施例的描述都各有侧重,某个实施例中没有详述的部分,可以参见其他实施例的相关描述。In the foregoing embodiments, the descriptions of each embodiment have their own emphases, and for parts not described in detail in a certain embodiment, reference may be made to relevant descriptions of other embodiments.
以上对本申请实施例所提供的MicroLED显示器件及其制备方法进行了详细介绍,并应用了具体个例对本申请的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想;本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。The Micro LED display device and its preparation method provided by the embodiments of the present application have been introduced in detail above, and the principles and implementation methods of the present application have been explained by using specific examples. The descriptions of the above embodiments are only used to help understand the present application. Technical solutions and their core ideas; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not The essence of the corresponding technical solutions deviates from the scope of the technical solutions of the embodiments of the present application.
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Application Number | Priority Date | Filing Date | Title |
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CN202211608392.0A CN115881711A (en) | 2022-12-14 | 2022-12-14 | Micro LED display device and preparation method thereof |
PCT/CN2023/130412 WO2024125166A1 (en) | 2022-12-14 | 2023-11-08 | Microled display device and manufacturing method therefor |
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CN117393682A (en) * | 2023-12-13 | 2024-01-12 | 晶能光电股份有限公司 | Microdisplay device, microdisplay array structure and preparation method thereof |
WO2024125166A1 (en) * | 2022-12-14 | 2024-06-20 | 镭昱光电科技(苏州)有限公司 | Microled display device and manufacturing method therefor |
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CN118943158B (en) * | 2024-07-23 | 2025-02-18 | 盐城鸿石智能科技有限公司 | Micro LED display chip and preparation method thereof |
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US11569415B2 (en) * | 2020-03-11 | 2023-01-31 | Lumileds Llc | Light emitting diode devices with defined hard mask opening |
KR102416148B1 (en) * | 2020-06-15 | 2022-07-04 | 고려대학교 산학협력단 | Micro-led including optimized passivation layer and fabricating method thereof |
CN114023854B (en) * | 2021-09-09 | 2023-08-25 | 重庆康佳光电科技有限公司 | Light-emitting diode chip, preparation method thereof and display device |
CN114497333B (en) * | 2021-12-21 | 2024-12-17 | 镭昱光电科技(苏州)有限公司 | Micro-LED Micro display chip and manufacturing method thereof |
CN114628563B (en) * | 2022-05-12 | 2022-09-09 | 镭昱光电科技(苏州)有限公司 | Micro LED display chip and preparation method thereof |
CN114649322B (en) * | 2022-05-21 | 2022-08-09 | 镭昱光电科技(苏州)有限公司 | Micro LED display device and preparation method |
CN115881711A (en) * | 2022-12-14 | 2023-03-31 | 镭昱光电科技(苏州)有限公司 | Micro LED display device and preparation method thereof |
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WO2024125166A1 (en) * | 2022-12-14 | 2024-06-20 | 镭昱光电科技(苏州)有限公司 | Microled display device and manufacturing method therefor |
CN117393682A (en) * | 2023-12-13 | 2024-01-12 | 晶能光电股份有限公司 | Microdisplay device, microdisplay array structure and preparation method thereof |
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