CN113451146A

CN113451146A - Method for producing compound semiconductor device and compound semiconductor device

Info

Publication number: CN113451146A
Application number: CN202110675444.5A
Authority: CN
Inventors: 李勇
Original assignee: Gexin Zhixian Hangzhou Technology Co ltd
Current assignee: Gexin Zhixian Hangzhou Technology Co ltd
Priority date: 2021-06-18
Filing date: 2021-06-18
Publication date: 2021-09-28

Abstract

The invention discloses a preparation method of a compound semiconductor device and the compound semiconductor device, which mainly comprises the following steps: preparing a first conductive type semiconductor layer and a second conductive type semiconductor layer on the whole surface of a substrate; carrying out patterned etching from one side of the second conductive type semiconductor layer to form a first patterned etching structure exposed to the first conductive type semiconductor layer; respectively preparing a second contact electrode and a first contact electrode on the surface of the second conductive type semiconductor layer and the surface of the first conductive type semiconductor layer at the bottom of the first patterned etching structure; preparing an insulating passivation layer in the first patterned etching structure; electrically connecting the second contact electrode with the drive contact; a second patterned etching structure exposing a portion of the first contact electrode from one side of the first conductive type semiconductor layer is formed. The invention has no defect of material layer caused by selective area growth, and can avoid signal crosstalk between devices, thereby improving the performance of compound semiconductor device as a whole.

Description

Method for producing compound semiconductor device and compound semiconductor device

Technical Field

The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a method for manufacturing a monolithic compound semiconductor device and a monolithic compound semiconductor device.

Background

In conventional semiconductor systems, functional devices or devices and driving circuits are often separated on different wafers or substrates, or distributed at different locations on the same wafer or substrate, and are electrically connected by means of related wiring. For example, the compound Semiconductor device is packaged on a PCB (Printed Circuit Board) Circuit or a CMOS (Complementary Metal Oxide Semiconductor) driver after being manufactured. Such connections may generate more impedance and electromagnetic interference due to length and distance problems, affecting power consumption and signal transmission. Due to the long distance wiring and the integration of the conventional discrete devices, the conventional semiconductor system is difficult and challenged to continue to be miniaturized and integrated with high density, and in addition, due to the existence of the electrically connected lines, the light intensity and the direction of the photoelectric compound device are influenced, and the performance of the compound semiconductor device is also reduced.

Patent TW202006968A proposes a monolithic LED array precursor that solves the problems of difficulty in miniaturization and high-density integration due to excessively long wiring and degradation of performance of compound semiconductor devices due to wiring.

Fig. 1A and 1B show a cross-sectional structure and an LED array structure of the related art LED array precursor, respectively. The semiconductor material system related to this prior art is GaN (gallium nitride) and its alloy with InN (indium nitride) and AlN (aluminum nitride), the main structure includes a growth substrate 100 of sapphire, SiC (silicon carbide), Si (silicon) type material, a first semiconductor layer 110 (N-type semiconductor, which may contain GaN system material such as required buffer layer, etc.), SiO system including N through holes₂(silicon oxide) or Si₃N₄A masking layer 120 of (silicon nitride) material, a second semiconductor layer 130 (N-type semiconductor) via hole selective area grown based on the masking layer 120, a third semiconductor layer 140 including a plurality of quantum well layers 141 and a fourth semiconductor layer 150 (P-type semiconductor), and a main electrical contact 160 (main contact electrode) for ohmic contact current injection.

After the basic device (precursor) is completed, it is transferred to a driving backplate comprising a backplate substrate 200 and backplate contact pads 220, on which the reworked basic device is contained, which removes the growth substrate 100, covers the third semiconductor layer 140 again with a polar insulating passivation of the first semiconductor layer 121, and performs a roughening on the first semiconductor layer 110, performing an increase in light extraction, completing the roughening layer 112, while completing auxiliary electrical contacts 180 (auxiliary contact electrodes) on the first semiconductor layer 110 for making electrical contact with the first semiconductor layer 110.

This prior art mainly has the following problems:

1) as shown in fig. 1A, the device is prepared by a selective area growth scheme, and when an actual material grows, materials in the area around the masking layer 120 have defects, which causes the problems of quantum well layer active area defects, performance damage and the like;

2) the devices share the first semiconductor layer 110 (i.e., are common to the first semiconductor layer 110), and there may be problems of optical-electrical and signal crosstalk between the devices due to the sharing of the first semiconductor layer 110;

3) the auxiliary electrical contact 180 (auxiliary contact electrode) has a poorer electrical contact capability on the side closer to the substrate (growth substrate 100) than on the side farther from the substrate (growth substrate 100). Taking GaN polar material as an example, one surface close to the substrate (growth substrate 100) is an N polar surface, the other surface far from the substrate (growth substrate 100) is a Ga polar surface, the difficulty and stability of ohmic contact formed by the N polar surface are poorer than those of the Ga polar surface, and the voltage of the finally manufactured device is slightly higher;

4) the auxiliary electrical contact 180 (auxiliary contact electrode) is located on the side close to the substrate (growth substrate 100), and removal of the substrate (growth substrate 100) is necessary to form an electrical connection.

Disclosure of Invention

In view of the above, the present invention provides a method for manufacturing a compound semiconductor device and a compound semiconductor device, so as to avoid the problems of functional layer defects, signal crosstalk, and the like, and improve the performance of the compound semiconductor device.

The technical scheme of the invention is realized as follows:

a method for manufacturing a compound semiconductor device, comprising:

providing a first substrate, and preparing a semiconductor stacked structure on the whole surface of the first substrate, wherein the semiconductor stacked structure comprises a transition semiconductor layer, a first conductivity type semiconductor layer and a second conductivity type semiconductor layer which are stacked outwards from the surface of the first substrate;

performing patterned etching on the semiconductor stacked structure from one side of the second conductive type semiconductor layer to form a first patterned etching structure exposed to the first conductive type semiconductor layer;

respectively preparing a second contact electrode and a first contact electrode on the surface of the second conductive type semiconductor layer and the surface of the first conductive type semiconductor layer exposed at the bottom of the first patterned etching structure;

preparing an insulating passivation layer in the first patterned etching structure;

providing a driving back plate containing a driving contact, and electrically connecting the second contact electrode with the driving contact one to one;

and carrying out patterned etching on the semiconductor stacked structure to form a second patterned etching structure exposing a part of the first contact electrode from one side far away from the second conductivity type semiconductor layer and close to the first conductivity type semiconductor layer.

Further, still include:

and preparing a functional structure on one side of the first substrate.

Further, the semiconductor device structure does not include the first substrate portion.

Further, after the second contact electrode is electrically connected to the driving contact one-to-one, the method further includes:

and removing the first substrate.

Further, the preparing of the functional structure on the first substrate side includes:

preparing a metal bridging structure in the second patterned etching structure or preparing an interconnection structure for connecting the first contact electrode with other semiconductor device devices;

or,

preparing an insulating layer which is filled in the second patterned etching structure and is higher than the opening position of the second patterned etching structure, and forming a pit structure by the surrounding of the insulating layer;

and filling a chromatic aberration conversion material in the pit structure, and sealing the pit structure to form the optical color conversion structure.

Further, the one-to-one electrical connection of the second contact electrode with the driving contact includes:

and the second contact electrode and the driving contact are electrically connected in a one-to-one mode by adopting an alignment bonding mode, a welding mode or an electrode bridging mode.

Further, the one-to-one electrical connection of the second contact electrode and the driving contact by using an alignment bonding manner includes: aligning the driving contact with the second contact electrode and bonding the driving back plate to the second conductive type semiconductor layer;

the distribution of the driving contacts on the surface of the driving back plate is matched with the distribution of the second contact electrodes on the surface of the second conductive type semiconductor layer.

Further, the first conductive type semiconductor layer is an N-type semiconductor layer, and the second conductive type semiconductor layer is a P-type semiconductor layer;

or,

the first conductive type semiconductor layer is a P-type semiconductor layer, and the second conductive type semiconductor layer is an N-type semiconductor layer.

Further, when the semiconductor stack structure is prepared on the whole surface of the first substrate, the method further comprises the following steps:

an active region or a high electron mobility film layer is formed between the first conductive type semiconductor layer and the second conductive type semiconductor layer.

A compound semiconductor device comprising:

a drive back plate, the drive back plate containing drive contacts;

a second conductive type semiconductor layer;

a first conductive type semiconductor layer stacked on the second conductive type semiconductor layer;

a second contact electrode on a surface of the second conductive type semiconductor layer, and electrically connected to the driving contact one-to-one;

a first patterned etching structure in the second conductive type semiconductor layer and a portion of the first conductive type semiconductor layer;

the first contact electrode is positioned on the first conductive type semiconductor layer at the bottom of the first graphical etching structure;

an insulating passivation layer in the first patterned etched structure;

and the second patterned etching structure is positioned in the first conductive type semiconductor layer and positioned on one side far away from the second conductive type semiconductor layer and close to the first conductive type semiconductor layer, and part of the first contact electrode is exposed from the second patterned etching structure.

As can be seen from the above-described aspects, in the method for manufacturing a compound semiconductor device and the compound semiconductor device according to the present invention, after the entire surface of the semiconductor stacked structure is manufactured on the first substrate, the device region including the second contact electrode and the first contact electrode is defined by the patterned etching means, and the present invention does not employ the patterned growth means, and therefore, there is no defect of the material layer or the functional layer due to the selective area growth or the patterned growth.

Meanwhile, the second contact electrodes are electrically connected with the driving contacts in a one-to-one mode, so that the second contact electrodes are not connected in a common electrode mode, the first contact electrodes are provided with corresponding functional structures according to needs, a non-common electrode connection structure of the first contact electrodes can be achieved, and the problem of signal crosstalk caused by common electrodes among devices can be solved.

In addition, in the invention, the first contact electrode and the second contact electrode are not positioned on the first substrate, so that the electric connection structure does not relate to connection on the substrate, and the problems that the first substrate needs to be removed to carry out electric connection and the requirement on electric connection on the first substrate is high are solved.

As a whole, the compound semiconductor device and the method for manufacturing the compound semiconductor device according to the present invention can improve the performance of the compound semiconductor device as a whole.

Drawings

FIG. 1A is a schematic cross-sectional view of a prior art LED array precursor;

FIG. 1B is a schematic diagram of a prior art LED array structure;

FIG. 2 is a schematic flow chart of a method for fabricating a compound semiconductor device according to an embodiment of the present invention;

fig. 3A to 3F are schematic diagrams showing the evolution process of the device cross-sectional structure of the method for manufacturing a compound semiconductor device implemented by the present invention;

FIG. 4 is a schematic view of another insulating passivation layer in an embodiment of the present invention;

FIG. 5A is a schematic diagram of a hemispherical and pyramidal structure etched in a first substrate in an embodiment of the present invention;

FIG. 5B is a schematic diagram of a taper structure etched on the transition semiconductor layer after the first substrate is removed according to an embodiment of the present invention;

FIG. 6 is a schematic diagram illustrating a second patterned etched structure in a direction perpendicular to a surface of a transition semiconductor layer according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of an optical color conversion structure according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of one-to-one connection between the device and the first contact electrode in the embodiment of the present invention.

In the drawings, the names of the components represented by the respective reference numerals are as follows:

100. growth substrate

110. First semiconductor layer

112. Roughened layer

120. Masking layer

121. First semiconductor layer

130. A second semiconductor layer

140. Third semiconductor layer

141. Quantum well layer

150. A fourth semiconductor layer

160. Main electrical contact

180. Auxiliary electrical contact

200. Back board substrate

220. Back plate contact pad

101. A first substrate

102. Transitional semiconductor layer

103. A semiconductor layer of the first conductivity type

104. A semiconductor layer of the second conductivity type

105. First patterned etching structure

106. First contact electrode

107. Second contact electrode

108. Insulating passivation layer

201. Driving back plate

202. Driving contact

203. Second patterned etching structure

301. Insulating layer

302. Pit structure

303. Color difference conversion material

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and examples.

As shown in fig. 2, the method for manufacturing a compound semiconductor device according to an embodiment of the present invention mainly includes the following steps:

step 1, providing a first substrate, and preparing a semiconductor stacked structure on the whole surface of the first substrate, wherein the semiconductor stacked structure comprises a transition semiconductor layer, a first conductivity type semiconductor layer and a second conductivity type semiconductor layer which are stacked outwards from the surface of the first substrate;

step 2, carrying out patterned etching on the semiconductor stacked structure from one side of the second conduction type semiconductor layer to form a first patterned etching structure exposed to the first conduction type semiconductor layer, wherein the first patterned etching structure penetrates through the second conduction type semiconductor layer but does not penetrate through the first conduction type semiconductor layer;

step 3, respectively preparing a second contact electrode and a first contact electrode on the surface of the second conductive type semiconductor layer and the surface of the first conductive type semiconductor layer exposed at the bottom of the first graphical etching structure;

step 4, preparing an insulating passivation layer in the first graphical etching structure;

step 5, providing a driving back plate containing a driving contact, and electrically connecting the second contact electrode with the driving contact one to one;

and 6, carrying out patterned etching on the semiconductor stacked structure to form a second patterned etching structure which exposes a part of the first contact electrode from one side far away from the second conductive type semiconductor layer and close to the first conductive type semiconductor layer.

In the method for manufacturing the compound semiconductor device according to the embodiment of the present invention, the device region (including the second contact electrode and the first contact electrode) is defined by the patterned etching means after the entire surface of the semiconductor stacked structure is manufactured on the first substrate, and the method for manufacturing the compound semiconductor device according to the embodiment of the present invention does not use the patterned growth means, so that the compound semiconductor device manufactured by the method according to the embodiment of the present invention does not have the defects of some material layers (functional layers) caused by the selective growth means (patterned growth) in patent TW202006968A, and meanwhile, in the compound semiconductor device manufactured by the method according to the embodiment of the present invention, the second contact electrode and the driving contact are electrically connected in a one-to-one manner, so that the common electrode connection between the second contact electrodes does not exist, and the first contact electrode can also realize the non-common electrode connection structure according to the need to manufacture the corresponding functional structure, instead of inevitably having the devices common to the first semiconductor layer as in the TW202006968A patent, the problem of signal crosstalk between the devices due to common can be avoided. As a whole, the compound semiconductor device produced by the production method of the compound semiconductor device of the embodiment of the present invention can improve the performance of the compound semiconductor device as a whole.

Wherein in alternative embodiments the material of the first substrate comprises sapphire, silicon carbide, silicon, gallium nitride, gallium arsenide, gallium oxide, diamond, and the like. In alternative embodiments, the first substrate may be planar or micro-patterned (180 nm to 5 μm).

In an alternative embodiment, cleaning the surface of the first substrate before preparing the semiconductor stacked structure on the whole surface of the first substrate may specifically include: the first substrate surface is subjected to a hydrogenation treatment (left under a hydrogen atmosphere for 1 to 20 minutes) under a high temperature condition of 600 to 1300 ℃.

In an alternative embodiment, the transition semiconductor layer is grown on the cleaned surface of the first substrate at a temperature ranging from room temperature to 1200 ℃, the transition semiconductor layer may be made of a III-V compound such as gallium nitride, gallium oxide, gallium arsenide, silicon carbide, aluminum nitride, aluminum gallium indium phosphide (AlGaInP), aluminum gallium indium nitride (AlGaInN), or a multi-component alloy thereof, the transition semiconductor layer may include a stacked structure of different combinations of these materials, the transition semiconductor layer may be made of a special thin film material such as graphene, silicon oxide, aluminum oxide, or diamond, the transition semiconductor layer may be planar or patterned, and the transition semiconductor layer may be made of a combination of the above III-V compound and the above special thin film material.

In an alternative embodiment, the transition semiconductor Layer may be prepared by MOCVD (Metal-organic Chemical Vapor Deposition), Sputter (sputtering), or other methods, and may further include ALD (Atomic Layer Deposition), HVPE (Hydride Vapor Phase Epitaxy), MBE (Molecular Beam Epitaxy), and other methods for transferring a film Layer to a substrate, including bonding, assembly, or the like.

In the embodiment of the present invention, the transition semiconductor layer mainly functions to improve lattice, dislocation, thermal expansion, and stress mismatch problems of the first substrate and the subsequent compound semiconductor (the first conductivity type semiconductor layer, the second conductivity type semiconductor layer, and the like).

In an alternative embodiment, the thickness of the transition semiconductor layer is 1 nanometer to 5 micrometers.

In an alternative embodiment, the first conductive type semiconductor layer is an N-type semiconductor layer, and the second conductive type semiconductor layer is a P-type semiconductor layer; or, the first conductive type semiconductor layer is a P-type semiconductor layer, and the second conductive type semiconductor layer is an N-type semiconductor layer.

In alternative embodiments, the material of the first conductivity type semiconductor layer may be a group III-V compound such as gallium nitride, gallium oxide, gallium arsenide, silicon carbide, aluminum nitride, aluminum gallium indium phosphide, aluminum gallium indium nitride, and the like, and a multi-component alloy thereof, the material of the first conductivity type semiconductor layer may include a stacked structure of different combinations of these materials, and N-type (e.g., silicon doped) or P-type (e.g., magnesium doped) is formed by doping a suitable element, and the material of the first conductivity type semiconductor layer may further include a special thin film crystal such as graphene, silicon nitride, silicon oxide, aluminum oxide, and the like, and the special thin film crystal may be randomly distributed or orderly arranged.

In an alternative embodiment, the first conductive type semiconductor layer and the special thin film crystal structure therein are prepared by MOCVD, Sputter process, ALD, PECVD (Plasma Enhanced Chemical Vapor Deposition), HVPE, MBE and other film preparation methods, including growth, bonding, assembly, thin film coating and patterning.

In the embodiment of the invention, the first conductive type semiconductor layer is mainly used for forming an N-type or P-type semiconductor structure.

In an alternative embodiment, the thickness of the first conductive type semiconductor layer is 200 nm to 5 μm.

In alternative embodiments, the material of the second conductivity type semiconductor layer may be gallium nitride, gallium oxide, gallium arsenide, silicon carbide, aluminum nitride, aluminum gallium indium phosphide, or other III-V compounds, or a multi-component alloy thereof, and the material of the second conductivity type semiconductor layer may include a stacked structure of different combinations of these materials, and P-type (e.g., magnesium-doped) or N-type (e.g., silicon-doped) is formed by doping with a suitable element.

In an alternative embodiment, in performing the entire surface preparation of the semiconductor stack structure on the first substrate in step 1, the method for manufacturing a compound semiconductor device according to an embodiment of the present invention may further include:

In an alternative embodiment, the active region or the high electron mobility film may be disposed inside the second conductive type semiconductor layer or between the second conductive type semiconductor layer and the first conductive type semiconductor layer, and the active region or the high electron mobility film includes a quantum well, a two-dimensional electrical channel, an optical DBR (Distributed Bragg reflector), a current blocking layer, and the like.

In an alternative embodiment, the second conductive type semiconductor layer is prepared by MOCVD, Sputter process, ALD, PECVD, HVPE, MBE, and other methods of transferring a film layer to a substrate, including growth, bonding, assembly, film coating, patterning, and the like.

In the embodiment of the invention, the second conductive type semiconductor layer is mainly used for forming a P-type or N-type semiconductor structure.

In an alternative embodiment, the thickness of the second conductive type semiconductor layer is 80 nm to 3 μm.

In alternative embodiments, the cross section of the first patterned etching structure in step 2 may be a vertical structure, a regular trapezoid structure or an inverted trapezoid structure, and the cross section structures with different shapes may be selected according to the target device to be manufactured. For example, the first patterned etched structure having a vertical cross-sectional structure is preferable if the target device to be manufactured is an electronic device, and the first patterned etched structure having a trapezoidal or inverted trapezoidal cross-sectional structure is preferable if the target device to be manufactured is an optoelectronic device. In a preferred embodiment, the sidewall angle to the base in either the right trapezoid or the inverted trapezoid is optimally at a 55 angle.

In an alternative embodiment, the first contact electrode corresponds to the first conductive type semiconductor layer, and the second contact electrode corresponds to the second conductive type semiconductor layer. If the first conductive type semiconductor layer is an N-type semiconductor layer and the second conductive type semiconductor layer is a P-type semiconductor layer, the first contact electrode is an N-type contact electrode and the second contact electrode is a P-type contact electrode; if the first conductive type semiconductor layer is a P-type semiconductor layer and the second conductive type semiconductor layer is an N-type semiconductor layer, the first contact electrode is a P-type contact electrode and the second contact electrode is an N-type contact electrode.

In alternative embodiments, it is also possible to prepare only the first contact electrode or only the second contact electrode.

In alternative embodiments, the material of the first contact electrode and the second contact electrode may include one or more stacked structures of metals such as chromium, titanium, aluminum, nickel, silver, gold, platinum, germanium, zinc, and the like, one or more stacked structures of metal oxides such as indium tin oxide, zinc oxide, and the like, and a mixed film of these metals and metal oxides.

In an alternative embodiment, the first contact electrode and the second contact electrode may be prepared by a patterned metal evaporation method, a sputtering coating method, or a contact electrode is prepared and then patterned. In alternative embodiments, the first contact electrode and the second contact electrode may be prepared simultaneously, or the first contact electrode and the second contact electrode may be prepared separately. In an alternative embodiment, after the electrode film layers of the first contact electrode and the second contact electrode are prepared, a high temperature alloy or other related processes may be performed to obtain the required contact, such as an ohmic contact or a schottky contact.

In the embodiment of the invention, the insulating passivation layer has the function of preventing the problems of electric leakage, impurity particle adhesion of a dangling bond, insulation and the like of the side wall of the exposed first conductive type semiconductor layer in the first patterned etching structure.

In an alternative embodiment, the insulating passivation layer may be filled only in the first patterned etched structure, or may be filled in the entire surface (including the first patterned etched structure and the surface of the second conductive type semiconductor layer) and then the second contact electrode is exposed.

In alternative embodiments, the material of the insulating passivation layer may be a dielectric material such as silicon nitride, silicon oxide, aluminum oxide, or the like, or a stacked structure thereof, the material of the insulating passivation layer may also be a non-conductive compound semiconductor material that is the same as the material of the transition semiconductor layer, and the material of the insulating passivation layer may also be an organic material such as SU8 (a photosensitive organic silicon type material), polyimide, or polymer.

In alternative embodiments, the insulating passivation layer may be prepared by CVD, ALD, blanket coating, and the like.

In alternative embodiments, the driving backplane may contain driving circuitry therein, or the driving backplane may contain a circuit arrangement electrically connected to the driving contacts by the driving circuitry.

In an alternative embodiment, the second patterned etched structure is prepared by means of a deep trench etch in step 6 to expose a portion of the first contact electrode from one side of the first conductive type semiconductor layer, and another portion of the first contact electrode is still in electrical contact with the first conductive type semiconductor layer material at the bottom of the first patterned etched structure. Wherein, the first conductive type semiconductor layer of the monolithic region can be exposed or the first conductive type semiconductor layer of the prepared surrounding region of the device can be exposed through the design of the second patterned etching structure.

In alternative embodiments, the shape of the second patterned etched structure may be a single via, a ring-shaped groove, a rectangular groove, or other common shapes. In an alternative embodiment, the sidewall profile etched by the deep trench of the second patterned etching structure may be vertical, trapezoidal, etc., preferably vertical. The width (e.g., via width, groove width) of the second patterned etching structure is 1 to 200 μm.

The first contact electrode exposed in the second patterned etched structure may be integrated with other semiconductor devices in a series-parallel manner.

The compound semiconductor device after the completion of the above steps 1 to 6 corresponds to a precursor (i.e., a base device) in the patent TW202006968A, and on this basis, a corresponding functional structure can be prepared as required, and finally, the preparation of a desired semiconductor device (device) is completed. Therefore, in alternative embodiments, the method of the compound semiconductor device of the embodiment of the present invention may further include, after completion of step 6:

and 7, preparing a functional structure on one side of the first substrate.

In an alternative embodiment, the semiconductor device structure does not include the first substrate portion. With this alternative embodiment, the possibility of the first contact electrode being connected in common via the first substrate is eliminated, thereby eliminating signal cross-talk between the devices due to common.

Therefore, in an alternative embodiment, after the step 5 of electrically connecting the second contact electrode and the driving contact one-to-one is completed, the method for manufacturing a compound semiconductor device of an embodiment of the present invention further includes: the first substrate is removed.

The step of removing the first substrate may be performed before step 6, or may be performed after step 6.

In addition, in other embodiments of manufacturing a device requiring the first substrate for performing a function, the step of removing the first substrate may not be performed, and the first substrate may be patterned and etched correspondingly as required to form a component of the functional device.

In addition, in alternative embodiments, the transition semiconductor layer may be selectively retained or removed as desired.

In an alternative embodiment, if the first substrate and the transition semiconductor layer remain, the first substrate (or the first substrate and the transition semiconductor layer together) may be patterned and etched in a subsequent process as required to obtain a desired structure, such as a hemispherical structure, a pointed conical structure, and the like.

In alternative embodiments, the functional structures fabricated on the first substrate side may include metal bridging structures, interconnect structures, optical color conversion structures, and the like.

On the basis of this, in an alternative embodiment, the step 7 of preparing the functional structure on the first substrate side may include:

and preparing a metal bridging structure in the second patterned etching structure or preparing an interconnection structure for connecting the first contact electrode with other semiconductor device devices.

Alternatively, the step 7 of preparing the functional structure on the first substrate side may include:

step 71, preparing an insulating layer which is filled in the second patterned etching structure and is higher than the opening position of the second patterned etching structure, and forming a pit structure by the surrounding of the insulating layer;

and step 72, filling a chromatic aberration conversion material in the pit structure, and sealing the pit structure to form the optical color conversion structure.

Wherein steps 71 and 72 are steps performed to prepare the optical color conversion structure.

It should be noted that, according to the design requirements of the semiconductor integrated circuit, different functional structures such as a metal bridging structure, an interconnection structure, an optical color conversion structure, and the like may exist on the same semiconductor stacked structure at the same time, or only one or more of the functional structures may exist, and different functional structures may be prepared in different regions of the same semiconductor stacked structure according to different functional partition.

In an alternative embodiment, the material of the insulating layer used in step 71 is, for example, an insulating dielectric material, photoresist, SU8 (a photosensitive silicone type material), or the like.

In alternative embodiments, the color difference conversion material is a material such as quantum dots, phosphors, or the like.

In an alternative embodiment, the pit structure is sealed in step 72 with a material such as silicon oxide, aluminum oxide, or the like.

In an alternative embodiment, the one-to-one electrical connection of the second contact electrode with the driving contact of step 5 includes:

For the requirements of miniaturization and high-density integration, it is preferable that the second contact electrode is electrically connected to the driving contact one-to-one in an aligned bonding manner. In the preferred embodiment, the one-to-one electrical connection of the second contact electrode with the driving contact by aligned bonding includes:

the driving contact is aligned with the second contact electrode, and the driving back plate is bonded to the second conductive type semiconductor layer.

In alternative embodiments, the material used for electrically connecting the second contact electrode and the driving contact may be the material of the second contact electrode and the driving contact, at least one of gold, tin, copper, nickel, indium, or other welding metal materials, or an alloy composed of at least two of these metal materials, or a non-metal material such as silicon oxide, polymer, or other material filled in the non-electrode region. If the material used for electrically connecting the second contact electrode and the driving contact is non-metal material such as silicon oxide, polymer and the like filled in the non-electrode region, an electrically conductive bridge needs to be prepared on the non-metal material such as silicon oxide, polymer and the like filled in the non-electrode region to electrically connect the second contact electrode and the driving contact.

The method for manufacturing a compound semiconductor device according to the embodiment of the present invention will be further described below with reference to specific examples of a process for manufacturing a compound semiconductor device.

Step a1, as shown in FIG. 3A, a compound semiconductor wafer is prepared.

Preferably, a suitable first substrate 101 is selected, and materials such as sapphire, silicon carbide, silicon, gallium nitride, gallium arsenide, gallium oxide, diamond, etc. can be used as the material of the first substrate 101. The first substrate 101 may be planar or micro (180 nm to 5 μm) patterned.

The first substrate 101 is passed through a 600 deg.C temperatureAfter the surface cleaning is finished by high-temperature hydrogenation (standing for 1-20 minutes in hydrogen atmosphere) treatment to 1300 ℃, the growth of the transition semiconductor layer 102 is carried out, the growth temperature is in the range of normal temperature to 1200 ℃, and the transition semiconductor layer 102 can be GaN (gallium nitride) and Ga₂O₃(gallium oxide), GaAs (gallium arsenide), SiC (silicon carbide), AlN (aluminum nitride), AlGaInP, AlGaInN, and other III-V group compounds and their multi-element alloys, the transition semiconductor layer 102 comprises different combination laminates of these materials, the transition semiconductor layer 102 can also be graphene, SiO, etc₂(silicon oxide) and Al₂O₃(alumina), diamond, and other special thin film materials. The transition semiconductor layer 102 may be a full-thickness film layer or a patterned film layer, and the transition semiconductor layer 102 may also be a combination of a group III-V compound and a special thin film material. The first semiconductor may be prepared by a conventional method such as MOCVD or Sputter sputtering, or by a thin film preparation method such as ALD, HVPE, and MBE, or by other methods such as bonding and assembly, in which a film layer is transferred to a substrate. The transition semiconductor layer 102 is mainly used to improve lattice, dislocation, thermal expansion, and stress mismatch problems between the first substrate 101 and the subsequent compound semiconductor. The thickness of the transition semiconductor layer 102 is in the range of 1 nm to 5 μm.

After the transition semiconductor layer 102 is completed, the first conductive type semiconductor layer 103 is prepared, and the first conductive type semiconductor layer 103 may be of an N type or a P type. The first conductive type semiconductor layer 103 may be GaN, Ga₂O₃GaAs, SiC, AlN, AlGaInP, AlGaInN, and the like group III-V compounds and multi-element alloys thereof, the first conductivity type semiconductor layer 103 includes different combination stacks of these materials. The first conductive type semiconductor layer 103 is formed to be N-type (e.g., Si-doped) or P-type (e.g., Mg-doped) by doping of an appropriate element. Graphene, silicon nitride, SiO may be included in the first conductive type semiconductor layer 103₂、Al₂O₃And the special thin film crystals can be randomly distributed or orderly arranged. The first conductivity type semiconductor layer 103 and the method for preparing the special thin film crystal therein include MOCVD, Sputter sputtering, ALD, PECVD, HVPE, MBE and other thin film preparation methods orOther methods for transferring the film layer to the substrate include growing, bonding, assembling, film coating, patterning, and the like. The first conductive type semiconductor layer 103 is mainly used to form an N-type or P-type semiconductor structure. The thickness of the first conductive type semiconductor layer 103 is 200 nm to 5 μm.

The preparation of the second conductive type semiconductor layer 104 is performed after the first conductive type semiconductor layer 103 is completed. The second conductive type semiconductor layer 104 may be P-type or N-type, as required. The second conductive type semiconductor layer 104 may be GaN, Ga₂O₃GaAs, SiC, AlN, AlGaInP, AlGaInN, and the like, and multi-element alloys thereof, and the second conductive type semiconductor layer 104 includes different combination stacks of these materials. The second conductive type semiconductor layer 104 is doped with a suitable element to form a P-type (e.g., Mg-doped) or an N-type (e.g., Si-doped). Meanwhile, a source region or a high electron mobility film (not shown) may be disposed inside the second conductive type semiconductor layer 104 or between the second conductive type semiconductor layer 104 and the first conductive type semiconductor layer 103, and the active region or the high electron mobility film may include a quantum well, a two-dimensional electrical channel, an optical DBR, a current blocking layer, and the like. The second conductive type semiconductor layer 104 may be formed by a method including a thin film formation method such as MOCVD, Sputter sputtering, ALD, PECVD, HVPE, MBE, or other methods of transferring a film layer to a substrate, such as growth, bonding, assembly, thin film coating, and patterning. The second conductive type semiconductor layer 104 is mainly used to form a P-type or N-type semiconductor structure. The thickness of the second conductive type semiconductor layer 104 is 80 nm to 3 μm.

Step a2, as shown in fig. 3B, prepares the first patterned etched structure 105.

The first patterned etching structure 105 is formed by performing patterned etching from the second conductive type semiconductor layer 104 side by etching or cutting means. The first patterned etched structure 105 is exposed to the first conductive type semiconductor layer 103, i.e., the first patterned etched structure 105 penetrates the second conductive type semiconductor layer 104 but does not penetrate the first conductive type semiconductor layer 103. As shown in fig. 3B, the sidewall angle of the first patterned etched structure 105 may be a vertical structure, a regular trapezoid structure or an inverted trapezoid structure, and the specific structure is selected according to the target device to be manufactured, for example, the electronic device is preferably a vertical structure, the optoelectronic device is preferably a trapezoid structure, and the angle between the sidewall and the bottom surface (sidewall inclination angle) of the first patterned etched structure 105 is most preferably 55 ° regardless of the regular trapezoid structure or the inverted trapezoid structure.

Step a3, shown in FIG. 3C, prepares a contact electrode.

Common devices need to prepare two kinds of contact electrodes, i.e., a P-type contact electrode and an N-type contact electrode, and the number of contact electrodes in practice may include one to more.

The preparation of the contact electrode may include a first contact electrode 106 on first conductivity-type semiconductor layer 103 and a second contact electrode 107 on second conductivity-type semiconductor layer 104, or only first contact electrode 106 on first conductivity-type semiconductor layer 103, or single kind(s) of second contact electrode 107 on second conductivity-type semiconductor layer 104. The material of the first contact electrode 106 and the second contact electrode 107 may include one or more stacked-layer structures of metals such as Cr (chromium), Ti (titanium), Al (aluminum), Ni (nickel), Ag (silver), Au (gold), Pt (platinum), Ge (germanium), Zn (zinc), or one or more stacked-layer structures of metal oxides such as indium tin oxide, zinc oxide, and a mixed film layer of metals and metal oxides.

The contact electrode is prepared by a patterned metal evaporation and sputtering coating method, or the contact electrode is prepared first and then patterned, the first contact electrode 106 and the second contact electrode 107 can be prepared together, the first contact electrode 106 and the second contact electrode 107 can be prepared separately, and after the preparation of the electrode film layer of the contact electrode, the electrode film layer can be subjected to related processing such as high-temperature alloy and the like to obtain the required contact, such as ohmic contact or schottky contact.

Step a4, shown in FIG. 3D, passivation.

An insulating passivation layer 108 is prepared in the first patterned etched structure 105. As shown in fig. 3D, the insulating passivation layer 108 may be filled only in the first patterned etched structure 105. In addition, fig. 4 shows another topographic structure of the insulating passivation layer 108, wherein the insulating passivation layer 108 may be filled on the entire surface of the first patterned etched structure 105 and the surface of the second conductive type semiconductor layer 104, and then the second contact electrode 107 is exposed.

The material of the insulating passivation layer 108 may be silicon nitride, SiO₂、Al₂O₃The dielectric material and the stack thereof may be a non-conductive compound semiconductor material similar to the material of the transition semiconductor layer 102, or may be an organic material such as SU8, polyimide, or polymer.

The insulating passivation layer 108 may be prepared by CVD, ALD, blanket coating, etc.

The passivation process (the prepared insulating passivation layer 108) can prevent the sidewall of the first conductive type semiconductor layer 103 exposed in the first patterned etched structure 105 from problems of leakage, dangling bond adhesion of impurity particles, insulation, and the like.

Step a5, as shown in FIG. 3E, drives the connection.

A drive backplane 201 is provided that contains drive contacts 202. The driving backplane 201 may contain driving circuitry therein, or a circuit arrangement connecting the driving circuitry and the driving contacts 202.

The second contact electrode 107 is connected to the driving contact 202 in a one-to-one manner, which includes alignment bonding, soldering, electrode bridging, and the like, and fig. 3E shows a structure of the alignment bonding connection.

The material for connecting the second contact electrode 107 and the driving contact 202 may be the material of the second contact electrode 107 and the driving contact 202, at least one of the soldering metal materials such as Au, Sn (tin), Cu (copper), Ni, In (indium), or an alloy composed of at least two of these metal materials, or an alloy filled In the non-electrode region such as SiO₂And non-metallic materials such as polymers.

Step a6, as shown in FIG. 3F, the first contact electrode 106 is exposed.

This step is to form second patterned etched structure 203 exposing a portion of first contact electrode 106 from a side remote from second conductivity-type semiconductor layer 104 and close to first conductivity-type semiconductor layer 103 by performing patterned etching on the semiconductor stacked structure from a side remote from second conductivity-type semiconductor layer 104 and close to first conductivity-type semiconductor layer 103.

In this step, the first substrate 101 and the transition semiconductor layer 102 may be selectively remained or removed according to requirements, for example, the first substrate 101 is selectively removed and the transition semiconductor layer 102 is remained as shown in fig. 3F. If the first substrate 101 and the transition semiconductor layer 102 remain, a corresponding patterning etching may be performed as required, including a hemispherical structure, a pointed cone structure, and the like, for example, the hemispherical structure and the pointed cone structure etched on the first substrate 101 shown in fig. 5A, and the pointed cone structure etched on the transition semiconductor layer 102 and removed from the first substrate 101 shown in fig. 5B.

In this step, the device preparation area and shape may be confirmed according to the positions of the driving contact 202 on the driving back plate 201 and the first contact electrode 106 connected to the first conductive type semiconductor layer 103 (for example, alignment may be performed by using infrared, far infrared penetration related materials, which may include a front alignment technique and a back alignment technique, or edge alignment may be performed by using a wafer profile), the transition semiconductor layer 102 (in a case where it is not removed) and the first conductive type semiconductor layer 103 are etched by a deep trench etching method to form the second patterned etching structure 203, a portion of the material of the first contact electrode 106 forming an electrical contact with the first conductive type semiconductor layer 103 is exposed from the bottom of the second patterned etching structure 203, and another portion of the material of the first contact electrode 106 continues to maintain an electrical contact with the first conductive type semiconductor layer 103. As shown in fig. 6, the second patterned etched structure 203 may expose the first conductive type semiconductor layer 103 in a single region or expose the first conductive type semiconductor layer 103 in a region around the prepared device, and the second patterned etched structure 203 may have a shape of a single via, a rectangle, a ring, or the like.

The width (e.g., via width, groove width) of the second patterned etched structure 203 is 1 to 200 micrometers, and the exposed first contact electrode 106 may be integrated with other devices in a series-parallel manner, and the sidewall profile of the second patterned etched structure 203 may be vertical or inclined, preferably vertical.

Fig. 5A and 5B show a structure in which adjacent devices are connected in common at the same first contact electrode 106, and this structure can realize parallel connection between the devices. In other alternative embodiments, adjacent devices may be configured as shown in fig. 8, wherein each device is electrically connected to only one first contact electrode 106, in such a way that individual circuit control for each device may be achieved.

Step a7, carrying out other structure preparation.

In this step, a subsequent structure may be prepared on the basis of the structure prepared in step a6 as required. For example, the second contact electrode 107 deep trench is exposed to be filled and leveled or a concave or convex step is prepared, and after filling, the electrical connection is enhanced or a subsequent structure is prepared, such as a metal bridge for enhancing current spreading, a signal enhancement, other device interconnection for signal reception, an optical color conversion structure, and the like.

Fig. 7 shows an optical color conversion structure. The process of the optical color conversion structure is as follows:

an insulating layer 301 filled in the second patterned etched structure 203 and having a height higher than the opening position (i.e., the surface of the transition semiconductor layer 102) of the second patterned etched structure 203 is prepared, and a pit structure 302 is formed surrounded by the insulating layer 301. A pit structure 302 is filled with a chromatic aberration conversion material 303, and the pit structure 302 is sealed to form an optical color conversion structure. Wherein, the material of the insulating layer 301 such as insulating dielectric material, photoresist, organic matter such as SU8, etc., the color difference conversion material 303 such as quantum dot, phosphor, etc., and the sealing of the pit structure 302 can be made of SiO₂Or Al₂O₃And (6) packaging.

The embodiment of the present invention also provides a compound semiconductor device, which includes, as shown in fig. 3F, a driving back plate 201, a second conductive type semiconductor layer 104, a first conductive type semiconductor layer 103, a second contact electrode 107, a first patterned etching structure 105, a first contact electrode 106, an insulating passivation layer 108, and a second patterned etching structure 203. Wherein the driving back plate 201 contains driving contacts 202. The first conductive type semiconductor layer 103 is stacked on the second conductive type semiconductor layer 104. The second contact electrode 107 is located on a surface of the second conductive type semiconductor layer 104 facing the driving back plate 201, and the second contact electrode 107 is electrically connected to the driving contacts 202 one-to-one. First patterned etched structure 105 is located in second conductive type semiconductor layer 104 and a portion of first conductive type semiconductor layer 103, i.e., first patterned etched structure 105 penetrates second conductive type semiconductor layer 104 but does not penetrate first conductive type semiconductor layer 103.

The first contact electrode 106 is positioned on the first conductive type semiconductor layer 103 at the bottom of the first patterned etched structure 105. An insulating passivation layer 108 is located in the first patterned etched structure 105. Second patterned etched structure 203 is located in first conductive type semiconductor layer 103, and second patterned etched structure 203 is located at a side far from second conductive type semiconductor layer 104 and close to first conductive type semiconductor layer 103, and a portion of first contact electrode 106 is exposed from second patterned etched structure 203.

In the method for manufacturing a compound semiconductor device and the compound semiconductor device according to the embodiments of the present invention, after the entire surface of the semiconductor stacked structure is manufactured on the first substrate, the device region including the second contact electrode and the first contact electrode is defined by the patterned etching means.

Meanwhile, in the embodiment of the invention, the second contact electrodes are electrically connected with the driving contacts in a one-to-one manner, so that no common-pole connection exists between the second contact electrodes, and the first contact electrode is provided with a corresponding functional structure as required, so that a non-common-pole connection structure of the first contact electrode can be realized, and the problem of signal crosstalk caused by common-pole connection between devices can be further avoided.

In addition, in the embodiment of the invention, the first contact electrode and the second contact electrode are not positioned on the first substrate, so that the electrical connection structure does not relate to connection on the substrate, and the problems that the first substrate needs to be removed to carry out electrical connection and the requirement on electrical connection on the first substrate is high are solved.

In general, the compound semiconductor device and the method for manufacturing the compound semiconductor device according to the embodiments of the present invention can improve the performance of the compound semiconductor device as a whole.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A method for manufacturing a compound semiconductor device, comprising:

2. The method for manufacturing a compound semiconductor device according to claim 1, further comprising:

and preparing a functional structure on one side of the first substrate.

3. The method for manufacturing a compound semiconductor device according to claim 2, wherein:

the semiconductor device structure does not include the first substrate portion.

4. The method for manufacturing a compound semiconductor device according to claim 3, further comprising, after electrically connecting the second contact electrode and the driving contact one-to-one:

and removing the first substrate.

5. The method for manufacturing a compound semiconductor device according to claim 4, wherein the manufacturing of the functional structure on the first substrate side includes:

or,

6. A method for producing a compound semiconductor device according to claim 1, wherein said electrically connecting the second contact electrode and the driving contact one to one comprises:

7. The method for producing a compound semiconductor device according to claim 6, wherein the one-to-one electrical connection of the second contact electrode and the driving contact by aligned bonding comprises:

aligning the driving contact with the second contact electrode and bonding the driving back plate to the second conductive type semiconductor layer;

8. The method for manufacturing a compound semiconductor device according to claim 1, wherein:

the first conduction type semiconductor layer is an N-type semiconductor layer, and the second conduction type semiconductor layer is a P-type semiconductor layer;

or,

9. The method for manufacturing a compound semiconductor device according to claim 1, further comprising, when manufacturing a semiconductor stack structure over the entire surface of the first substrate:

10. A compound semiconductor device, comprising:

a drive back plate, the drive back plate containing drive contacts;

a second conductive type semiconductor layer;

an insulating passivation layer in the first patterned etched structure;