CN1157644C - Computer system capable of supporting different types of dynamic random access memories - Google Patents

Abstract

A computer system that can support different types of dynamic random access memory includes a first slot, a second slot, a north bridge chip that can support the first type of slot and the second type of slot respectively, and a control circuit connected to the north bridge chip. The first slot is used to install the first type of dynamic random access memory. The first slot includes a plurality of first slot pins, and each first slot pin corresponds to a first pin definition. The second slot is used to install the second type of dynamic random access memory. The second slot includes a plurality of second slot pins, and each second slot pin corresponds to a second pin definition.

Description

Computer system that can support different types of dynamic random access memory

technical field

The invention relates to a computer system capable of supporting different types of dynamic random access memory, in particular to a computer system capable of supporting double data dynamic random access memory (DDRAM) and synchronous dynamic random access memory (SDRAM).

Background technique

Double Data Dynamic Random Access Memory (DDRAM) and Double Line Memory Module Socket with 184 pins (184pin DIMM) have become the main trends in the future of Dynamic Random Access Memory (DRAM). However, there will still be a considerable market transition period from synchronous dynamic random access memory (SDRAM) and double-lined memory module sockets with 168 pins (168pin DIMM) to DDRAM and 184pin DIMM.

Because the pin assignments of 184pin DIMM and 168pin DIMM are different, the computer system that supports DDRAM and 184pin DIMM cannot support SDRAM and 168pin DIMM, and the computer system that supports SDRAM and 168pin DIMM cannot support DDRAM and 184pin DIMM DIMMs. Therefore, during the transition period of market conversion, users will have considerable troubles and troubles in selecting and upgrading specifications.

Contents of the invention

Therefore, the main objective of the present invention is to provide a computer system capable of supporting both double data dynamic random access memory (DDRAM) and synchronous dynamic dynamic random access memory (SDRAM), so as to solve the above-mentioned problems.

In order to achieve the purpose of the present invention, the present invention provides a computer system for supporting a first type of dynamic random access memory and a second type of dynamic random access memory, which includes: a motherboard, including a A first plane and a second plane; a first slot installed on the first plane of the motherboard for installing the first type of dynamic random access memory, the first slot includes a plurality of first slots Groove pins, each first slot pin is defined corresponding to a first pin; a second slot, installed on the first plane of the motherboard, used to install the second type of dynamic random access Memory, the second slot includes a plurality of second slot pins, each second slot pin is defined corresponding to a second pin; multiple conduction paths; a north bridge chip installed on the motherboard The first plane, which includes a plurality of chip pins, is connected to the first socket and the second socket through the conduction path, and each chip pin is corresponding to a first pin definition and a second pin definition; and a control circuit installed on the first plane of the main board and connected to the north bridge chip for setting the pin definition of the chip pin; wherein the control circuit inputs a first control signal into the north bridge Chip, the pin definition of the chip pin will be set to the first pin definition, so that the north bridge chip can carry out data transmission with the first type of dynamic random access memory; the control circuit sends a second control signal Inputting the north bridge chip, the pin definition of the chip pin will be set as the second pin definition, so that the north bridge chip can perform data transmission with the second type of dynamic random access memory.

The present invention also provides a computer system for supporting a double data dynamic random access memory and a synchronous dynamic random access memory, which includes: a motherboard including a first plane and a second plane; a The first slot is installed on the first plane of the motherboard, and is used to install the double data dynamic random access memory. The first slot includes a plurality of first slot pins, and each first slot tube The pin is corresponding to a first pin definition, and the first pin definition belongs to a plurality of pin definition groups; a second slot is installed on the first plane of the motherboard, and is used for installing the synchronous dynamic random For accessing memory, the second slot includes a plurality of second slot pins, each second slot pin corresponds to a second pin definition, and the second pin definition belongs to the plurality of pins respectively Definition group; multiple conduction paths; a North Bridge chip installed on the first plane of the motherboard, which includes a plurality of chip pins, connected to the first slot and the second slot via the conduction path, each A chip pin is corresponding to a first pin definition and a second pin definition, and the first pin definition and the second pin definition belong to the same pin definition group; and a control circuit installed on The first plane of the motherboard is connected to the north bridge chip, and is used to set the pin definitions of the chip pins; wherein, the control circuit inputs a first control signal into the north bridge chip, and the pins of the chip pins The definition will be set as the first pin definition, so that the north bridge chip can carry out data transmission with the double data dynamic random access memory; and when the control circuit inputs a second control signal into the north bridge chip, the chip tube The pin definition of the pin is set to the second pin definition, so that the north bridge chip can perform data transmission with the synchronous dynamic random access memory.

Description of drawings

FIG. 1 is a schematic diagram of the computer system of the present invention.

Fig. 2 is a schematic diagram of the first slot.

Figure 3 is a pin definition group table.

Fig. 4 is a schematic diagram of the second slot.

FIG. 5 is a pin definition correspondence table of chip pins of the north bridge chip.

FIG. 6 is a schematic view of the first plane of the motherboard of the computer system of the present invention.

FIG. 7 is a schematic diagram of the second plane of the motherboard of the computer system of the present invention.

Detailed ways

See Figure 1. FIG. 1 is a schematic diagram of a computer system 10 of the present invention. The computer system 10 can support both types of DRAM at the same time. Wherein, the first type of DRAM is double data DRAM (DDRAM), and the second type of DRAM is a synchronous DRAM (SDRAM). The computer system 10 includes a first slot 12 , a second slot 14 , a north bridge chip 16 , a control circuit 18 , and a detection circuit 20 .

Please refer to Figure 2. FIG. 2 is a schematic diagram of the first slot 12 . The first slot 12 is a double-line memory module slot (184pin DIMM) with 184 pins, which is used for installing double data dynamic random access memory (DDRAM). The first socket 12 includes a plurality of pins, and each pin corresponds to a first pin definition.

See Figure 3. Figure 3 is a pin definition group table. The first pin definitions corresponding to the pins of the first socket 12 connected to the north bridge chip 16 respectively belong to a data pin definition group, an address pin definition group, and a command pin definition group. For example, a pin defined as MD[0:63] belongs to the data pin definition group.

See Figure 4. FIG. 4 is a schematic diagram of the second slot 14 . The second slot 14 is a double line memory module slot (168pin DIMM) with 168 pins, which is used to install a synchronous dynamic random access memory (SDRAM). The second socket 14 includes a plurality of pins, and each pin corresponds to a second pin definition.

As shown in FIG. 3 , the second slot 14 is used to connect to the second pin definitions corresponding to the pins of the northbridge chip 16 respectively belonging to the data pin definition group, the address pin definition group, and the command pin definition group. For example, a pin defined as MD[0:63] belongs to the data pin definition group.

The north bridge chip 16 is connected to the first socket 12 and the second socket 14 . See Figure 5. FIG. 5 is a pin definition correspondence table of chip pins of the north bridge chip 16 . The north bridge chip includes a plurality of chip pins for connecting to the first socket 12 and the second socket 14 to control the memory. Each chip pin corresponds to a first pin definition and a second pin definition. Wherein, the first pin definition and the second pin definition corresponding to each chip pin belong to the same pin definition group. For example, the pin Y24 corresponds to the first pin definition CKE(J)5 and the second pin definition CKE(J)3, and both CKE(J)5 and CKEJ)3 belong to the command pin definition group.

As shown in FIG. 1 , the detection circuit 20 is electrically connected to the control circuit 18 . When the detection circuit 20 detects that the double data DRAM is installed in the first slot 12, the detection circuit 20 will transmit a first detection signal to the control circuit 18, so that the control circuit 18 will input a first control signal To the north bridge chip 16. At this time, the pin definition of the chip pins of the north bridge chip 16 will be set as the first pin definition, so that the north bridge chip 16 can perform data transmission with the double data DRAM.

When the detection circuit 20 detects that the synchronous dynamic random access memory is installed in the second slot 14, the detection circuit 20 will transmit a second detection signal to the control circuit 18, so that the control circuit 18 will input a second control signal to the north bridge Chip 16. At this time, the pin definition of the chip pins of the north bridge chip 16 will be set as the second pin definition, so that the north bridge chip 16 can perform data transmission with the synchronous dynamic random access memory.

For example, the control circuit 18 can utilize other pins (non-chip pins) of the north bridge chip 16, such as AD18 (not shown), to set the pin definition of the chip pins (listed in FIG. 5 ) of the north bridge chip 16 . When the pin AD18 is high, the pin definition of the chip pins of the north bridge chip 16 will be set as the first pin definition to support the DDR memory component. And when the pin AD18 is at low potential, the pin definition of the chip pins of the north bridge chip 16 will be set as the second pin definition to support the SDR memory component.

In the present invention, the north bridge chip must support two kinds of memory components. Therefore, in order to implement the present invention, considerable thought must be spent on the component configuration and pin arrangement of the motherboard. In the known technology, R&D engineers will first define the function of the chip, determine the number of pins, and arrange the positions of the pins, and then design the circuit and make the motherboard accordingly. Due to the fixed position of the pins, in the process of circuit layout (layout), unnecessary through-holes, layer changes, and crossing over different power supply areas (that is, cross-Moat) are often generated on the motherboard, resulting in Unpredictable noises and disturbances. In the era of low computer operating frequency in the past, its impact is acceptable. However, now entering the high-frequency era, these problems often cause customers to request to re-determine the pin position, which causes a huge loss in product development time and cost.

Therefore, in the implementation process of the present invention, after determining the number of pins, the research and development engineer will first consider the difference in the arrangement of the pins of the first slot and the second slot to determine the number of pins in the first slot and the second slot. Two-slot placement. When the first slot is placed upright and the second slot is placed upside down, the arrangement of the two pins will be similar and corresponding to a certain extent. Therefore, a pin definition correspondence table (as shown in FIG. 5 ) of the chip pins of the north bridge chip can be ordered.

Please refer to Figure 6 and Figure 7. FIG. 6 is a schematic diagram of the first plane 24 of the motherboard 22 of the computer system 10 of the present invention. FIG. 7 is a schematic diagram of the second plane 26 of the motherboard 22 of the computer system 10 of the present invention. The computer system 10 further includes a motherboard 22 , wherein the first socket 12 , the second socket 14 , the north bridge chip 16 , the control circuit 18 and a detection circuit 20 are installed on the first plane 24 of the motherboard 22 . The pins of the north bridge chip used to control the memory are connected to the first slot 12 and the second slot 14 via the conduction path 28 on the motherboard 22 .

In order to use the fewest through holes and the smoothest routing on the motherboard during the circuit layout process, so that the loss of the signal when traveling on the motherboard is minimized, the present invention divides the pin definition into three groups Groups are defined as groups for data pins, groups for address pins, and groups for command pins (as shown in FIG. 3 ). Among them, the signals generated by the pins belonging to the same pin definition group have a certain degree of similarity, so they can be interchanged in the most smooth way. For example, since MD[0:63] and DM[0:7] belong to the same pin definition group, their routing can be interchanged in the most smooth way. For example, MD 63 of DDR is MD 32 in SDR, and DM0 of SDR is MD 37 in DDR. Likewise, A[0:12], BA[0:1], SCAAJ, SRASJ, and SWEAJ are interchangeable on the trace. For example, A3 of DDR is A7 in SDR, and SCASJ of SDR is SWEAJ in DDR. The same is true for CS[0:5] and CKE[0:5].

As shown in FIG. 6 and FIG. 7 , the chip pins corresponding to the defined group of data pins in the north bridge chip 16 are connected to the first slot 12 and the second socket 12 via the conduction path 28 installed on the first plane 24 of the motherboard 22 . Second slot 14. The chip pins corresponding to the address pin definition group and the command pin definition group in the north bridge chip 16 are connected to the first slot 12 and the second socket 12 through the conduction path 28 installed on the second plane 26 of the motherboard 22. Slot 14. In addition, generally speaking, on the routing of the circuit layout, the outer three rows of pins in the chip can be routed on the front of the motherboard to avoid noise caused by unnecessary through-holes, layer changes, and cross-Moat. uncertain factors. Since the signal of the DRAM is a high-frequency action, the present invention will belong to the pins of the data pin definition group (MD[0:63], DM[0:7], DQS[0:7], etc. 80 pins), all arranged in the first three rows, so that it can be routed on the front (component side) of the motherboard, and the pins belonging to the address pin definition group and the command pin definition group (A[ 0:12], BA[0:1], SCASJ, SRASJ, SWEAJ, CS[0:5], CKE[0:5]) are arranged in the last three rows so that they can be routed on the back (solder side).

However, since the 80 pin signals are all routed to the front side, the routing area will be too large. Therefore, during the implementation process, the R&D engineers will divide the 80 pin signals into 8 groups. For example, draw ten pin signals such as MD[0:7], DM[0], DQS[0] as the first group (group 0), and MD[8:15], DM[1], Ten signals such as DQS[1] are drawn as the second group (group 1), and so on. Then, the R&D engineers will make the same number of through holes and layer changes in each group, so that the signal characteristics of each group are more consistent, that is, there are also noises, and the interference is similar, so Reduce the degree of influence, and reduce the trace area. That is to say, the data pin definition group is further divided into eight data pin definition subgroups, so that the chip pins corresponding to each data pin definition subgroup in the north bridge chip 16 have similar signal characteristics, to reduce the degree of impact.

Compared with known technology, computer system 10 of the present invention has 184pin DIMM and 168pin DIMM two kinds of slots with different pin definition simultaneously, and the chip pin of its north bridge chip 16 is the pin definition corresponding to 184pin DIMM respectively and 168pin DIMM pin definition, so it can support double data DRAM and synchronous DRAM at the same time. Therefore, during the market transition from SDRAM and 168pin DIMMs to DDRAM and 184pin DIMMs, users do not need to worry about specification selection and upgrades.

The above descriptions are only preferred embodiments of the present invention, and all changes and modifications made within the scope of the present invention are within the protection scope of the present invention.

Claims (14)

1. A computer system for supporting a first type of dynamic random access memory and a second type of dynamic random access memory, comprising: A motherboard, including a first plane and a second plane; A first slot, installed on the first plane of the motherboard, used to install the first type of dynamic random access memory, the first slot includes a plurality of first slot pins, each first slot The slot pin is defined corresponding to a first pin; A second slot, installed on the first plane of the motherboard, used to install the second type of dynamic random access memory, the second slot includes a plurality of second slot pins, each second slot The slot pin is defined corresponding to a second pin; Multiple conduction paths; A north bridge chip is installed on the first plane of the motherboard, and it includes a plurality of chip pins, which are connected to the first slot and the second slot via the conduction path, and each chip pin is corresponding to a first slot. a pin definition and a second pin definition; and A control circuit, installed on the first plane of the motherboard and connected to the north bridge chip, is used to set the pin definition of the chip pin; Wherein, the control circuit inputs a first control signal into the north bridge chip, and the pin definition of the chip pin will be set as the first pin definition, so that the north bridge chip can be connected with the first type of dynamic random access memory Carry out data transmission; the control circuit inputs a second control signal into the north bridge chip, and the pin definition of the chip pin will be set to the second pin definition, so that the north bridge chip can communicate with the second type of dynamic random memory Take memory for data transfer. 2. The computer system as claimed in claim 1, wherein the first type of DRAM is a double data DRAM, and the second type of DRAM is a synchronous DRAM access memory. 3. The computer system as claimed in claim 2, wherein the first slot is a double-line memory module slot with 184 pins, and the second slot is a double-line memory module slot with 168 pins line memory component slot. 4. The computer system according to claim 1, wherein the first pin definitions corresponding to the first socket pins respectively belong to a plurality of pin definition groups, and the corresponding pin definitions of the second socket pins The second pin definition also belongs to the plurality of pin definition groups, and the first pin definition and the second pin definition corresponding to each chip pin belong to the same pin definition group. 5. The computer system as claimed in claim 4, wherein the pin definition groups are respectively a data pin definition group, an address pin definition group, and a command pin definition group. 6. The computer system as claimed in claim 5 , wherein the chip pins corresponding to the data pin definition group in the north bridge chip are connected to the first socket via a conductive path mounted on the first plane of the motherboard. slot and a second slot, and the chip pins corresponding to the address pin definition group and the command pin definition group in the North Bridge chip are connected to the motherboard through the conduction path installed on the second plane first slot and second slot. 7. The computer system as claimed in claim 5, wherein the data pin definition group is further divided into eight data pin definition subgroups, and a chip corresponding to each data pin definition subgroup in the north bridge chip The pins have similar signal characteristics. 8. The computer system as claimed in claim 1, further comprising a detection circuit electrically connected to the control circuit, the detection circuit detects that the first type of dynamic random access memory is installed in the first slot, the detection The circuit will transmit a first detection signal to the control circuit, so that the control circuit transmits the first control signal to the north bridge chip, so that the pin definition of the chip pin is set as the first pin definition; the detection circuit When detecting that the second type of dynamic random access memory is installed in the second slot, the detection circuit will transmit a second detection signal to the control circuit, so that the control circuit transmits the second control signal to the north bridge chip , to set the pin definition of the chip pin as the second pin definition. 9. A computer system for supporting a double data DRAM and a synchronous DRAM, comprising: A motherboard, including a first plane and a second plane; A first slot, installed on the first plane of the motherboard, used to install the double data DRAM, the first slot includes a plurality of first slot pins, each first slot The pins correspond to a first pin definition, and the first pin definition respectively belongs to multiple pin definition groups; A second slot, installed on the first plane of the motherboard, used to install the synchronous dynamic random access memory, the second slot includes a plurality of second slot pins, each second slot pin is corresponding to a second pin definition, and the second pin definition respectively belongs to the plurality of pin definition groups; Multiple conduction paths; A north bridge chip is installed on the first plane of the motherboard, and it includes a plurality of chip pins, which are connected to the first slot and the second slot via the conduction path, and each chip pin is corresponding to a first slot. a pin definition and a second pin definition, and the first pin definition and the second pin definition belong to the same pin definition group; and A control circuit, installed on the first plane of the motherboard and connected to the north bridge chip, is used to set the pin definition of the chip pin; Wherein, the control circuit inputs a first control signal into the north bridge chip, and the pin definition of the chip pin will be set as the first pin definition, so that the north bridge chip can communicate with the double data dynamic random access memory. data transmission; and when the control circuit inputs a second control signal into the north bridge chip, the pin definition of the chip pin will be set to the second pin definition, so that the north bridge chip can be synchronized with the synchronous dynamic random access memory for data transfer. 10. The computer system as claimed in claim 9, wherein the first socket is a double line memory module socket with 184 pins, and the second socket is a memory module socket with 168 pins Double line memory component socket. 11. The computer system as claimed in claim 9, wherein the pin definition groups are respectively a data pin definition group, an address pin definition group, and a command pin definition group. 12. The computer system as claimed in claim 9, further comprising a detection circuit electrically connected to the control circuit, the detection circuit detects that the first type of dynamic random access memory is installed in the first slot, the detection The circuit will transmit a first detection signal to the control circuit, so that the control circuit transmits the first control signal to the north bridge chip, so that the pin definition of the chip pin is set as the first pin definition; the detection circuit detecting that the second type of dynamic random access memory is installed in the second slot, the detection circuit will transmit a second detection signal to the control circuit, so that the control circuit transmits the second control signal to the north bridge chip, The pin definition of the chip pin is set as the second pin definition. 13. The computer system as claimed in claim 11 , wherein the chip pins corresponding to the data pin definition group in the north bridge chip are connected to the first socket via a conductive path mounted on the first plane of the motherboard. slot and a second slot, and the chip pins corresponding to the address pin definition group and the command pin definition group in the North Bridge chip are connected to the motherboard through the conduction path installed on the second plane the first slot and the second slot. 14. The computer system as claimed in claim 11 , wherein the data pin definition group is further divided into eight data pin definition subgroups, and a chip corresponding to each data pin definition subgroup in the north bridge chip The pins have similar signal characteristics.

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