CN111274162B - Dual in-line memory module device of storage-level memory and data access method - Google Patents
Dual in-line memory module device of storage-level memory and data access method Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
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Abstract
本发明涉及储存级存储器SCM的双列直插式存储模块DIMM装置及访问数据方法。本发明的装置及读写数据方法能够增加装置的内存空间、提高装置的速率性能、降低印刷电路板设计难度且使主机能够以低的开销访问非易失性存储器。
The present invention relates to a dual in-line memory module (DIMM) device of a storage class memory (SCM) and a method for accessing data. The device and the method for reading and writing data of the present invention can increase the memory space of the device, improve the speed performance of the device, reduce the difficulty of printed circuit board design, and enable a host to access a non-volatile memory with low overhead.
Description
Technical Field
The present invention relates to the field of memory. More particularly, the present invention relates to Dual In-line Memory Module Dual In-line memory module DIMM devices and methods of accessing data for storage level memories SCM (Storage Class Memory).
Background
The dual inline memory module DIMM of the storage level memory SCM is a new type of dual inline memory module, on which there is memory space accessible in storage form.
A schematic diagram of signal flow and interface in a dual inline memory module DIMM of a storage level memory SCM is shown in fig. 1. In fig. 1, with a fork (stub) signal, a host (host) or a central processing unit CPU (Central Processing Unit) can access a dynamic random access memory DRAM (Dynamic Random Access Memory) and a controller such as a nonvolatile controller NVC (Non-Volatile Controller) in normal operation, and achieve the purpose of accessing the nonvolatile memory such as NAND FLASH via the access controller, thereby increasing the memory space of the system.
The fork signal particularly shows that there is a fork (stub) signal after the Command/Address CA (Command/Address) signal is output from the DIMM slot (slot), which is connected to the register clock driver RCD (Register Clock Driver) and the controller, respectively, and that there is a fork signal also between the data buffer DB (Data Buffer) and the dynamic random access memory DRAM. The bifurcated signal has great difficulty in realizing high-speed signals by the printed circuit board, because the feedback of the high-speed signals can cause interference to the signals of the other path, and the speed performance is affected.
Another solution for removing the bifurcation signal, which is known in the prior art, is shown in fig. 2. In fig. 2, the command/address CA signal and the data DQ signal enter the controller first, omitting the fork signal shown in fig. 1. However, in the case shown in fig. 2, there are two problems as follows:
first, the data DQ signals are drive-enhanced through the data buffer DB, but it is more difficult to hold and transfer the drive-enhanced signals to a nonvolatile memory such as NAND FLASH on-chip after entering the controller.
Second, the high-speed data DQ signals are on both sides of the DIMM slot, making it difficult to achieve equal length connections between the high-speed data DQ signals and the controller when routed on the printed circuit board. However, the unequal lengths of the high-speed parallel signals result in different times for the signals to reach the destination, and also in reduced rate performance.
Accordingly, there is a need for a dual inline memory module DIMM device and method of accessing data for a storage level memory SCM that addresses the above-described problems.
Disclosure of Invention
The present invention relates to a dual inline memory module DIMM device and method of accessing data that can increase the memory space of the device, improve the rate performance of the device, reduce the difficulty of printed circuit board design, and enable a host to access the storage level memory SCM of a non-volatile memory with low overhead.
According to a first aspect of the present invention there is provided a dual in-line memory module arrangement for a storage class memory comprising:
a first storage area storing data having a first range of host access frequencies, an
A second storage area storing data having a second range of host access frequencies;
Wherein the first range host access frequency is greater than the second range host access frequency.
Thus, the memory area of the dual inline memory module apparatus is divided into a "hot zone" (i.e., a first memory area) where the host or central processing unit frequently reads and writes and a "cold zone" (i.e., a second memory area) where the host or central processing unit does not frequently read and write, and the processing speed of the "hot zone" is relatively fast and the processing speed of the "cold zone" is relatively slow. In this way, the rate performance of the modular device can be improved.
In a preferred embodiment of the dual in-line memory module arrangement of the storage class memory according to the invention, the data with the second range of host access frequencies is stored in the second memory area indirectly via the first memory area.
Thus, the present invention specifies a method of accessing a "cold zone" (i.e., the second storage area), i.e., the need to access the "cold zone" via a "hot zone" (i.e., the first storage area), by accessing the "cold zone" to increase the memory space of the device.
In a preferred embodiment of the dual in-line memory module arrangement of the storage class memory according to the invention, the first memory area comprises a predetermined size of memory space for data having a second range of host access frequencies.
Preferably, the size of these memory spaces is each greater than 64KB. In developing the size of these memory spaces, factors to be considered are, for example, the data rate at which the host accesses the dynamic random access memory DRAM, the data rate at which the controller accesses the dynamic random access memory DRAM, and the data rate at which the controller accesses the nonvolatile memory such as NAND FLASH.
In a preferred embodiment of the dual in-line memory module arrangement of the storage class memory according to the invention, the second memory area comprises a plurality of sub-memory areas, each storing data having a different range of host access frequencies.
In a preferred embodiment of the dual in-line memory module arrangement of the storage class memory according to the invention, the second memory area comprises two sub-memory areas:
A first sub-storage area storing data having a first sub-range host access frequency;
A second sub-storage area storing data having a second sub-range host access frequency;
wherein the first sub-range host access frequency is greater than the second sub-range host access frequency.
In a preferred embodiment of the dual in-line memory module arrangement of the storage class memory according to the invention, the first storage area is a plurality of dynamic random access memories.
Since the processing speed of the dynamic random access memory is relatively high, the speed performance of the module device can be improved by storing the data frequently read and written by the host or the central processing unit in the dynamic random access memory.
According to a preferred embodiment of the dual in-line memory module arrangement of the storage class memory according to the invention, the first sub-storage area is a dynamic random access memory cache module and the second sub-storage area is a non-volatile memory.
Thus, data in "cold data" having a relatively high host access frequency is written to the dynamic random access memory cache module, and data in "cold data" having a relatively low host access frequency is written to the nonvolatile memory. In this way, the rate performance of the device is further improved and frequent access to the non-volatile memory is avoided, thereby avoiding damage to the non-volatile memory.
A preferred embodiment of the dual in-line memory module arrangement of a storage class memory according to the invention further comprises:
and the controller is respectively connected with the dynamic random access memory cache module and the nonvolatile memory.
The dual in-line memory module apparatus of the storage class memory according to the present invention further comprises:
and the clock driver is connected with the controller.
According to a preferred embodiment of the dual in-line memory module device of the storage class memory of the present invention, in response to a host writing data having a second range of host access frequencies to one or more of the plurality of dynamic random access memories and in response to the controller receiving an address of the host notified by the host via a system management bus of the data having the second range of host access frequencies, the controller sends a get data command to one or more of the plurality of data buffers to command one or more of the plurality of data buffers to get the data having the second range of host access frequencies from one or more of the plurality of dynamic random access memories and to send the data having the second range of host access frequencies to the controller, and
In response to receiving the data having the second range of host access frequencies, the controller writes the data having the second range of host access frequencies to the dynamic random access memory cache module or the non-volatile memory.
Thus, the host can access the controller during normal operation, and by writing data having a second range of host access frequencies to the controller, the memory space of the device is increased. In addition, writing data that is not frequently accessed by the host (i.e., cold data) to the dynamic random access memory cache module or the non-volatile memory can improve the rate performance of the device.
According to a preferred embodiment of the dual in-line memory module device of the storage class memory of the invention, the clock driver is connected to the controller via a local command bus, the clock driver is connected to each of the plurality of data buffers via a data buffer command bus, and the plurality of data buffers are each connected to the controller via a local data bus.
According to a preferred embodiment of the dual in-line memory module device of the storage class memory of the present invention, the controller sends the get data command to one or more of the plurality of data buffers via the local command bus and the data buffer command bus.
According to a preferred embodiment of the dual in-line memory module arrangement of the storage class memory of the invention, one or more of the plurality of data buffers transmits the data having the second range of host access frequencies to the controller via the local data bus.
Therefore, the design difficulty of the printed circuit board of the device is reduced. At the same time, the cache is employed to balance the rate difference between the non-volatile memory and the memory, so that the non-volatile memory can be accessed stably with low overhead.
According to a preferred embodiment of the dual in-line memory module arrangement of the storage class memory of the present invention, the controller writes data having the host access frequency of the first sub-range into the dynamic random access memory cache module, and the controller writes data having the host access frequency of the second sub-range into the non-volatile memory.
According to a preferred embodiment of the dual in-line memory module device of the storage class memory of the present invention, the host writes data directly to one or more of the plurality of dynamic random access memories via one or more of the plurality of data buffers.
Therefore, the host and the controller can be prevented from being connected with high-speed signals at the same time, and difficulty is not brought to the design of the printed circuit board.
In accordance with a preferred embodiment of the dual in-line memory module apparatus of the storage class memory of the present invention, in response to receiving an address of data having a second range of host access frequencies notified by a host via a system management bus, the controller reads the data having the second range of host access frequencies from the dynamic random access memory cache module or the non-volatile memory and sends a write data command to one or more of the plurality of data buffers to command one or more of the plurality of data buffers to retrieve the data having the second range of host access frequencies from the controller and then write the data having the second range of host access frequencies into one or more of the plurality of dynamic random access memories, and
The host reads data from one or more of the plurality of dynamic random access memories.
According to a preferred embodiment of the dual in-line memory module device of the storage class memory of the invention, the clock driver is connected to the controller via a local command bus, the clock driver is connected to each of the plurality of data buffers via a data buffer command bus, and the plurality of data buffers are each connected to the controller via a local data bus.
According to a preferred embodiment of the dual in-line memory module device of the storage class memory of the present invention, the controller sends write data commands to one or more of the plurality of data buffers via the local command bus and the data buffer command bus.
According to a preferred embodiment of the dual in-line memory module arrangement of the storage class memory of the invention, one or more of the plurality of data buffers obtains the data having the first range of host access frequencies from the controller via the local data bus.
Therefore, the design difficulty of the printed circuit board of the device is reduced. At the same time, the cache is employed to balance the rate difference between the non-volatile memory and the memory, so that the non-volatile memory can be accessed stably with low overhead.
According to a preferred embodiment of the dual in-line memory module arrangement of the storage class memory of the present invention, the controller reads the data having the host access frequency of the first sub-range from the dynamic random access memory cache module, and the controller reads the data having the host access frequency of the second sub-range from the non-volatile memory.
According to a preferred embodiment of the dual in-line memory module arrangement of the storage class memory of the present invention, the host reads data directly from one or more of the plurality of dynamic random access memories via one or more of the plurality of data buffers.
Therefore, the host and the controller can be prevented from being connected with high-speed signals at the same time, and difficulty is not brought to the design of the printed circuit board.
According to a preferred embodiment of the dual in-line memory module arrangement of the storage class memory according to the invention, the wiring of the printed circuit board between the plurality of dynamic random access memories and the plurality of data buffers is of equal length.
Thus, the time for the signal to reach the destination is not caused to be different, and the rate performance is further improved.
According to a second aspect of the present invention there is provided a method of accessing data for a dual in-line memory module arrangement of a storage class memory, the dual in-line memory module arrangement comprising a first memory area and a second memory area;
The data access method comprises the following steps:
Storing data having a first range of host access frequencies in a first storage area, and
Storing data having a second range of host access frequencies in a second storage area;
Wherein the first range host access frequency is greater than the second range host access frequency.
According to a preferred embodiment of the method of accessing data according to the present invention, the method of accessing data further comprises:
The data having the second range of host access frequencies is stored in the second storage area indirectly via the first storage area.
According to a preferred embodiment of the method of accessing data according to the invention, said first memory area comprises a predetermined size of memory space for data having a second range of host access frequencies.
According to a preferred embodiment of the method of accessing data according to the present invention, said second storage area comprises a plurality of sub-storage areas;
the method for accessing data further comprises the following steps:
data having different ranges of host access frequencies are each stored in the plurality of sub-storage areas.
According to a preferred embodiment of the method of accessing data according to the present invention, the second storage area comprises two sub-storage areas, the two sub-storage areas being a first sub-storage area and a second storage area;
the method for accessing data further comprises the following steps:
storing data having a first sub-range of host access frequencies in the first sub-storage area, and
Storing data having a second sub-range host access frequency in the second sub-storage area;
wherein the first sub-range host access frequency is greater than the second sub-range host access frequency.
According to a preferred embodiment of the method for accessing data according to the invention, said first memory area is a plurality of dynamic random access memories.
According to a preferred embodiment of the method for accessing data according to the invention, said first sub-storage area is a dynamic random access memory cache module and said second sub-storage area is a non-volatile memory.
According to a preferred embodiment of the method for accessing data according to the present invention, the dual inline memory module apparatus further comprises a controller;
the method for accessing data further comprises the following steps:
and respectively connecting the controller with the dynamic random access memory cache module and the nonvolatile memory.
According to a preferred embodiment of the method of accessing data according to the present invention, the dual in-line memory module device further comprises a clock driver;
the method for accessing data further comprises the following steps:
And connecting the clock driver with the controller.
According to a preferred embodiment of the method of accessing data according to the present invention, the method of accessing data further comprises:
Responsive to a host writing data having a second range of host access frequencies to one or more of the plurality of dynamic random access memories and responsive to the controller receiving, via a system management bus, an address of the host-notified data having the second range of host access frequencies, the controller sending a get data command to one or more of the plurality of data buffers to command one or more of the plurality of data buffers to get the data having the second range of host access frequencies from one or more of the dynamic random access memories and to send the data having the second range of host access frequencies to the controller, and
In response to receiving the data having the second range of host access frequencies, the controller writes the data having the second range of host access frequencies to the dynamic random access memory cache module or the non-volatile memory.
According to a preferred embodiment of the method of accessing data according to the present invention, the method of accessing data further comprises:
The clock driver is connected with the controller via a local command bus;
the clock driver being connected to each of the plurality of data buffers via a data buffer command bus, and
The plurality of data buffers are each connected with the controller via a local data bus.
According to a preferred embodiment of the method of accessing data according to the present invention, the method of accessing data further comprises:
the controller sends the get data command to one or more of the plurality of data buffers via the local command bus and the data buffer command bus.
According to a preferred embodiment of the method of accessing data according to the present invention, the method of accessing data further comprises:
one or more of the plurality of data buffers transmits the data having the second range of host access frequencies to the controller via the local data bus.
According to a preferred embodiment of the method of accessing data according to the present invention, the method of accessing data further comprises:
The controller writes data having the host access frequency of the first sub-range into the DRAM cache module, and
The controller writes data having the host access frequency of the second sub-range into the non-volatile memory.
According to a preferred embodiment of the method of accessing data according to the present invention, the method of accessing data further comprises:
The host writes data directly to one or more of the plurality of dynamic random access memories via one or more of the plurality of data buffers.
According to a preferred embodiment of the method of accessing data according to the present invention, the method of accessing data further comprises:
in response to receiving an address of data having a second range of host access frequencies notified by a host via a system management bus, the controller reads the data having the second range of host access frequencies from the dynamic random access memory cache module or the non-volatile memory and sends a write data command to one or more of the plurality of data buffers to command the one or more of the plurality of data buffers to retrieve the data having the second range of host access frequencies from the controller and then write the data having the second range of host access frequencies into the one or more of the plurality of dynamic random access memories, and
The host reads data from one or more of the plurality of dynamic random access memories.
According to a preferred embodiment of the method of accessing data according to the present invention, the method of accessing data further comprises:
The clock driver is connected with the controller via a local command bus;
the clock driver being connected to each of the plurality of data buffers via a data buffer command bus, and
The plurality of data buffers are each connected with the controller via a local data bus.
According to a preferred embodiment of the method of accessing data according to the present invention, the method of accessing data further comprises:
The controller sends a write data command to one or more of the plurality of data buffers via the local command bus and the data buffer command bus.
According to a preferred embodiment of the method of accessing data according to the present invention, the method of accessing data further comprises:
One or more of the plurality of data buffers obtains the data having the first range of host access frequencies from the controller via the local data bus.
According to a preferred embodiment of the method of accessing data according to the present invention, the method of accessing data further comprises:
The controller reads the data having the host access frequency of the first sub-range from the dynamic random access memory cache module, and
The controller reads the data having the host access frequency of the second sub-range from the non-volatile memory.
According to a preferred embodiment of the method of accessing data according to the present invention, the method of accessing data further comprises:
the host reads data directly from one or more of the plurality of dynamic random access memories via one or more of the plurality of data buffers.
According to a preferred embodiment of the method of accessing data according to the present invention, the method of accessing data further comprises:
Wiring of a printed circuit board between the plurality of dynamic random access memories and the plurality of data buffers is set to be of equal length.
It will be appreciated by those skilled in the art that the technical effects as described in relation to the first aspect of the invention can be achieved according to the second aspect of the invention.
Drawings
The invention will be more readily understood from the following description taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a schematic diagram of the signal flow and interface in a dual in-line memory module DIMM of a storage class memory SCM of the prior art.
FIG. 2 is a schematic diagram of the signal flow and interface in a dual in-line memory module DIMM of another prior art storage class memory SCM.
Fig. 3 is a configuration in a dual in-line memory module DIMM of a storage level memory SCM according to one embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
Fig. 3 is a configuration in a dual in-line memory module DIMM of a storage level memory SCM according to one embodiment of the present invention.
In the configuration of fig. 3, the dynamic random access memory DRAM 301 and the controller 304 are able to be accessed during normal operation, and the purpose of accessing the nonvolatile memory such as NAND FLASH is achieved via the access controller 304, thereby increasing the memory space of the system.
In comparison with fig. 2, in the configuration of fig. 3, the data DQ signal and the command/address CA signal are improved in driving capability using the Zhong Qudong resistor RCD 305 and the data buffer DB 306, respectively. In addition, the host directly writes data into the DRAM 301 via the data buffer DB 306, avoiding the simultaneous connection of the host and the controller 304 with high-speed signals, without making the PCB design difficult. In addition, the wiring of the printed circuit board between the data buffer DB 306 and the dynamic random access memory DRAM 301 is also of equal length, which does not cause the arrival time of signals at the destination to be different, further improving the rate performance.
In addition, when the host needs to access the nonvolatile memory such as NAND FLASH to 302, the controller 304 is notified via the system management bus SMBus that it is to access the address segment of the nonvolatile memory such as NAND FLASH to 302, and the controller 304 uses a portion of the space of the DRAM 301 on the device as a buffer to effect the host's access to the nonvolatile memory such as NAND FLASH to 302.
Therefore, the design difficulty of the system printed circuit board is reduced, and meanwhile, the cache is adopted to balance the speed difference between the nonvolatile memory and the memory, so that the nonvolatile memory can be stably accessed with low cost.
The configuration of fig. 3 is described in further detail below.
As shown in fig. 3, the dual inline memory module DIMM of the storage level memory SCM includes a plurality of dynamic random access memory DRAM 301, nonvolatile memory such as NAND FLASH, 302, and dynamic random access memory DRAM Cache (Cache) module 303.
In the present invention, the dynamic random access memory DRAM 301 finally stores "hot data", while the nonvolatile memory such as NAND FLASH and the dynamic random access memory DRAM cache module 303 stores "cold data", and the dynamic random access memory DRAM cache module 303 stores data having a relatively high host access frequency among the "cold data", and the nonvolatile memory such as NAND FLASH stores data having a relatively low host access frequency among the "cold data".
In the present invention, "hot data" refers to data frequently accessed by a host or a central processing unit, and "cold data" refers to data not frequently accessed by a host or a central processing unit.
In the definition of "hot data" and "cold data", whether frequent accesses are defined according to a specific case is defined without a specific value.
The configuration as described in the present invention can improve the rate performance of the device and avoid frequent access to the non-volatile memory, thereby avoiding damage to the non-volatile memory.
As further shown in fig. 3, the dual in-line memory module DIMM of the storage class memory SCM includes a controller 304, a clock driver RCD 305, and a plurality of data buffers DB 306. The clock driver RCD 305 is connected to the controller 304 via a local command bus LCOM, the clock driver RCD 305 is connected to each of the plurality of data buffers DB 306 via a data buffer command bus BCOM, the data buffers DB 306 are each connected to the controller 304 via a local data bus LDQ.
The configuration of fig. 3 is further understood in conjunction with the process by which the host writes data to and reads data from the controller 304 or the dynamic random access memory DRAM cache module 303.
When a host writes data to a non-volatile memory such as NAND FLASH or dynamic random access memory DRAM cache module 303, the host first writes the data to one or more of the plurality of dynamic random access memory DRAMs 301. In the method of the present invention, this "data" is referred to as "cold data" because it is ultimately written to a nonvolatile memory such as NAND FLASH a 302 or a dynamic random access memory DRAM cache module 303.
It should be appreciated that the host may write hot data and cold data into the dynamic random access memory DRAM 301, the hot data being ultimately stored in the dynamic random access memory DRAM 301 and the cold data being ultimately stored in a non-volatile memory such as NAND FLASH or dynamic random access memory DRAM cache module 303. In the present invention, in each of the plurality of dynamic random access memory DRAMs 301, there is a buffer area reserved and having a fixed space size for buffering cold data.
Preferably, the size of the space of these buffers is each greater than 64KB. In developing the size of the space for these buffers, factors such as the data rate at which the host accesses the DRAM, the data rate at which the controller 304 accesses the DRAM, and the data rate at which the controller 304 accesses the nonvolatile memory such as NAND FLASH, 302, are considered.
After the host writes the cold data into one or more of the plurality of dynamic random access memory DRAMs 301, the controller 304 retrieves the "cold data" from one or more of the plurality of dynamic random access memory DRAMs 301 and writes these "cold data" into the non-volatile memory such as NAND FLASH and dynamic random access memory DRAM cache module 303 according to the caching algorithm.
In the present invention, the host is capable of directly writing data into one or more of the plurality of dynamic random access memory DRAMs 301 via one or more of the plurality of data buffer DBs 306, where the host has the operation control rights of the plurality of dynamic random access memory DRAMs 301.
Then, the host notifies the controller 304 via the system management bus SMBus of the address of the data having the host access frequency of the second range (i.e., the "cold data" that the host does not frequently access), and the controller 304 switches the operation control authority of the dynamic random access memory DRAM 301 from the host. Thereafter, the controller 304 sends the get data command to one or more of the plurality of data buffers DB 306 via the local command bus LCOM between the clock driver RCD 305 and the controller 304 and the data buffer command bus BCOM between the clock driver RCD 305 and each of the plurality of data buffers DB 306 to command one or more of the plurality of data buffers DB 306 to fetch the "cold data" from one or more of the plurality of dynamic random access memory DRAM 301 and send the "cold data" to the controller 304 via the local data bus LDQ. Finally, the controller 304 writes the "cold data" to the dynamic random access memory DRAM cache module 303 or the non-volatile memory such as NAND FLASH 302,302 according to a caching algorithm.
The general idea of the caching algorithm is to write data in the "cold data" having a first sub-range of host access frequencies (i.e., relatively high host access frequencies) into the dynamic random access memory cache module 303 and to write data in the "cold data" having a second sub-range of host access frequencies (i.e., relatively low host access frequencies) into the non-volatile memory 302.
When the host reads data from a nonvolatile memory such as NAND FLASH or the dynamic random access memory DRAM cache module 303, the host first notifies the controller 304 of an address of "cold data", the controller 304 reads "cold data" from the nonvolatile memory such as NAND FLASH 302 and the dynamic random access memory DRAM cache module 303 according to the address, and writes these "cold data" into one or more of the plurality of dynamic random access memory DRAMs 301, after which the host reads "cold data" from one or more of the plurality of dynamic random access memory DRAMs 301.
Specifically, the host first notifies the controller 304 via the system management bus SMBus of an address of data (i.e., "cold data") having a first range of host access frequencies, the controller 304 reads "cold data" from a nonvolatile memory such as NAND FLASH and a dynamic random access memory DRAM cache module 303 according to the address, and sends the write data command to one or more of the plurality of data buffers DB 306 via the local command bus LCOM between the clock driver RCD 305 and the controller 304 and the data buffer command bus BCOM between the clock driver RCD 305 and one or more of the plurality of data buffers DB 306 to command the one or more of the plurality of data buffers DB 306 to acquire the "cold data" from the controller 304 via the local data bus LDQ and then write the "cold data" into one or more of the plurality of dynamic random access memory DRAM 301. Finally, the host reads data from one or more of the plurality of dynamic random access memory DRAMs 301.
In addition, the dual inline memory module DIMM of the storage class memory SCM shown in FIG. 3 is of the typical NVDIMM-N type. Typical save_n signals between a host and a dual inline memory module DIMM of a storage class memory SCM are shown in fig. 3. The save_n signal is used to be pulled down by the host to notify the dual inline memory module NVDIMM to back up data when the system is abnormally powered down.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. It is to be understood that the scope of the invention is defined by the claims.
Claims (28)
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| CN202010230102.8A CN111274162B (en) | 2020-03-27 | 2020-03-27 | Dual in-line memory module device of storage-level memory and data access method |
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