CN100351827C - Pin sharing system - Google Patents

Abstract

The pin sharing system comprises an integrated circuit, a first device, a second device, a memory device, a first set of connections, a second set of connections, and a third set of connections. The integrated circuit comprises a first pin group and a second pin group. The first device includes a first set of data pins. The second device includes a set of input/output data address pins. The memory device includes a set of low address pins, a set of high address pins, and a set of memory data pins. The first group of wires connects the first group of data pins and the low address pin group to the first pin group. The second group of wires connects the memory data pin group and the input/output data address pin group to the second pin group. The second set of connections further includes a register coupled between the set of input/output data address pins and the second set of pins for temporarily storing a set of address information and subsequently transmitting the stored address information to the second device. The third group of wires connects the high address pin group and the register to the second pin group.

Description

pin sharing system

technical field

The present invention relates to a pin sharing system for sharing the lines connected between peripheral equipment and integrated circuits.

Background technique

With the rapid development of semiconductor manufacturing technology, the functions of general integrated circuits are becoming more and more complex, and some integrated circuits can even control many devices. However, when multiple devices are connected to the integrated circuit, a problem arises, that is, the number of externally connected pins of the integrated circuit is often insufficient due to the limitation of the integrated circuit packaging technology, so some pins must be designed to allow several devices to connect to each other. shared. Therefore, the pin-sharing system is a common structure in computers. A pin-shared system may consist of several peripherals, and an integrated circuit, usually a central processing unit. Each peripheral device is controlled by the integrated circuit, thus requiring different numbers of wires to connect the pins of the integrated circuit and the pins of the peripheral device to transmit signals. Since the pins of the integrated circuit are shared by several peripheral devices, it is necessary to avoid signal conflicts during transmission between the integrated circuit and the several peripheral devices.

For example, the technology disclosed in U.S. Patent No. 6,044,412, the pin sharing system can be applied between dynamic storage media (Dynamic Memory Device, such as: CD-ROM) and peripheral devices such as static storage media (StaticMemory Device, such as: ROM) . However, since the pins of several peripheral devices share the same wiring, several devices sharing the same wiring will not be able to communicate with the integrated circuit at the same time, so that multiple peripherals in this pin-sharing system are often limited by the shared wiring and are in a state. idle state. If some peripheral devices can be controlled by the integrated circuit while sharing wiring or pins, the overall performance of the computer system will be improved accordingly.

Contents of the invention

The present invention relates to a pin sharing system for sharing the lines connected between peripheral equipment and integrated circuits.

The pin sharing system includes an integrated circuit, a first device, a second device, a memory device, a first set of wires, a second set of wires, and a third set of wires. The integrated circuit includes a first pin group and a second pin group. The first device includes a first set of data pins. The second device includes a set of input and output data address pins. The memory device includes a set of low address pins, a set of high address pins and a set of memory data pins. The first set of wires connects the first set of data pins and the set of low address pins to the first set of pins. The second group of wires connects the memory data pin group and the I/O data address pin group to the second pin group. The second set of wiring also includes a register connected between the I/O data address pin and the second set of pins, and the register is used to temporarily store a set of address information, and then transmit the stored address information to the second device. A third set of wires connects the high address pin set and registers to the second set of pins.

This pin sharing system enables the integrated circuit to control more than one peripheral device at the same time, and enables several pins of the integrated circuit to be shared by several peripheral devices, so as to improve the efficiency of the use of peripheral devices and reduce the pins required by the integrated circuit number.

Description of drawings

FIG. 1 is a schematic diagram of a first embodiment of a pin sharing system of the present invention.

FIG. 2 is a schematic diagram of the integrated circuit of FIG. 1 .

FIG. 3 is a schematic diagram of a second embodiment of the pin sharing system of the present invention.

FIG. 4 is a schematic diagram of a third embodiment of the pin sharing system of the present invention.

Explanation of reference numbers

10: Pin sharing system 12: Integrated circuit

14: First device 16: Second device

18: memory device 20: first pin group

22: The second pin group 26: The first group of data pins

28: I/O data address pin 30: Low address pin

32: High address pin 34: Memory data pin

40: The first set of wiring 42: The second set of wiring

44: The third group of wiring 46: Register

50: Pin selection module 52: Control module

54: Arbiter 56: Memory controller

58: First device controller 60: Second device controller

66: The fourth group of wiring 68: The first logic gate

70: Second logic gate 72: Read pin

74: Write pin 76: Memory control pin

80: The third logic gate 82: Device control pin

221: IC address pin 222: IC data pin

223: IC control pin

281: Second device data input pin

282: Second device data output pin

283: Second device address pin

Detailed ways

Please refer to FIG. 1 , which is a schematic diagram of a first embodiment of a pin sharing system 10 of the present invention. The pin sharing system 10 includes an integrated circuit 12 , a first device 14 , a second device 16 , and peripheral devices such as a memory device 18 . The integrated circuit includes a first pin group 20 and a second pin group 22 . The first device 14 has a first set of data pins 26, the second device 16 has a set of I/O data address pins 28, and the memory device 18 includes a set of low address pins 30, a set of high address pins 32 and a set of Memory data pin 34.

The pin sharing system 10 according to the present invention has a first set of wires 40, a second set of wires 42, and a third set of wires 44 for connecting the integrated circuit 12 to the first device 14, the second device 16, and the memory device 18. . The first set of wires 40 connects the first set of data pins 26 and the set of lower address pins 30 to the first set of pins 20 . The second group of wires 42 is used to connect the memory data pin group 34 and the I/O data address pin group 28 to the second pin group 22 of the integrated circuit 12 . The second group of wires 42 also includes a register 46 connected between the I/O data address pin group 28 and the second pin group 22 for temporarily storing data and then latching the data. Wherein the group of I/O data address pins 28 includes a group of second device data input pins 281, a group of second device data output pins 282, and a group of second device address pins 283, and the register 46 is connected between the set of second device address pins 283 and the second set of pins 22 . The third group of wires 44 is used to connect the group of high address pins 32 and the register 46 of the second group of wires 42 to the second pin group 22 . Wherein, the second pin group 22 of the integrated circuit 12 may include a group of integrated circuit address pins 221 and a group of integrated circuit data pins 222, so that the second group of wires 42 is connected to the group of the second group of pins 22 IC data pins 222 , and the third group of wires 44 can be connected to the group of IC address pins 221 of the second pin group 22 .

Table 1 is a list of connection lines shared by each group of wires with the first device 14, the second device 16, and the memory device 18:

Table I

Please refer to Table 1. It can be seen from Table 1 that the first set of wires 40 , the second set of wires 42 , and the third set of wires 44 are shared by the first device 14 , the second device 16 , and the memory device 18 . In this pin-sharing system, the first device 14 and the second device 16 do not share any set of wires. The first set of wires 40 are shared by the lower address pins 30 of the memory device 18 and the data pins 26 of the first device 14 to transmit data to the first set of pins 20 of the integrated circuit 12 . The second set of wires 42 are shared by the memory data pins 34 of the memory device 18 and the I/O data address pins 28 of the second device 16 to transmit data to the set of IC data pins 222 of the second set of pins 22 . The third set of wires 44 connects the upper address pin 32 of the memory device 18 and the latch enable of the register 46 on the second set of wires 42 to the first set of IC address pins 221 of the second set of pins 22 . At this time, the first pin group of the integrated circuit 12 is shared by the first device 14 and the memory device 18, and the integrated circuit address pin 221 and the integrated circuit data pin 222 of the integrated circuit 12 are shared by the second device 16 and the memory device 18 .

Table 2 is the usage and signal comparison table of the pin sharing system 10 of the present invention.

Table II

According to the description in Table 2, the horizontal axis represents the usage status of the peripheral devices of the pin-sharing system 10 , and the vertical axis represents the signals transmitted in the three sets of wiring. When the memory device 18 is used, the first set of wires 40 is used to transmit low address signals, the second set of wires 42 is used to transmit memory data signals, and the third set of wires 44 is used to transmit high address signals to the memory device 18 . When the first device 14 is used, the first set of wires 40 is used to transmit data signals.

When there is data to be written into the second device 16, the second group of wires 42 is used to time-divisionally transmit data or address signals to the second device 16, and the third group of wires 44 is used to transmit an address latch command (AddressLatch Enable , ALE) to register 46. At this time, the second group of wires 42 transmits the address signal to the register 46 for registration at the first time, and waits for the address latch command, while the third group of wires 44 transmits the address latch command to the register 46 so that the address data can be transmitted to the set of second device address pins 283 of the second device 16 . At a second time, the second set of wires 42 transmits another data message to the set of second device data input pins 281 of the second device 16 . Since the first device 14 and the second device 16 have no common wires or pins, the first device 14 and the second device 16 of the pin-sharing system 10 can operate simultaneously.

Please refer to FIG. 2 , which is a schematic diagram of the integrated circuit 12 in FIG. 1 . The integrated circuit 12 is used to determine the usage sequence of the memory device (not shown), the first device (not shown) and the second device (not shown). The integrated circuit 12 includes a pin selection module 50 (Pin Mux Selection Module) and a control module 52 (Control Module). The control module 52 includes an arbiter 54 , a memory controller 56 , a first device controller 58 , and a second device controller 60 to determine the usage order of the peripheral devices. The pin selection module 50 is controlled by the arbiter 54 and connected to the first pin group 20 and the second pin group 22 to transmit the memory controller 56, the first device controller 58, and the second device controller 60 The control signal to the first pin group 20 and the second pin group 22 and through the first set of wiring (not shown), the second set of wiring (not shown) and the third set of wiring (not shown) and a plurality of signals to Peripherals communicate.

When the memory device is used, the Arbitrator 54 (Arbitrator) in the control module 52 will arbitrate (Arbitrate) the access (Access) pin selection module 50 by the memory controller 56, and the pin selection module 50 further connects the first group of wires 40 , the second set of wires 42 , and the third set of wires 44 are assigned to the memory controller 56 to transmit signals and control the memory device 18 .

When the memory device 18 is not in use, the arbitrator 54 (Arbitrator) in the control module 52 will arbitrate (Arbitrate) the first device controller 58 and the second device controller 60 to be available for use. At this time, the first device controller 58 can access the first device 14 , while the second device controller 60 can access the second device 16 . The pin selection module 50 further distributes the third group of wires 44 and the second group of wires 42 to the second device controller 60 and the second device 16, and distributes the first group of wires 40 to the first device controller 58 and the second device controller 58. A device 14 is provided so that the integrated circuit 12 can transmit signals to the first device 14 and the second device 16 simultaneously.

Please refer to FIG. 3 . FIG. 3 is a schematic diagram of a second embodiment of the pin sharing system 10 of the present invention. Compared with the previous embodiment, the fourth group of wires 66 , and the first logic gate 68 and the second logic gate 70 are further added in this embodiment. The fourth set of wires 66 connects the read pin 72 , the write pin 74 of the second device 16 and the memory control pin 76 of the memory device 18 to an integrated circuit control pin 223 of the second pin set 22 . The first logic gate 68 and the second logic gate 70 are located on the fourth set of wires 66 and connected to the read pin 72 and the write pin 74 respectively. In addition, the third group of wiring 44 originally used to connect the high address pin 32 and the register 46 to the second pin group 22 is further connected to the first logic gate 68 and the second logic gate 70 to control transmission to the second pin group. Read pin 72 , write pin 74 of device 16 .

Please refer to Table 3. Table 3 is a list of connection lines shared by each group of wires and the first device 14, the second device 16, and the memory device 18 in the second embodiment of the present invention:

Table three

Compared with the first embodiment, in the second embodiment, the fourth group of wiring 66 is further shared by the read pin 72, the write pin 74, and the memory control pin 76, so that the integrated circuit control of the second pin group 22 The pin 223 is shared by the second device 16 and the memory device 18 , and the fourth set of wires 66 is not connected to the first device 14 . The first pin group 40 of the integrated circuit 12 is shared by the first device 14 and the memory device 18, and the integrated circuit address pin 221 and the integrated circuit data pin 222 of the integrated circuit 12 are shared by the second device 16 and the memory device 18. The integrated circuit memory control pin 223 of the circuit 12 is shared by the second device 16 and the memory device 18 .

Please refer to Table 4, Table 4 is a comparison table of device usage and signals in the second embodiment of the present invention.

Table four

The horizontal axis of Table 4 represents the usage status of the peripheral devices of the pin-sharing system 10 , and the vertical axis represents the signals transmitted in the three sets of wiring. When the memory device 18 is used, the first set of wires 40 , the second set of wires 42 , and the third set of wires 44 are used to control the memory device 18 as previously described. The fourth set of wires 66 is used to transmit the memory control signal to the memory control pin 76 in this state. When the first device 14 is used, the first set of wires 40 is used to transmit data signals to the first device 14 . When the second device 16 is used, in addition to the signal transmission mechanism in the first embodiment, the third set of wires 44 further transmits the I/O read/write signals to the first logic gate 68 and the second logic gate 70 . The fourth set of wires 66 transmits the memory idle signal to the first logic gate 68 and the second logic gate 70 . The two groups of logic gates 68 and 70 determine the values of the input and output read and write signals and the memory control signal, and transmit the results of logic operations to the read pin 72 and the write pin 74 respectively. At this time, the integrated circuit 12 can still transmit signals to the first device 14 and the second device 16 at the same time.

Please refer to FIG. 4 , which is a schematic diagram of a third embodiment of the present invention. Compared with the first embodiment, the fourth group of wires 66 and the third logic gate 80 are further added in this embodiment. The fourth set of wires 66 connects a device control pin 82 of the second device 16 and a memory control pin 76 of the memory device 18 to an IC control pin 223 of the second pin set 22 . The third group of wires 44 is further connected to a third logic gate 80 , and the third logic gate 80 is further connected to a device control pin 82 of the second device 16 . The third set of wires 44 is further connected to the read pin 72 and the write pin 74 of the second device 16 .

The first device of the pin-sharing system according to the present invention can be an integrated electronic drive device (Integrated Device Electronic Device) with an integrated electronic interface, and the second device can be a microcontroller device (Micro Controller) that includes a microcontroller. Device), and the memory device can be a flash memory (Flash Memory).

Compared with the known pin-sharing system, the pin-sharing system enables the integrated circuit to control more than one peripheral device at the same time, and enables the pins of the integrated circuit to be shared by the peripheral devices, so as to improve the efficiency of using the peripheral devices.

Through the above detailed description of the preferred embodiments, it is hoped that the characteristics and spirit of the present invention can be described more clearly, and the scope of the present invention is not limited by the preferred embodiments disclosed above. On the contrary, the intention is to cover various modifications and equivalent arrangements within the scope of the appended claims of the present invention.

Claims (11)

1. A pin sharing system, the pin sharing system comprising: an integrated circuit comprising a first set of pins and a second set of pins; a first device comprising a first set of data pins; A second device, the second device includes a set of input and output data address pins; A memory device comprising a set of low address pins, a set of high address pins and a set of memory data pins; a first group of wires, connecting the first group of data pins and the group of low address pins to the first group of pins of the integrated circuit; A second set of wiring, connecting the set of memory data pins and the set of I/O data address pins to the second pin set of the integrated circuit, wherein the second set of wiring includes a register connected to the set of I/O Between the data address pin and the second pin group, a set of address information is temporarily stored, and when an address latch command is received, the stored set of address information is transmitted to the second device; and a third set of wires connecting the high address pins of the memory device with the latch instruction of the register of the second set of wires to the second set of pins of the integrated circuit, Wherein, the integrated circuit controls the order in which the first group of wires, the second group of wires and the third group of wires communicate a plurality of signals to the memory device, the first device and the second device, so that the integrated circuit can Simultaneously communicate with the first device and the second device. 2. The pin sharing system as claimed in claim 1, wherein the integrated circuit comprises: A control module, including a memory controller, a first device controller, and a second device controller, to determine the usage order of the memory device, the first device and the second device; and A pin selection module is connected to the control module to select the first group of wires, the second group of wires, or the third group of wires to transmit the plurality of signals. 3. The pin sharing system as claimed in claim 1, wherein the second group of pins includes a group of integrated circuit address pins and a group of integrated circuit data pins, and the second group of wiring is connected to the group of integrated circuit data pins. pins, and the third set of wires is connected to the set of integrated circuit address pins. 4. The pin sharing system as claimed in claim 1, wherein the group of I/O data address pins of the second device comprises a group of second device data input pins, a group of second device data output pins, and A group of second device address pins, the register is connected between the group of second device address pins and the second group of pins. 5. The pin sharing system as claimed in claim 1 , further comprising a fourth set of wiring and a set of logic gates to connect a read pin of the second device, a write pin, and the memory device A memory control pin of the integrated circuit is connected to an integrated circuit control pin of the second pin group of the integrated circuit, and the group of logic gates is connected to the third group of wiring. 6. The pin sharing system as claimed in claim 1 , further comprising a fourth set of wires and a logic gate to connect a device control pin of the second device and a memory control pin of the memory device to the An integrated circuit control pin of the second set of pins of the integrated circuit, the logic gate and a read pin and a write pin of the second device are connected to the third set of wires. 7. The pin sharing system according to claim 5 or 6, the integrated circuit controls the first group of wiring, the second group of wiring, the third group of wiring and the fourth group of wiring to communicate a plurality of signals to the The sequence of the memory device, the first device and the second device enables the integrated circuit to communicate with the first device and the second device simultaneously. 8. The pin sharing system as claimed in claim 7, wherein the integrated circuit comprises: A control module, including a memory controller, a first device controller, and a second device controller, to determine the usage order of the memory device, the first device and the second device; and A pin selection module is used to select the first group of wires, the second group of wires, the third group of wires, or the fourth group of wires to transmit the plurality of signals. 9. The pin sharing system of claim 1, wherein the first device comprises an integrated electronic drive device. 10. The pin sharing system of claim 1, wherein the second device comprises a microcontroller device. 11. The pin sharing system of claim 1, wherein the memory device comprises a flash memory.

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