CN115579391A - Multi-channel fin structure and its preparation method - Google Patents

Abstract

The present application discloses a diamond-integrated multi-channel fin-type GaN device structure and a preparation method thereof, which improves the thermal management of the GaN device from two aspects of the device structure and materials. The structure adopts multi-heterojunction channel and FinFET device design, among which the multi-channel can provide greater current density and power, and the FinFET structure design can provide a larger heat dissipation area while enhancing gate control, which can prepared by corrosion process. Diamond with high thermal conductivity is introduced into the material, the diamond substrate is integrated through the bonding process, and a diamond cap layer with high thermal conductivity is grown between the gate fingers, which can effectively conduct the heat of the device from the upper and lower directions. A dielectric layer is designed between the multi-channel structure and the diamond cap layer and between the multi-channel structure and the gate to protect the surface of the multi-channel structure, reduce the damage caused by the growth of the diamond cap layer, and realize diamond oxygen plasma Etch self-stop while reducing gate leakage.

Description

Multi-channel fin structure and its preparation method

technical field

The present application relates to the technical field of microelectronic devices, in particular to a double-channel fin structure and a preparation method thereof.

Background technique

GaN materials have the characteristics of large band gap, high breakdown field strength, high mobility, and high electron saturation velocity. Due to the characteristics of spontaneous polarization and piezoelectric polarization of GaN-based materials, a high-concentration two-dimensional electron gas channel can be formed in the AlGaN/GaN heterostructure, and GaN high electron mobility transistors (HEMTs) can be prepared, which are suitable for radio frequency and field of power electronics. GaN HEMT devices often work under high voltage and high current conditions, and the self-heating effect of the device is significant, especially near the drain side under the gate, which will generate local hot spots during operation, causing electrical characteristic degradation and reliability problems.

Contents of the invention

Embodiments of the present application provide a multi-channel fin structure and a manufacturing method thereof, which are used to solve the technical problem of obvious self-heating effect of high electron mobility transistors in the prior art.

Multi-channel fin structures, including:

Substrate;

a multi-channel structure on the substrate;

a source/drain/gate located on the bottom channel layer in the multi-channel structure;

In the multi-channel structure, there is a fin structure located in the gate and between the gate and the drain, the fin structure includes a plurality of fins, and the depth of each fin penetrates the multi-channel from the top barrier layer to the bottom barrier layer of the channel structure;

a capping layer located between the source and the gate and on the multi-channel structure between the gate and the drain and between the fins;

The thermal conductivity of the substrate and the capping layer is higher than that of the multi-channel structure.

Further, the capping layer is also located outside the edge fins in the multi-channel structure.

Further, it also includes:

a medium layer,

located between the multi-channel structure and the capping layer,

and / or,

Located between the multi-channel structure and the gate.

Further, the material of the capping layer is diamond.

Further, the thickness of the capping layer is 180nm-250nm.

Further, the material of the dielectric layer is Al ₂ O ₃ .

Further, the thickness of the dielectric layer is 4nm-6nm.

Further, the multi-channel structure includes a multi-layer AlGaN/GaN heterojunction.

Further, the material of the substrate is diamond.

A second aspect of the present invention provides a method for preparing a multi-channel fin structure, including:

Prepare the Si substrate;

forming a multi-channel structure on the Si substrate;

grinding and etching the Si substrate and bonding a diamond substrate below the multi-channel structure;

A SiO ₂ mask layer is grown on the multi-channel structure and etched to form a groove, the SiO ₂ mask layer is located between the gate region and the gate and drain regions, and the SiO ₂ mask layer Layered fin distribution;

Etching the multi-channel structure below it along each fin of the _SiO2 mask layer until the bottom barrier layer;

Oxidizing the bottom barrier layer at a high temperature, then wet etching the bottom barrier layer and self-stopping on the surface of the channel layer at the bottom, so that the multi-channel structure forms a fin structure;

removing the SiO ₂ mask layer;

Form a dielectric layer completely covering the surface of all channel structures, and etch to remove the dielectric layer in the source and drain regions;

forming a capping layer completely covering the surface of the dielectric layer;

growing an Al ₂ O ₃ mask layer at a position between the source and drain regions on the capping layer and etching to form a pattern;

etching the cap layer at the position of the source-drain region and self-stopping on the surface of the dielectric layer;

Form the source/drain in the source-drain region and realize the ohmic contact;

forming grooves in the Al ₂ O ₃ mask layer in the gate region;

Etching the cap layer directly below the groove of the Al ₂ O ₃ mask layer and self-stopping on the surface of the dielectric layer;

a gate formed on the dielectric layer of the gate region;

_Etch the _Al2O3 mask layer above the source/drain/gate locations.

Beneficial effect

The present invention proposes a multi-channel fin structure and its preparation method. The structure adopts the structure design of multiple heterojunction channels and FinFET, wherein the multi-channel can provide greater current density and power; the FinFET structure design can While enhancing grid control, it provides a larger heat dissipation area, which can be prepared by oxidation wet etching process; introduces high thermal conductivity materials, preferably diamond materials, integrates diamond substrates by bonding, and grows diamond caps between grid fingers layer, which can effectively conduct heat from the top and bottom of the device; a dielectric layer is designed between the multi-channel structure and the capping layer and between the multi-channel structure and the gate to protect the surface of the multi-channel structure and reduce the growth of the diamond capping layer The damage caused by the process can realize the self-stopping of the oxygen plasma etching of the diamond layer, and at the same time reduce the gate leakage.

Description of drawings

The drawings constituting a part of the application are used to provide further understanding of the application, and the schematic embodiments and descriptions of the application are used to explain the application, and do not constitute an improper limitation to the application. In the attached picture:

Fig. 1 is the three-dimensional structure schematic diagram of the embodiment of the present application;

Fig. 2 is a schematic diagram of vertical cross-sectional positions perpendicular to the direction of the channel and along the direction of the channel on the schematic diagram of the three-dimensional structure of the embodiment of the application;

Fig. 3 is a schematic cross-sectional view at the position A-A1 perpendicular to the channel direction in Fig. 2 according to the embodiment of the present application;

Fig. 4 is a schematic cross-sectional view at the position B-B1 perpendicular to the channel direction in Fig. 2 according to the embodiment of the present application;

Fig. 5 is a schematic cross-sectional view at the position C-C1 perpendicular to the channel direction in Fig. 2 according to the embodiment of the present application;

Fig. 6 is a schematic cross-sectional view at the position D-D1 along the channel direction in Fig. 2 according to the embodiment of the present application;

Fig. 7 is a schematic cross-sectional view at the position E-E1 along the channel direction in Fig. 2 according to the embodiment of the present application;

FIG. 8 is a schematic diagram of a silicon substrate and a multi-channel structure in an embodiment of the present application;

FIG. 9 is a schematic diagram of the structure after removing the silicon substrate in the embodiment of the present application;

10 is a schematic diagram of a diamond substrate and a multi-channel structure in an embodiment of the present application;

Fig. 11 is the schematic diagram of the _SiO2 mask layer grown when making the Fin structure in the embodiment of the present application;

12 is a schematic diagram of Cl-based ICP etching when making a Fin structure in the embodiment of the present application;

FIG. 13 is a schematic diagram of wet oxidation and etching of the remaining AlGaN layer when the Fin structure is fabricated in the embodiment of the present application;

14 is a schematic diagram of removing the _SiO2 mask layer when making a Fin structure in the embodiment of the present application;

Fig. 15 is a schematic diagram of growing an Al ₂ O ₃ dielectric layer in the embodiment of the present application;

Figure 16 is a schematic diagram of growing a diamond cap layer in the embodiment of the present application;

17 is a schematic diagram of growing an Al ₂ O ₃ mask when making an ohmic contact in the embodiment of the present application;

Figure 18 is a schematic diagram of oxygen ICP etching diamond when making ohmic contacts in the embodiment of the present application;

Figure 19 is a schematic diagram of BOE etching to remove Al2O3 in the ohmic region when making ohmic contacts in the embodiment of the present application;

FIG. 20 is a schematic diagram of sputtering and growing source and drain metals when making ohmic contacts in the embodiment of the present application;

Figure 21 is a schematic diagram of forming a mask groove at the gate position by BOE etching Al ₂ O ₃ when making the gate metal in the embodiment of the present application;

FIG. 22 is a schematic diagram of depositing gate metal when fabricating the gate metal in the embodiment of the present application.

In the figure, the meanings of each reference sign are as follows:

First substrate 0; substrate 1; fin 2; multi-channel structure 3; first channel layer 3-1; bottom barrier layer 3-2; second channel layer 3-3; top barrier layer 3 -4; dielectric layer 4; source 5; drain 6; gate 7; cap layer 8; SiO ₂ mask layer 9; Al ₂ O ₃ mask layer 10.

detailed description

It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and embodiments.

For the convenience of description, spatial relation terms such as "below", "below", "below", "below", "above", "on" etc. may be used herein to describe an element or element shown in the drawings. The relationship of a feature to other components or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, structures described as having a first feature "on top of" a second feature may include embodiments where the first and second features are formed in direct contact, as well as additional features formed between the first and second features. Embodiments between the second feature such that the first and second features may not be in direct contact.

Aiming at the thermal management problem of traditional GaN devices, the embodiments of the present invention propose a multi-channel fin structure and a manufacturing method thereof. In order to meet the requirements of high voltage and high current, the embodiment of the present invention adopts a multi-channel design. In order to improve heat dissipation, starting from improving heat dissipation efficiency and improving gate control, specifically by setting a heat dissipation channel with a higher thermal conductivity than the multi-channel structure. The surface conducts heat from the inside of the device, a larger heat dissipation surface is provided to speed up heat dissipation, and a fin structure is provided for realization. Based on the above comprehensive means, as shown in Figure 1, it is a multi-channel fin structure according to the embodiment of the present application, which includes:

Substrate;

a multi-channel structure on the substrate;

a source/drain/gate located on the bottom channel layer in the multi-channel structure;

In the multi-channel structure, there is a fin structure located in the gate and between the gate and the drain, the fin structure includes a plurality of fins, and the depth of each fin penetrates the multi-channel from the top barrier layer to the bottom barrier layer of the channel structure;

The capping layer is located on the multi-channel structure between the source and the gate and between the gate and the drain and between the fins, and the thermal conductivity of the capping layer is higher than that of the multi-channel structure.

The fin structure is also called FinFET structure. In the traditional transistor structure, the gate that controls the flow of current can only control the on and off of the circuit on one side of the gate, which belongs to the planar structure. In the FinFET structure, the gate is formed into a fork-shaped 3D structure similar to a fish fin, which can control the on and off of the circuit on both sides of the circuit. This design can greatly improve circuit control and reduce leakage current, and can also greatly shorten the gate length of the transistor.

The embodiment of the present application utilizes the advantages of the above structure and applies the above structure to a high electron mobility transistor. The provided fin structure can improve the gate control ability of the multi-channel structure, and at the same time bring a larger heat dissipation area. The distribution of the above-mentioned fin structure realizes the use of a fin structure in the gate area to improve gate control, the use of a fin structure at the gate edge of the drain side to improve heat dissipation, and the use of planar trenches in the gate-source channel and the channel farther away from the drain side. The channel design reduces the channel on-resistance. In order to further improve the heat dissipation capability of the device, a cap layer with higher thermal conductivity is integrated. After the heat is transferred to the cap layer, the heat dissipation is faster because of the higher thermal conductivity. At the same time, the cap layer has a larger heat dissipation area and can dissipate heat faster.

In some embodiments, the above-mentioned multi-channel structure adopts a multi-layer AlGaN/GaN heterojunction, specifically, in the embodiment shown in FIG. 1, an AlGaN/GaN/AlGaN/GaN double heterojunction channel is used, Compared with a single-channel device, this structure can obtain a larger on-current, a wider high-transconductance region to improve the linearity of the device, and the lower channel current collapse phenomenon is improved. Among them, the bottom one is the first channel layer, which is composed of a buffer layer and a channel layer, and the material is AlGaN, wherein the buffer layer is on the bottom and the channel layer is on the top, and the thickness of the buffer layer is 4000nm, and the channel layer is 400nm. In some other embodiments, the first channel layer includes a nucleation layer, a buffer layer, and a channel layer, which are arranged in sequence from bottom to top, wherein the size and material of the buffer layer and the channel layer are the same as those mentioned above. The embodiment of the buffer layer and the channel layer are the same, the size of the nucleation layer is about 90nm, and the material is AlN, which can play a role in alleviating lattice mismatch. The bottom barrier layer immediately above the first channel layer is made of GaN and has a thickness of 10 nm. Immediately above the bottom barrier layer is a second channel layer made of AlGaN with a thickness of 10 nm. Immediately above the second channel layer is a top epitaxial layer made of GaN with a thickness of 20nm.

Based on the double heterojunction channel shown in Figure 1, one channel is far from the gate, and the gate control capability is poor. The FinFET structure can effectively improve the gate control capability of the dual-channel device, realize enhanced operation, increase the heat dissipation path of the device, and improve the thermal management of the device.

The existence of the fin structure makes the dimensions of each plane in the height direction in the multi-channel structure not completely the same, as shown in FIG. Not affected by the fin structure. The planar dimensions of the bottom epitaxial layer, the second channel layer, and the top barrier layer that exist sequentially above the first channel layer are smaller than the size of the first channel layer, partly due to the need to make room for The source and drain on both sides, on the other hand, need to leave a space between the fins between the source and the drain to form a fin structure. Similarly, the dimensions of the multi-channel structure at different sections in the length direction are not completely the same, as shown in Figures 3-5, and the dimensions of the multi-channel structure at different sections in the width direction are also Not exactly the same, as shown in Figure 6 and Figure 7. The space between the fins formed by the above-mentioned various cross-sectional changes has multiple sidewalls to increase the heat dissipation area. The space between the above-mentioned fins and the space between the top of the fin structure and the top of each electrode are filled with a capping layer, which guides heat to the capping layer, thereby reducing the channel temperature, especially the edge hot spot temperature of the drain side gate, and capping The upper surface of the layer is large to quickly conduct heat away from the device. In the embodiment shown in Figure 1, the width of the entire device is 10 μm, the distance between the source and the gate is 2 μm, and the distance between the gate and the drain is 13 μm, and the fin structure has 3 fins , the width of each fin is 2 μm, the length between the source and the gate is 2.5 μm, there is one inter-fin between two fins, and a total of two fins are formed, and the width between each fin is 1 μm. The length between the electrode and the gate is 2.5 μm.

The thermal conductivity of the above-mentioned capping layer is relatively high, and it is preferably made of diamond. Diamond is the material with the highest thermal conductivity in nature, generally 138.16W/(m·K).

Diamond can be divided into two types: type I diamond and type II diamond according to the trace elements contained in it. Among them, type II diamond has better thermal conductivity and semiconductor properties. The thermal conductivity of diamond material is 2200-3300W/mK, much higher than GaN, SiC and Si and other materials. In this embodiment, the peak temperature of the device can be reduced by 10% to 20%, and the thermal resistance of the device can be reduced by at most 30% by means of a GaN/diamond wafer or a diamond film passivation layer.

In some embodiments, the capping layer is also located outside the edge-located fins in the multi-channel structure. There is a part of space on the outside of the two fins located at the edge, and the width of each part of the space is 1 μm. The capping layer also fills the space located outside, so that the entire structure is regular, so that the multi-channel structure can be placed at each position. In contact with the capping layer, the heat is drawn away. The thickness of the capping layer at different positions in the above structure is different. In this embodiment, the thickness of the capping layer is 180nm-250nm, wherein the thickness from the top of the fin to the top of the device is about 180nm, the bottom between the fins and The thickness from the bottom of the outside of the fin to the top of the device is around 250nm.

In some embodiments, the above structure further includes: a dielectric layer located between the multi-channel structure and the capping layer, and/or located between the multi-channel structure and the gate. In some embodiments, the material of the dielectric layer is Al ₂ O ₃ , and the Al ₂ O ₃ dielectric layer plays three roles. One is to serve as a surface protection layer of the semiconductor material during the growth of the diamond cap layer, reducing The damage caused by the small growth process; the second is that the diamond oxygen plasma etching can self-stop on the Al ₂ O ₃ layer to avoid over-etching damage to the channel; the third is to reduce the gate leakage as a gate dielectric layer. In order to take into account both gate control capability and surface protection, the thickness is designed to be 4nm to 6nm.

In the above-mentioned embodiments, the heat inside the device is easily dissipated from above through the high thermal conductivity and large heat-conducting area of the surface. In some embodiments, heat can be further dissipated from the bottom of the device. Therefore, in these embodiments, The thermal conductivity of the substrate is higher than that of the multi-channel structure, and the substrate material is also made of diamond, so that the upper and lower sides cooperate with each other to obtain better heat dissipation effect.

Further, a method for preparing a multi-channel fin structure as shown in Figure 1 is given, including the following steps:

Step S101, preparing a first substrate.

Silicon is a common substrate material. In addition to silicon, it can also be made of gallium nitride, silicon carbide and other materials. In this embodiment, the first substrate is a silicon substrate with a thickness of 1000 μm.

Step S102, forming a multi-channel structure on the first substrate.

As shown in Figure 8, 4μm GaN buffer layer/400nm GaN channel layer/10nmAl _0.15 Ga _0.84 N bottom barrier layer/10nm GaN channel layer/20nm Al _0.3 Ga _0.7 N barrier layer are grown sequentially on the first substrate layers form a double heterojunction channel.

Step S103 , grinding and etching the first substrate, specifically by attaching a wafer on the front side of the wafer, then grinding to remove the Si substrate, and tearing the wafer. As shown in FIG. 9 , a second substrate is surface-bonded under the multi-channel structure, as shown in FIG. 10 . The diamond material with better heat dissipation effect is selected for the second substrate in this embodiment.

Prepare the Fin structure, including steps S104-S107.

Step S104, as shown in FIG. 11, grow a _SiO2 mask layer with a thickness of 50-70 nm on the multi-channel structure by means of plasma-enhanced chemical vapor deposition, and use reactive ion etching technology to form grooves as Fin The SiO ₂ mask layer is located between the gate region and the gate and drain regions, and the SiO ₂ mask layer is distributed in a fin shape.

Step S105, as shown in Figure 12, using Cl-based plasma dry etching to etch the groove area between the Fins until the last AlGaN barrier layer remains. In the actual preparation process, as shown in the figure, the etching Remove a certain thickness of the upper part of the last AlGaN barrier layer and retain a certain thickness of the lower part of the layer, that is, etch the multi-channel structure below it along each fin of the _SiO2 mask layer until the bottom barrier layer.

Step S106 , as shown in FIG. 13 , place the epitaxial wafer in an oxygen atmosphere at 620-680° C. for 100-120 minutes, and oxidize the bottom barrier layer at a high temperature. Under this condition, the GaN layer below the AlGaN layer will not be oxidized; then Wet etching the bottom barrier layer and self-stopping on the surface of the channel layer at the bottom, so that the multi-channel structure forms a fin structure; specifically, by placing the oxidized epitaxial wafer in TMAH or KOH at 70-90°C Etching in the solution for 100 to 120 minutes, the groove area is etched and stops at the lower GaN layer; the oxidation wet etching process can avoid over-etching of the GaN channel layer by dry etching and reduce damage to the channel. Complete the preparation of the Fin structure.

Step S107 , as shown in FIG. 14 , remove the SiO ₂ mask layer by BOE etching.

Step S108 , as shown in FIG. 15 , forming a dielectric layer completely covering the surface of all channel structures, and etching to remove the dielectric layer in the source and drain regions. Specifically, an Al ₂ O ₃ dielectric layer with a thickness of about 5 nm is deposited by ALD. The Al ₂ O ₃ dielectric layer on the surface of AlGaN can play a protective role in the subsequent growth of the cap layer material diamond, and play a self-stop role in the etching process of diamond, and a MIS structure can be formed under the gate to reduce gate leakage.

Step S109 , as shown in FIG. 16 , forming a capping layer completely covering the surface of the dielectric layer; specifically, a polycrystalline diamond capping layer with a thickness of about 300 nm is grown by microwave plasma chemical vapor deposition (MPCVD). The thermal conductivity of diamond is much higher than that of the GaN layer, providing an effective heat dissipation channel on the top of the device, which can effectively reduce the channel temperature.

Step S110 , as shown in FIG. 17 , grow an Al ₂ O ₃ mask layer on the capping layer between the source and drain regions and form a pattern by BOE etching.

Step S111 , as shown in FIG. 18 , using ICP oxygen plasma etching to etch the cap layer at the position of the source and drain regions and self-stop on the surface of the Al ₂ O ₃ dielectric layer.

Using ICP oxygen ion dry etching of diamond, using Al ₂ O ₃ as a mask layer, can obtain a higher etching ratio. At the same time, an Al ₂ O ₃ dielectric protection layer is introduced on the surface of AlGaN, which plays three functions at the same time: ① it acts as a gate dielectric in the area under the gate to reduce leakage; ② it plays a role of surface protection during the diamond growth process; It plays a self-stop function during the diamond etching process to prevent over-etching.

Step S112, as shown in Figure 19, form the source/drain electrodes in the source and drain regions and realize the ohmic contact, specifically grow the Ti/Al/Ni/Au metal stack by electron beam evaporation, and leave at the ohmic contact position after stripping The metal stack is followed by rapid annealing to form ohmic contacts.

Preparing the grid includes steps S113-S115.

Step S113, as shown in FIG. ₂₀ , photolithography, BOE etching of Al2O3, forming grooves in the _Al2O3 mask layer in the gate region;

Step S114, as shown in FIG. 21, ICP oxygen plasma etches the cap layer directly below the groove of the Al ₂ O ₃ mask layer and self-stops on the surface of the dielectric layer;

Step S115, as shown in FIG. 22, electron beam evaporation deposits the metal stack Ni/Au, leaves the gate metal after stripping, and forms the gate on the dielectric layer of the gate region;

Step S116, BOE etching the Al ₂ O ₃ mask layer higher than the source/drain/gate position.

The process of the above embodiment makes the top and bottom of the device are materials with good heat dissipation effect, and the wet etching process is used to ensure the integrity of the channel.

The above are only examples of the present application, and are not intended to limit the present application. For those skilled in the art, various modifications and changes may occur in this application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

Claims (10)

1. A multi-channel fin structure, comprising:

a substrate;

a multi-channel structure located over the substrate;

a source/drain/gate located on the bottom channel layer in the multi-channel structure;

a fin structure in the multi-channel structure within the gate and between the gate and the drain, the fin structure comprising a plurality of fins each having a depth that penetrates a top barrier layer to a bottom barrier layer of the multi-channel structure;

the cap layer is positioned above the multi-channel structure between the source electrode and the grid electrode and between the grid electrode and the drain electrode and between the fins;

the substrate and the cap layer have higher thermal conductivity than the multi-channel structure.

2. The structure of claim 1 wherein the cap layer is further located outside the marginally located fin in the multi-channel structure.

3. The structure of claim 1 or 2, further comprising:

a dielectric layer, a first dielectric layer and a second dielectric layer,

between the multi-channel structure and the cap layer,

and/or the presence of a gas in the gas,

located between the multi-channel structure and the gate.

4. The structure of claim 3, wherein the cap layer is made of diamond.

5. The structure of claim 4 wherein the cap layer has a thickness of 180nm to 250nm.

6. The structure of claim 3, wherein the dielectric layer is made of Al ₂ O ₃ 。

7. The structure of claim 6, wherein the dielectric layer has a thickness of 4nm to 6nm.

8. The structure of claim 3, wherein the multi-channel structure comprises a multilayer AlGaN/GaN heterojunction.

9. A structure according to any one of claims 4 to 6, wherein the substrate is diamond.

10. The preparation method of the multi-channel fin structure is characterized by comprising the following steps:

preparing a Si substrate;

forming a multi-channel structure on the Si substrate;

grinding and etching the Si substrate and bonding an alloy diamond substrate below the multi-channel structure;

growing SiO on the multi-channel structure ₂ Masking film layer and etching to form a groove, wherein the SiO is ₂ A mask layer arranged between the gate region and the gate and drain regions and made of SiO ₂ The mask layer is distributed in a fin mode;

along the SiO ₂ Etching a multi-channel structure below each fin of the mask layer until reaching the bottom barrier layer;

oxidizing the bottom barrier layer at high temperature, and then etching the bottom barrier layer by a wet method and stopping on the surface of the channel layer at the bottom, so that the multi-channel structure forms a fin structure;

removing the SiO ₂ A mask layer;

forming a dielectric layer which completely covers the surfaces of all the channel structures, and etching to remove the dielectric layer in the source drain region;

forming a cap layer completely covering the surface of the dielectric layer;

growing Al on the cap layer at the position between the source and drain regions ₂ O ₃ The mask layer is etched to form a pattern;

etching the cap layer at the position of the source-drain region and stopping on the surface of the dielectric layer;

forming a source/drain electrode in the source/drain region and realizing ohmic contact;

al formed in gate region ₂ O ₃ A mask layer groove;

etching the Al ₂ O ₃ The cover cap layer is arranged right below the mask layer groove and stops on the surface of the medium layer;

a gate formed over the dielectric layer of the gate region;

etching Al higher than source/drain/gate ₂ O ₃ And (5) masking the layer.

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