CN115274846A - High Electron Mobility Transistor - Google Patents

Abstract

The embodiment of the invention discloses a high electron mobility transistor, and belongs to the technical field of semiconductors. The invention protects a high electron mobility transistor, comprising: the semiconductor device includes a substrate, and a first channel layer and a first barrier layer sequentially formed on the substrate. And etching to form a first groove, wherein the first groove is provided with a bottom surface and a side wall. Forming a second channel layer on the first barrier layer, the sidewalls, and the bottom surface. And respectively etching the second channel layer to form a second groove and a third groove, filling the second groove and the third groove to form a source electrode and a drain electrode, and filling the first groove to form a grid electrode. According to the invention, the second channel layer is filled on the surface of the etched first channel layer by arranging the second channel layer, so that the influence of etching on the first channel layer is reduced, and meanwhile, the newly added second channel layer increases an electron transfer channel from a source electrode to a drain electrode, so that the electron mobility is improved.

Description

High Electron Mobility Transistor

technical field

The invention relates to the technical field of semiconductors, in particular to a high electron mobility transistor.

Background technique

Semiconductor (semiconductor material) is a class of electronic materials with semiconductor properties (conductivity between conductors and insulators, resistivity in the range of about 1mΩ·cm～1GΩ·cm), which can be used to make semiconductor devices and integrated circuits. Among them, power electronic devices are semiconductor devices used for power control and conversion, including metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs) and other transistors. Compared with traditional silicon materials, the new wide-bandgap semiconductor material Gallium Nitride (GaN) has great advantages, and its power electronic devices - High Electron Mobility Transistors (HEMTs) - have higher breakdown voltage, lower on-resistance, and less charge, ideal for high-speed power switching. Gallium nitride HEMT can shorten the dead time, thereby improving efficiency and realizing passive cooling. At the same time, its high switching frequency can reduce the size of passive devices, thereby improving the reliability and power density of the gallium nitride solution.

Power electronic transistors are usually used as switches in circuits and are required to have a normally off (e-mode or normally-off) characteristic. Existing gallium nitride HEMTs mainly realize normally-off characteristics through a P-type gate structure. Referring to FIG. 1, this structure adds a p-gallium nitride channel layer 108 above the aluminum gallium nitride barrier layer 102 in the region of the gate 107 to deplete the two-dimensional electron gas to achieve normally-off characteristics, with high electron mobility, Advantages such as low interface state density; however, the lack of a gate insulating layer in this structure leads to problems such as low breakdown voltage from source 101 to gate 107 and large leakage current, making it difficult to control devices with a P-type gate structure , Low gate reliability and other issues.

In view of the shortcomings of the P-type gate structure, a normally-off GaN HEMT can be realized through a recessed gate structure. Referring to FIG. Or full etching to remove the two-dimensional electron gas, and then deposit the gate insulating layer 202 by low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), etc., and finally obtain a high gate breakdown voltage, low Normally-off GaN HEMT with gate leakage. However, the etching in this technology will cause damage to the AlGaN barrier layer 203 and the channel layer 204, resulting in reduced electron mobility from the source 201 to the drain 209 in the GaN HEMT, affecting the performance of the GaN HEMT. performance.

Contents of the invention

In view of this, the present invention provides a high electron mobility transistor, which is used to solve the problem caused by the surface damage of the etched barrier layer and channel layer in the existing recessed gate technology from the source to the drain in the gallium nitride HEMT. The reduced electron mobility and the contamination of the etched surface affect the performance of GaN HEMTs.

The invention protects a high electron mobility transistor, including:

a substrate and a first channel layer and a first barrier layer sequentially formed on the substrate;

Etching the first barrier layer to the inside of the first channel layer to form a first groove, the first groove has a bottom surface and sidewalls, the bottom surface is the first channel layer;

A second channel layer is formed on the first barrier layer, the sidewall and the bottom surface, and the second channel layer is respectively etched to the first groove on both sides of the first groove. A barrier layer, the inside of the first barrier layer, the first channel layer, or the inside of the first channel layer form a second groove and a third groove, and in the second groove filling the trench to form a source, and filling the third groove to form a drain;

A gate is formed on the second channel layer and filled in the first groove.

Implementing the embodiment of the present invention will have the following beneficial effects:

By setting the second channel layer, the etched surface of the first channel layer is filled with the second channel layer. The newly added second channel layer forms a new two-dimensional electron gas channel, forming a source-to-drain electron migration channel in the gate region. The channel is not affected by etching, maintains relatively high electron mobility, and can effectively reduce the on-resistance and gate charge of the device.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

in:

FIG. 1 is a schematic structural diagram of a p-type structure in the background art.

FIG. 2 is a schematic structural diagram of a recessed gate structure in the background art.

FIG. 3 is a schematic structural diagram of a high electron mobility transistor according to a specific embodiment of the present invention.

FIG. 4 is a schematic structural diagram of a first groove in a rectangular shape when viewed from above in a specific embodiment of the present invention.

Fig. 5 is a schematic view of the structure of the first groove in a top view in a specific embodiment of the present invention, which is a rectangle with one side combined with a triangular shape.

FIG. 6 is a structural schematic view of a first groove in a top view of a specific embodiment of the present invention, which is a rectangle with two sides combined with a triangular shape.

Fig. 7 is a schematic view of the structure of the first groove in a top view of a specific embodiment of the present invention, which is a rectangle and one side is combined with a triangle shape.

FIG. 8 is a structural schematic view of a first groove in a top view of a specific embodiment of the present invention, which is a rectangle with one side combined with a semicircular shape.

FIG. 9 is a structural schematic view of a first groove in a top view of a specific embodiment of the present invention, which is a rectangular shape with two sides combined with a symmetrical semicircular shape.

Fig. 10 is a structural schematic view of a first groove in a top view of a specific embodiment of the present invention, which is a rectangle and one side combined with a semicircular shape.

Fig. 11 is a schematic view of the structure of the first groove in a top view of a specific embodiment of the present invention, where both sides of the rectangle are combined with an asymmetrical semicircular shape. In the figure,

101, source; 102, aluminum gallium nitride barrier layer; 103, gallium nitride channel layer; 104, gallium nitride layer; 105, buffer layer; 106, substrate; 107, gate; 108, p-nitrogen GaN channel layer, 109, drain;

201, source electrode; 202, gate insulating layer; 203, aluminum gallium nitride barrier layer; 204, channel layer; 205, gallium nitride layer; 206, buffer layer; 207, substrate; 208, gate; 209 , Drain;

301. The third metal electrode; 302. The first metal electrode; 303. The gate; 304. The first passivation layer; 305. The source; 306. The protective layer; 307. The first barrier layer; 308. The first trench channel layer; 309, doped channel layer; 310, buffer layer; 311, substrate; 312, fourth passivation layer; 313, fourth metal electrode; 314, third passivation layer; 315, second metal electrode 316, the second passivation layer; 317, the drain; 318 the gate insulating layer; 319, the second barrier layer; 320, the second channel layer.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Apparently, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

Referring to Fig. 3 ~ Fig. 11, the present invention provides a kind of high electron mobility transistor, comprises:

A substrate 311 and a first channel layer 308 and a first barrier layer 307 sequentially formed on the substrate 311, wherein the substrate 311 may be a sapphire substrate or the like, and the first channel layer 308 may be a gallium nitride layer etc., the first barrier layer 307 may be an aluminum gallium nitride layer, etc., and the molar ratio of aluminum in the aluminum gallium nitride layer is 20% to 35%, preferably 25%.

Etching the first barrier layer 307 to the inside of the first channel layer 308 forms a first groove, and etching the first groove to the inside of the first channel layer 308 is to deplete the first barrier layer 307 and The first channel layer 308 is in contact with the two-dimensional electron gas, so as to achieve the purpose of enhancing the high electron mobility transistor. Wherein, referring to FIG. 4 to FIG. 11 , the shape of the first groove may be an independent shape of periodic or aperiodic rows. It can be one or more of circular, rectangular, triangular, elliptical and parallelogram, and can also be an irregular figure, but there needs to be a through groove in the first groove.

The first groove has a bottom surface and sidewalls, the bottom surface is the first channel layer 308, the first groove is formed by vertically etching the surface of the first barrier layer 307 into the inside of the first channel layer 308, the first concave The groove has penetrated the first barrier layer 307 , therefore, the sidewall of the first groove is composed of the side of the first barrier layer 307 and part of the side of the first channel layer 308 . The second channel layer 320 is formed on the first barrier layer 307 , on the sidewalls and on the bottom surface.

Etching the second channel layer 320 to the first barrier layer 307, the inside of the first barrier layer 307, the first channel layer 308 or the inside of the first channel layer 308 respectively on both sides of the first groove, A second groove and a third groove are formed, the second groove is filled to form a source 305 , and the third groove is filled to form a drain 317 . The gate 303 is formed on the second channel layer 320 and filled in the first groove. Wherein, the material of the source electrode 305 and the drain electrode 317 is selected from one or more than two of titanium, aluminum, nickel and gold. The material of the gate 303 is selected from nickel or gold.

By setting the second channel layer 320, the surface of the etched first channel layer 308 is filled with the second channel layer 320, which reduces the impact of etching on the first channel layer 308 and improves the first channel layer 308. The electron mobility in the channel layer 308, meanwhile, the newly added second channel layer 320 increases the electron migration channel from the source electrode 305 to the drain electrode 317, thereby improving the electron mobility.

Referring to FIG. 3 , in a specific embodiment, a second barrier layer 319 and a gate insulating layer 318 are sequentially formed on the second channel layer 320 .

Among the second barrier layer 319, the second channel layer 320 and the gate insulating layer 318, at least the second channel layer 320 is a single crystal structure deposited by vapor deposition, and only the second channel layer 320 may be formed. It is a single crystal structure; it can also be that both the second channel layer 320 and the second barrier layer 319 have a single crystal structure; it can also be that both the second channel layer 320 and the gate insulating layer 318 have a single crystal structure; The second barrier layer 319, the second channel layer 320 and the gate insulating layer 318 are all of single crystal structure. Wherein, the second channel layer 320 has a single crystal structure to improve electron mobility. When the second barrier layer 319, the second channel layer 320 and the gate insulating layer 318 are all of a single crystal structure, they can be continuously deposited and formed by vapor phase deposition, and the whole process is operated in a vacuum without contact with air to prevent pollution. The above-mentioned layer structure and the quality of the high electron mobility transistor are guaranteed.

Referring to FIG. 3 , in a specific embodiment, the second channel layer 320 has a thickness of 1 nm to 100 nm, the second barrier layer 319 has a thickness of 1 nm to 50 nm, and the gate insulating layer 318 has a thickness of 1 nm to 100 nm. Wherein, the thickness of the second channel layer 320 within this range is conducive to improving electron mobility, and the thickness of the second barrier layer 319 and gate insulating layer 318 within this range is conducive to improving the distance between the source electrode 305 and the gate electrode 303. breakdown voltage.

Referring to FIG. 3, in a specific embodiment, the second barrier layer 319 is selected from one of an aluminum gallium nitride layer, an indium aluminum nitride layer, an indium aluminum gallium nitride layer and an aluminum nitride layer, preferably an aluminum gallium nitride layer . The second channel layer 320 is selected from one of a gallium nitride layer, an indium gallium nitride layer and an aluminum gallium nitride layer, preferably a gallium nitride layer. The gate insulating layer 318 is a silicon nitride layer or the like. Gallium nitride is a semiconductor with large band gap, strong atomic bond, high thermal conductivity, good chemical stability and strong radiation resistance, which is suitable for high electron mobility transistors. Silicon nitride has good insulation, and has the characteristics of high temperature resistance and thermal shock resistance, and the insulation effect is stable.

Referring to FIG. 3, in a specific embodiment, the high electron mobility transistor further includes a protection layer 306, the protection layer 306 is formed on the first barrier layer 307, and the protection layer 306 and the first barrier layer 307 are etched to the first A first groove is formed in the channel layer 308 . The purpose of providing the protection layer 306 is to protect the first barrier layer 307 and the first channel layer 308, because in the process of etching the first groove, if there is no protection of the protection layer 306, the first groove layer is easily damaged during the etching process. A barrier layer 307 and the first channel layer 308 , thereby affecting the performance between the first barrier layer 307 and the first channel layer 308 .

Further, in a specific embodiment, the protection layer 306 is a gallium nitride layer, etc., because the gallium nitride layer and the second channel layer 320 are both gallium nitride layers, the same material, and have high electron mobility.

Referring to FIG. 3, in a specific embodiment, the first passivation layer 304 is formed on the gate insulating layer 318, the source electrode 305 and the drain electrode 317, and the first passivation layer 304 is etched to the gate insulating layer 318 to form the first passivation layer 304. Four grooves, the gate 303 is formed by filling the fourth groove.

A second passivation layer 316 is formed on the first passivation layer 304 and the gate 303 .

The second passivation layer 316 and the first passivation layer 304 are respectively etched to the source electrode 305 and the drain electrode 317 to form a fifth groove and a sixth groove.

The first metal is filled on the source 305 and in the fifth groove, and the first metal is connected to the source 305 to form the first metal electrode 302 .

The second metal is filled on the drain 317 and in the sixth groove, and the second metal is connected to the drain 317 to form a second metal electrode 315 .

One of the purposes of setting the first passivation layer 304 and the second passivation layer 316 is to isolate the surface of the high electron mobility transistor from the surrounding electrical environment and chemical environment, so as to reduce the reverse leakage current and increase the breakdown voltage , increase the fixed power consumption; the second purpose is to fix the source 305, drain 317 and gate 303 more firmly on the high electron mobility; the third purpose is to play a buffer role, the passivation layer is subjected to physical In case of an impact, the source 305 , the drain 317 and the gate 303 can be protected.

Referring to FIG. 3 , in a specific embodiment, a third passivation layer 314 is formed on the first metal electrode 302 , the second metal electrode 315 and the second passivation layer 316 .

The third passivation layer 314 is respectively etched to the first metal electrode 302 and the second metal electrode 315 to form a seventh groove and an eighth groove.

The third metal is filled on the first metal electrode 302 and in the seventh groove, and the third metal is connected with the first metal electrode 302 to form the third metal electrode 301 .

A fourth metal is filled on the second metal electrode 315 and in the eighth groove, and the fourth metal is connected to the second metal electrode 315 to form a fourth metal electrode 313 .

A fourth passivation layer 312 is formed on the third metal electrode 301 , the fourth metal electrode 313 and the third passivation layer 314 .

The fourth passivation layer 312 is etched to the third metal electrode 301 and the fourth metal electrode 313 respectively.

The purposes of the third passivation layer 314 and the fourth passivation layer 312 are the same as those of the first passivation layer 304 and the second passivation layer 316 .

Further, in a specific embodiment, the materials of the first passivation layer 304, the second passivation layer 316, the third passivation layer 314 and the fourth passivation layer 312 can be respectively selected as silicon dioxide and silicon nitride Etc., silicon dioxide is a good insulator, and silicon dioxide itself is also resistant to high temperature and has good stability.

Referring to FIG. 3, a buffer layer 310 and a doped channel layer 309 are also provided between the substrate 311 and the first channel layer 308. The buffer layer 310 is formed on the substrate 311, and the doped channel layer 309 is formed on the buffer layer 310. Formed on. The doped channel layer 309 may be a carbon doped silicon nitride layer or the like. The purpose of setting the buffer layer 310 and the doped channel layer 309 is to improve the stability of the entire high electron mobility.

The above disclosures are only preferred embodiments of the present invention, and certainly cannot limit the scope of rights of the present invention. Therefore, equivalent changes made according to the claims of the present invention still fall within the scope of the present invention.

Claims (10)

1. A high electron mobility transistor, comprising:

the device comprises a substrate, and a first channel layer and a first barrier layer which are sequentially formed on the substrate;

etching the first barrier layer to the inside of the first channel layer to form a first groove, wherein the first groove is provided with a bottom surface and a side wall, and the bottom surface is the first channel layer;

forming second channel layers on the first barrier layer, the side wall and the bottom surface, respectively etching the second channel layers to the first barrier layer, the interior of the first channel layer or the first channel layer on two sides of the first groove to form a second groove and a third groove, filling the second groove to form a source electrode, and filling the third groove to form a drain electrode;

and filling the second channel layer and the first groove to form a grid.

2. The HEMT of claim 1,

a second barrier layer and a gate insulating layer are sequentially formed on the second channel layer;

the second channel layer is a single crystal structure.

3. The HEMT of claim 2,

the thickness of the second channel layer is 1nm to 100nm;

the thickness of the second barrier layer is 1nm to 50nm;

the thickness of the gate insulating layer is 1nm to 100nm.

4. The HEMT of claim 2,

the second barrier layer is selected from one or more of an aluminum gallium nitride layer, an indium aluminum gallium nitride layer and an aluminum nitride layer;

the second channel layer is selected from one or more of a gallium nitride layer, an indium gallium nitride layer and an aluminum gallium nitride layer;

the gate insulating layer is a silicon nitride layer.

5. The HEMT of claim 2~4,

the protective layer is formed on the first barrier layer, and the protective layer and the first barrier layer are etched to form the first groove in the first channel layer.

6. The hemt of claim 5, wherein said protective layer is a gallium nitride layer.

7. The HEMT of claim 5,

forming a first passivation layer on the gate insulating layer, the source electrode and the drain electrode, and etching the first passivation layer to the gate insulating layer to form a fourth groove; filling the fourth groove to form the grid electrode;

forming a second passivation layer on the first passivation layer and the gate electrode;

etching the second passivation layer and the first passivation layer to the source electrode and the drain electrode respectively to form a fifth groove and a sixth groove;

filling a first metal on the source electrode and in the fifth groove, wherein the first metal is connected with the source electrode to form a first metal electrode;

and filling a second metal on the drain electrode and in the sixth groove, wherein the second metal is connected with the drain electrode to form a second metal electrode.

8. The HEMT of claim 7,

forming a third passivation layer on the first metal electrode, the second metal electrode, and the second passivation layer;

etching the third passivation layer to the first metal electrode and the second metal electrode respectively to form a seventh groove and an eighth groove;

filling a third metal on the first metal electrode and in the seventh groove, wherein the third metal is connected with the first metal electrode to form a third metal electrode;

filling a fourth metal on the second metal electrode and in the eighth groove, wherein the fourth metal is connected with the second metal electrode to form a fourth metal electrode;

forming a fourth passivation layer on the third metal electrode, the fourth metal electrode, and the third passivation layer;

and etching the fourth passivation layer to the third metal electrode and the fourth metal electrode respectively.

9. The hemt of claim 8, wherein said first, second, third and fourth passivation layers are all of silicon dioxide.

10. The HEMT of claim 1,

a buffer layer and a doped channel layer are further arranged between the substrate and the first channel layer, the buffer layer is formed on the substrate, and the doped channel layer is formed on the buffer layer.

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