CN110660851A - High-voltage n-channel HEMT device - Google Patents

Abstract

A high-voltage n-channel HEMT device belongs to the technical field of semiconductor power devices. In view of the high technological difficulty of preparing superjunctions on heterojunction devices such as HEMTs, the present invention proposes a surface superjunction structure for n-channel HEMT devices, by preparing p-type p-type comb fingers on the surface of the device drift region The semiconductor strip, and the p-type semiconductor strip is electrically connected to the gate, can achieve large-scale depletion of the drift region channel under the off condition, and the depletion region can withstand higher voltages, so that the device breaks down Features are enhanced. On the other hand, since the p-type surface withstand voltage structure connected to the gate only covers a small part of the drift region area, when the device is turned on, the parasitic resistance and parasitic capacitance associated with it are also relatively small, which makes the device have Relatively good DC conduction characteristics and high frequency characteristics.

Description

A high-voltage n-channel HEMT device

technical field

The invention belongs to the technical field of semiconductor power devices, and particularly relates to an n-channel HEMT device with a p-type surface withstand voltage structure connected to a gate electrode.

Background technique

In the field of radio frequency and power integrated circuits, with the continuous improvement of the integration of the circuit, the requirements of the circuit on the characteristics of the device are also getting higher and higher. Under the circumstance that the performance of traditional silicon devices has almost reached the theoretical limit, it is urgent to develop a new device with high frequency, high speed, high power, low noise and low power consumption to meet the needs of high-speed and large-capacity computers and large-capacity long-distance Communication requirements, semiconductor heterojunction devices came into being. Among them, high electron mobility transistor (High Electron Mobility Transistor, HEMT) has received extensive attention of the industry due to its advantages such as ultra-high speed and low power consumption (especially at low temperature).

The basic structure of HEMT is a modulated doped heterojunction. Taking an n-channel HEMT device as an example, the basic HEMT device structure is shown in Figure 1. From bottom to top, it is: substrate, buffer layer, barrier layer and electrode. The buffer layer (Buffer) is epitaxially grown on the substrate, and then the barrier layer (Barrier) is grown on the buffer layer. The barrier layer can be doped or not according to the specific situation, and the source is distributed on the barrier layer. Source, gate and drain, the source and drain generally achieve ohmic contact with the two-dimensional conductive channel by alloying, while the gate and the barrier layer form Schottky contact . There is a two-dimensional electron gas (2-DEG) in the triangular potential well formed by the contact between the buffer layer and the barrier layer to form a heterojunction interface. Since the electron gas is far away from the surface state, it is spatially and in the barrier layer. The impurity center is separated and is not affected by the scattering of ionized impurities, so it has high mobility, and the depth and width of the triangular potential well can be controlled by the gate voltage, so that the concentration of the two-dimensional electron gas can be changed to achieve control HEMT purpose of current. In addition, how to improve the breakdown voltage of the device is one of the research focuses in this field. Because the HEMT device is in the working state, the electric field formed at the gate and drain edges will reduce the breakdown voltage of the device, thereby limiting the maximum output power of the device. Therefore, in order to apply HEMT devices as power devices, research on high-voltage HEMT devices is of great significance. In view of this, a variety of pressure-resistant structures have been developed, of which the field plate structure is the most common one. However, the field plate structure requires high process precision, and its breakdown voltage improvement of HEMT is limited, which limits its practical application. In addition, many researchers consider borrowing the superjunction structure in LDMOS and propose to introduce a similar superjunction in HEMT. However, since HEMT is a heterojunction epitaxial device, it has more limitations in process than traditional Si-based devices, which causes the existing superjunction structure for HEMT to be a multi-layer epitaxial structure, which is difficult to process. At the same time, the effect of pressure resistance improvement is also limited. In view of this situation, it is necessary to develop a new type of pressure-resistant structure similar to superjunction suitable for HEMT.

SUMMARY OF THE INVENTION

In view of the defects in the prior art that the withstand voltage structure proposed for HEMT devices is difficult to process and the breakdown voltage is limited, the present invention proposes an n-channel with a comb-finger p-type surface withstand voltage structure connected to the gate. HEMT device.

In order to strengthen the withstand voltage characteristics of the n-channel HEMT device, the present invention provides the following technical solutions:

A high-voltage n-channel HEMT device, comprising: a substrate 1, a buffer layer 2 arranged on the upper surface of the substrate 1, a barrier layer 3 arranged on the upper surface of the buffer layer 2, and a gate arranged on the upper surface of the barrier layer 3 electrode 4, source electrode 5 and drain electrode 6; the buffer layer 2 and the barrier layer 3 form a heterojunction at their contact interface, and there is a two-dimensional conductive channel 9 on the interface of the heterojunction; the source electrode 5 and The drain 6 is respectively arranged on both sides of the barrier layer 3 and forms ohmic contact with the two-dimensional conductive channel 9; the gate 4 is arranged on the barrier layer 3 between the source 5 and the drain 6 And form Schottky contact with the barrier layer 3; it is characterized in that,

There is a surface withstand voltage structure on the barrier layer 3 between the gate electrode 4 and the drain electrode 6, and the surface withstand voltage structure includes a plurality of p-type semiconductor blocks 7 arranged in a comb finger shape, wherein each p-type semiconductor block 7 is The gate-drain direction extends; the p-type semiconductor blocks 7 arranged in the form of comb fingers are electrically connected to the gate electrode 4 , but are not in contact with the drain electrode 6 .

Further, an insulating medium 8 is filled at least between adjacent p-type semiconductor blocks 7 .

Furthermore, the insulating medium 8 is in contact with or isolated from the drain 6 .

As an embodiment, both ends of the insulating medium 8 disposed between the adjacent p-type semiconductor blocks 7 are flush with the p-type semiconductor blocks 7 , that is, the end of the p-type semiconductor block 7 and the insulating medium 8 are along the p-type semiconductor block. 7 Arrange the directions flush.

As an embodiment, the insulating medium 8 disposed between adjacent p-type semiconductor blocks 7 may communicate with each other along the arrangement direction of the p-type semiconductor blocks 7 and half surround the p-type semiconductor blocks 7 , and the insulating medium 8 is in phase with the drain 6 . isolation.

As an embodiment, the insulating medium 8 disposed between the adjacent p-type semiconductor blocks 7 may extend toward the drain 6 and completely fill the gap between the p-type semiconductor block 7 and the drain 6, that is, the insulating medium 8 can communicate with each other along the arrangement direction of the p-type semiconductor blocks 7 and half surround the p-type semiconductor blocks 7 , and the insulating medium 8 is in contact with the drain 6 .

Further, the surface pressure-resistant structure can be used in combination with a pressure-resistant structure such as a field plate.

The working principle of the present invention is:

The p-type semiconductor block can raise the energy band of the barrier layer due to the p-type surface withstand voltage structure with a comb-finger distribution connected to the gate between the gate and the drain, making the triangular potential at the interface of the heterojunction. The well lifts up, depleting or partially depleting the two-dimensional electron gas in the channel.

When the device is turned off, when the positive voltage on the drain increases, the p-type p-type semiconductor block in contact with the gate will be gradually depleted, and the fixed negative charge in this depletion region will affect the two-dimensional conduction channel. The two-dimensional electron gas in the channel has a depletion effect. During this process, the two-dimensional electron gas under each p-type semiconductor block is first depleted. With the further increase of the positive voltage of the drain, the two-dimensional electron gas under the finger gap region of the p-type surface withstand voltage structure connected to the gate will be gradually depleted.

If all the semiconductor structures in the drift region are to be completely depleted when the drain voltage is large enough, the total amount of fixed positive charges generated by ionization needs to be equal to the total amount of fixed negative charges. According to this principle, the doping concentration of the comb-finger p-type surface withstand voltage structure can be appropriately set, so that the comb-finger p-type semiconductor block connected to the gate and the two-dimensional electron gas under the interdigital gap region are simultaneously depleted. In this way, the surface withstand voltage structure between the source and drain of the HEMT device and its extension area below form a larger depletion region, which can withstand a higher positive voltage, and the direct result is that the device withstand voltage is improved. .

When the device is turned on, the two-dimensional electron gas under the interdigital gap region of the comb-finger p-type surface withstand voltage structure connected to the gate through the metal wire is not affected by the multiple p-type semiconductor blocks, and has a high The electron concentration is thus a good conduction path, which ensures that the on-resistance of the device will not be significantly deteriorated by the use of a withstand voltage structure. In addition, when designing the device, the p-type surface withstand voltage structure connected to the gate only covers a small part of the drift region area, so that the parasitic capacitance introduced by the surface withstand voltage structure is relatively small. The device based on this withstand voltage structure has smaller on-resistance and additional capacitance, which makes it have better high-frequency characteristics.

The beneficial effects of the present invention are:

The HEMT device proposed by the invention realizes smaller on-resistance and parasitic capacitance of the withstand voltage structure while ensuring high breakdown voltage, and is suitable for application fields with higher requirements for output power and operating frequency.

Description of drawings

FIG. 1 is a schematic three-dimensional structure diagram of a conventional n-channel HEMT device.

FIG. 2 is one of the specific implementation manners of the n-channel HEMT device structure provided by the present invention having a p-type surface withstand voltage structure connected to the gate.

FIG. 3 is a second specific implementation manner of an n-channel HEMT device structure with a comb-finger p-type surface withstand voltage structure connected to the gate according to the present invention.

FIG. 4 is a top view of the second specific implementation manner of an n-channel HEMT device structure with a p-type surface withstand voltage structure connected to the gate according to the present invention.

FIG. 5 is a third specific implementation manner of an n-channel HEMT device structure with a comb-finger p-type surface withstand voltage structure connected to the gate according to the present invention.

FIG. 6 is a top view of the third specific implementation manner of an n-channel HEMT device structure with a comb-finger p-type surface withstand voltage structure connected to the gate according to the present invention.

FIG. 7 is a fourth specific implementation manner of an n-channel HEMT device structure with a comb-finger p-type surface withstand voltage structure connected to the gate according to the present invention.

FIG. 8 is a plan view of the fourth specific implementation manner of the n-channel HEMT device structure with the p-type surface withstand voltage structure connected to the gate according to the present invention.

9 is a three-dimensional schematic diagram of a depletion region formed under a plurality of p-type semiconductor blocks distributed in a comb-finger shape in an n-channel HEMT device with a p-type surface withstand voltage structure connected to the gate provided by the present invention .

FIG. 10 is an illustration of a depletion region under a plurality of p-type semiconductor blocks distributed in a comb-finger shape in an n-channel HEMT device with a p-type surface withstand voltage structure connected to the gate provided by the present invention to a plurality of p-type semiconductor blocks. Schematic diagram of the three-dimensional structure of the expansion of the region under the gap of the type semiconductor block and finally forming an approximately rectangular large-scale depletion.

FIG. 11 is a schematic three-dimensional structure diagram of forming a GaN buffer layer on the upper surface of the substrate provided by the present invention.

FIG. 12 is a schematic three-dimensional structure diagram of growing an AlGaN barrier layer on the upper surface of the GaN buffer layer and forming a two-dimensional conductive channel provided by the present invention.

13 is a schematic three-dimensional structural diagram of the source and drain electrodes that form ohmic contact with the two-dimensional conductive channel on the upper surface of the AlGaN barrier layer provided by the present invention.

FIG. 14 is a schematic three-dimensional structural diagram of the gate electrode formed on the upper surface of the AlGaN barrier layer to form Schottky contact with the AlGaN barrier layer provided by the present invention.

15 is a schematic three-dimensional structural diagram of a p-type GaN layer electrically connected to the gate while maintaining a certain gap with the drain and covering the upper surface of the AlGaN barrier layer between the gate and the drain provided by the present invention.

FIG. 16 is a schematic three-dimensional structural diagram of etching a p-type GaN layer to form a plurality of p-type GaN blocks provided by the present invention.

FIG. 17 is a schematic three-dimensional structural diagram of depositing a thin insulating medium on the side of the p-type surface withstanding voltage structure connected to the gate, which is close to the gate, and connected to the gate, provided by the present invention.

FIG. 18 is a schematic three-dimensional structural diagram of depositing a metal field plate on the gate electrode and the thin insulating medium provided by the present invention.

In the figure: 1 is the substrate, 2 is the buffer layer, 3 is the barrier layer, 4 is the gate, 5 is the source, 6 is the drain, 7 is a p-type semiconductor block, 8 is an insulating medium, and 9 is a two-dimensional Conductive channel, 10 is a GaN buffer layer, 11 is an AlGaN barrier layer, and 12 is a p-type GaN bulk.

Detailed ways

In order to make the solutions and principles of the present invention clearer to those skilled in the art, the following detailed description is given in conjunction with the accompanying drawings and specific embodiments. The content of the present invention is not limited to any specific embodiment, nor does it represent the best embodiment, and general substitutions known to those skilled in the art are also included within the protection scope of the present invention.

Example:

The present invention provides an n-channel HEMT device with a comb-finger p-type surface withstand voltage structure connected to a gate, comprising a substrate 1, a buffer layer 2, a barrier layer 3, a gate 4, a source 5 and a drain Electrode 6, a buffer layer 2 and a barrier layer 3 are sequentially arranged on the substrate 1, and a two-dimensional conductive channel 9 is formed at the interface between the barrier layer 3 and the buffer layer 2; the source electrode 5 and the drain electrode 6 are respectively arranged on the HEMT device Both sides are in ohmic contact with the two-dimensional conductive channel 9; a gate electrode 4 is provided between the source electrode 5 and the drain electrode 6, and the gate electrode 4 is located on the barrier layer 3 to form Schottky contact with the barrier layer 3; The barrier layer 3 between the gate 4 and the drain 6 is provided with a surface withstand voltage structure, and the surface withstand voltage structure includes a plurality of p-type semiconductor blocks 7 arranged in a comb finger shape, wherein each p-type semiconductor block 7 Extending along the gate-drain direction; the p-type semiconductor blocks 7 arranged in the form of comb fingers are electrically connected to the gate 4 , but are not in contact with the drain 6 .

Due to the existence of gaps between the p-type surface withstand voltage structures connected to the gate, the plurality of p-type semiconductor blocks 7 do not fully cover the entire area above the barrier layer 3, so that the two-dimensional area under the uncovered area is not completely covered. The electron gas is not affected by the depletion effect of the plurality of p-type semiconductor blocks 7, thereby reducing the on-resistance and reducing the additional capacitance introduced.

In some embodiments, an insulating medium 8 may be filled between a plurality of p-type semiconductor blocks 7 , as shown in FIG. extension, as shown in FIG. 5 and FIG. 7; a plurality of p-type semiconductor blocks 7 and the drain 6 are not directly connected, and no medium may be provided between the p-type semiconductor blocks 7 and the drain 6 as shown in FIG. 2, or as shown in FIG. As shown in FIG. 5 , the insulating medium 8 is extended without contacting the drain 6 , and the insulating medium 8 can also be extended to contact the drain 6 as shown in FIG. 7 , so that the plurality of p-type semiconductor blocks 7 and the drain 6 pass through The insulating medium 8 is indirectly connected.

The working process of the present invention will be described in detail below with reference to FIG. 9 and FIG. 10 .

For conventional n-channel HEMT devices, when a large positive voltage is applied to the drain, it is difficult to completely deplete the drift region between the gate and drain, causing the voltage to mainly drop near the gate edge, which creates a large electric field peak, causing the device to break down.

In the present invention, a surface withstand voltage structure composed of a plurality of p-type semiconductor blocks 7 distributed in a comb-finger shape is arranged on the surface of the barrier layer 3 between the gate 4 and the drain 6 of the n-channel HEMT device. When the device is turned off, as the positive voltage on the drain increases, the two-dimensional electron gas under the p-type semiconductor block 7 will be depleted first; when the positive drain voltage is large enough, the two-dimensional electron gas under each p-type semiconductor block 7 will be depleted first; The depletion region will expand around, so that the two-dimensional electron gas in the region below the gap of the voltage-resistant structure on the entire comb-finger surface is also depleted, and the depletion region gradually expands until it is connected to form a large depletion region that is approximately rectangular. During the process, the p-type semiconductor block 7 is also gradually depleted. Due to the proper doping concentration of the p-type semiconductor bulk, it can be ensured that it is depleted almost simultaneously with the two-dimensional electron gas in the drift region, as shown in FIG. 10 . Based on the depletion region can play a role in withstand voltage, the voltage distribution area originally concentrated on the gate edge is greatly expanded, so that the electric field peak in the drift region between the gate and drain can be effectively suppressed, thereby improving the impact of the device. The breakdown voltage greatly improves the withstand voltage capability of the device.

As shown in FIG. 11 to FIG. 16, a manufacturing method for manufacturing an n-channel HEMT device of the present invention is given. In this embodiment, a GaN-based n-channel HEMT device is taken as an example, and the GaN-based HEMT device in this embodiment is described in detail with reference to the accompanying drawings. The manufacturing process of the base n-channel HEMT device includes the following steps:

Step 1. Grow a GaN buffer layer 10 on the substrate 1, as shown in FIG. 11 .

Step 2. An AlGaN barrier layer 11 is grown on the GaN buffer layer 10, a two-dimensional conductive channel 9 is formed at the interface between the GaN buffer layer 10 and the AlGaN barrier layer 11, and a two-dimensional electron gas exists in the two-dimensional conductive channel 9, such as Figure 12.

Step 3, perform mesa etching to fabricate the active region of the device, then prepare the source electrode 5 and the drain electrode 6 on the surface of the mesa, and make the source electrode 5 and the drain electrode 6 and the GaN buffer layer 10 and the AlGaN barrier layer 11 interface at the interface respectively. The two-dimensional conductive channel 9 forms an ohmic contact, as shown in FIG. 13 .

Step 4. A gate electrode 4 that is in Schottky contact with the AlGaN barrier layer 11 is fabricated above the AlGaN barrier layer 11, as shown in FIG. 14 .

Step 5. Cover the area between the gate electrode 4 and the drain electrode 6 above the AlGaN barrier layer 11 with a p-type GaN layer to a suitable thickness, as shown in FIG. 15 .

Step 6, pattern etching the p-type GaN layer to the surface of the AlGaN barrier layer 11, so that a plurality of p-type GaN uniformly distributed and extending along the gate-drain direction and electrically connected to the gate 4 are formed above the AlGaN barrier layer 11 Block 12, the p-type GaN block 12 is not in direct contact with the drain 6, the subsequent process is consistent with the existing HEMT fabrication process, and finally the GaN-based HEMT device of this embodiment is obtained, as shown in FIG. 16 .

Furthermore, with reference to FIGS. 17 and 18 , the fabrication method of the n-channel HEMT device using the p-type surface withstand voltage structure in combination with the field plate structure is further clarified.

In this embodiment, a GaN-based n-channel HEMT device is taken as an example, and the manufacturing process of the GaN-based n-channel HEMT device in this embodiment is described in detail with reference to the accompanying drawings. The device combines a metal field plate and a comb-finger surface withstand voltage structure. , the device preparation includes the following steps:

Step 1. Grow a GaN buffer layer 10 on the substrate 1, as shown in FIG. 11 .

Step 2. An AlGaN barrier layer 11 is grown on the GaN buffer layer 10, a two-dimensional conductive channel 9 is formed at the interface between the GaN buffer layer 10 and the AlGaN barrier layer 11, and a two-dimensional electron gas exists in the two-dimensional conductive channel 9, such as Figure 12.

Step 3, perform mesa etching to fabricate the active region of the device, then prepare the source electrode 5 and the drain electrode 6 on the surface of the mesa, and make the source electrode 5 and the drain electrode 6 and the GaN buffer layer 10 and the AlGaN barrier layer 11 interface at the interface respectively. The two-dimensional conductive channel 9 forms an ohmic contact, as shown in FIG. 13 .

Step 4. A gate electrode 4 that is in Schottky contact with the AlGaN barrier layer 11 is fabricated above the AlGaN barrier layer 11, as shown in FIG. 14 .

Step 5. Cover the area between the gate electrode 4 and the drain electrode 6 above the AlGaN barrier layer 11 with a p-type GaN layer to a suitable thickness, as shown in FIG. 15 .

Step 6, pattern etching the p-type GaN layer to the surface of the AlGaN barrier layer 11, so that a plurality of p-type GaN uniformly distributed and extending along the gate-drain direction and electrically connected to the gate 4 are formed above the AlGaN barrier layer 11 Block 12 , the p-type GaN block 12 is not in direct contact with the drain 6 , as shown in FIG. 16 .

Step 7: Deposit a thin insulating medium 8 between the gate 4 and the drain 6 on the side of the gate 4 close to the gate 4 , and the insulating medium 8 is in contact with the gate 4 , as shown in FIG. 17 .

Step 8, depositing a metal field plate over the gate 4 and the thin insulating medium 8, the subsequent process is consistent with the existing HEMT fabrication process, and finally the GaN-based HEMT device of this embodiment is obtained, as shown in FIG. 18 .

Those skilled in the art can make various other specific modifications and combinations without departing from the essence of the present invention according to the technical teaching disclosed in the present invention, and these modifications and combinations still fall within the protection scope of the present invention.

The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.

Claims (5)

1. A high-voltage n-channel HEMT device, comprising: the transistor comprises a substrate (1), a buffer layer (2) arranged on the upper surface of the substrate (1), a barrier layer (3) arranged on the upper surface of the buffer layer (2), and a grid electrode (4), a source electrode (5) and a drain electrode (6) arranged on the upper surface of the barrier layer (3); the buffer layer (2) and the barrier layer (3) form a heterojunction at their contact interface, with a two-dimensional conductive channel (9) at said heterojunction interface; the source electrode (5) and the drain electrode (6) are respectively arranged on two sides of the barrier layer (3) and are in ohmic contact with the two-dimensional conductive channel (9); the grid (4) is arranged on the barrier layer (3) between the source electrode (5) and the drain electrode (6) and forms Schottky contact with the barrier layer (3); it is characterized in that the preparation method is characterized in that,

the barrier layer (3) between the grid electrode (4) and the drain electrode (6) is provided with a surface voltage-resistant structure, the surface voltage-resistant structure comprises a plurality of p-type semiconductor blocks (7) which are arranged in a comb finger shape, wherein each p-type semiconductor block (7) extends along the grid leakage direction; the p-type semiconductor blocks (7) arranged in a comb-finger shape are electrically connected with the grid electrode (4) and are not contacted with the drain electrode (6).

2. The high-voltage n-channel HEMT device of claim 1, wherein at least between adjacent p-type semiconductor blocks (7) is filled with an insulating medium (8).

3. The high-voltage n-channel HEMT device of claim 2, wherein said insulating dielectric (8) is separate from said drain (6).

4. The high-voltage n-channel HEMT device of claim 2, wherein the insulating dielectric (8) disposed between adjacent p-type semiconductor blocks (7) extends toward the drain (6) and completely fills the gap between the p-type semiconductor blocks (7) and the drain (6), i.e., the insulating dielectric (8) surrounds the p-type semiconductor blocks (7) on the side of the p-type semiconductor blocks (7) closer to the drain, and the insulating dielectric (8) contacts the drain (6).

5. The high-voltage n-channel HEMT device as claimed in any one of claims 1 to 4, wherein the surface voltage-resistant structure is used alone or in combination with a voltage-resistant structure such as a field plate.

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