CN104157691B - A kind of semiconductor devices and its manufacture method - Google Patents

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises: a substrate; a semiconductor layer on the substrate; a source, a drain on the semiconductor layer, and a The gate between the drains; the source field plate connected to the source on the semiconductor layer, the source field plate spans the gate, the gate-source region and part of the gate-drain region, and is isolated by air; the One end of the source field plate is connected to the source, and the connection between the source field plate and the source is formed by parallel connection of two or more metal field plates; the other end of the source field plate is located between the gate and the source between the drain and the semiconductor layer near the gate. The invention can not only give full play to the electric field modulation function of the source field plate, but also fully reduce the parasitic gate-source capacitance and parasitic on-resistance, and can also improve device reliability.

Description

A kind of semiconductor device and its manufacturing method

technical field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.

Background technique

Gallium nitride (GaN) semiconductor material has a relatively large forbidden band width. Based on the heterojunction structure formed by gallium nitride (GaN) semiconductor material, a high-concentration two-dimensional electron gas can be generated at the heterojunction interface and is confined In the quantum well, the electron mobility is very high. Semiconductor devices made using this feature, such as high electron mobility transistors (HEMT), have the characteristics of large breakdown electric field, high current density, and fast electron saturation drift speed, which are very suitable for making high temperature, high frequency, high voltage and high power devices. It can be widely used in the field of radio frequency microwave and power electronics, and is one of the research hotspots in the field of semiconductor devices at present.

For HEMT devices operating at high drain-source voltage, the electric field lines near the drain side of the gate are very dense, which will form a high electric field spike. The high electric field in this local area can cause a very large gate leakage current. It even leads to material breakdown and device failure, thereby reducing the breakdown voltage of the device, and the higher the electric field peak, the smaller the breakdown voltage that the device can withstand. At the same time, with the increase of time, the high electric field will also cause the degradation and denaturation of the dielectric layer or semiconductor material layer on the surface of the device, which will affect the reliability of the device and reduce the life of the device, so that the advantages of high temperature, high voltage and high frequency of HEMT devices cannot be fully utilized. . Therefore, in the structural design and process development of actual devices, people will always take various methods to reduce the strong electric field near the gate of the device to increase the breakdown voltage of the device and obtain excellent reliability.

The currently widely used method is to use a field plate structure, as shown in Figure 1, that is, a field plate is placed on the drain side of the gate. The field plate is usually connected to the source or gate, and an additional potential is generated in the gate-drain region. , which increases the area of the depletion region and improves the withstand voltage of the depletion region, and the field plate modulates the distribution of electric field lines in the gate-drain region, especially the dense electric field lines near the drain edge of the gate. The modulation makes the distribution of electric field lines more uniform, reduces the electric field at the edge of the gate near the drain end, reduces the gate leakage current, and improves the breakdown voltage of the device.

However, in the above field plate structure, the source field plate is directly covered on the dielectric layer, and the dielectric layer is generally thin ( left and right), at this time the distance between the source field plate and the gate metal and the two-dimensional electron gas in the channel is very close, and the large-area source field plate metal completely overlaps with the gate below and the two-dimensional electron gas in the channel, parasitic The gate-source capacitance is inversely proportional to the distance between the source field plate and the gate metal, and is proportional to the overlapping area of the source field plate and the gate metal. In addition, the dielectric constant of the dielectric layer is relatively large, so the device will A large parasitic gate-source capacitance C _gs is generated, which leads to the deterioration of the frequency characteristics of the device, such as the reduction of f _T and f _MAX , and because the source field plate is generally connected to the lowest potential, it will affect the distribution of the two-dimensional electron gas below it, making the two The two-dimensional electron gas expands into the channel layer, which reduces the concentration of two-dimensional electrons in the channel, thereby generating parasitic resistance and increasing the on-resistance during the working process of the device. Increasing the thickness of the dielectric layer under the source field plate can reduce C _gs and parasitic resistance, but the thickness of the dielectric layer is generally designed and debugged and is not easy to change, and the electric field modulation of the source field plate to the gate-drain region after the thickness of the dielectric layer is increased The effect will be weakened, and the meaning of using the source field plate may be lost, and the material of the dielectric layer that is too thick will also increase the difficulty of the process.

Another improved field plate technology is to divide the connecting part of the source field plate and the source into several segments, and reduce the source field plate metal and the gate and the two-dimensional electron gas conduction channel on the basis of satisfying the electrical connection of the source field plate. The top view of the device structure is shown in Figure 2. However, in this technology, the distance between the source field plate and the gate and the two-dimensional electron gas conduction channel is still very close, and a large gate-source parasitic capacitance will still be generated. and parasitic on-resistance.

Therefore, it is necessary to find a new method of designing and manufacturing the source field plate, which can not only give full play to the electric field modulation effect of the source field plate, but also fully reduce the parasitic gate-source capacitance and parasitic on-resistance, and improve device reliability.

Therefore, in view of the above technical problems, it is necessary to provide a semiconductor device and a manufacturing method thereof.

Contents of the invention

In view of this, the present invention proposes a semiconductor device with an air-isolated source-field plate structure and a manufacturing method thereof. The source-field plate structure utilizes the arched supporting effect of the metal to pass over the gate, the gate-source area and part of the gate-drain area above the dielectric layer, and air is used to isolate the middle. The metal above this area is divided into several sections for electrical connection with the source. Connection, the connection part is designed as a rectangle or arc, the entire source field plate metal is formed by air bridge technology combined with metal evaporation or metal sputtering or metal plating process, the metal layer is thicker, and the supporting part of the metal on both sides of the arch is added On this basis, part of the dielectric layer under the source field plate is thinned or removed. The source field plate straddles the gate, the gate-source region and part of the gate-drain region cover the dielectric layer in the gate-drain region, and modulates the electric field distribution in the gate-drain region.

This structure solves the problems existing in the existing source field plate technology. First, the source field plate of the present invention is not in direct contact with the dielectric layer of the gate, gate-source region, and part of the gate-drain region, and the distance between them is relatively long. It is about 1 μm to 5 μm, and the air with a very small dielectric constant is used for isolation. On this basis, the arched connection part between the source field plate and the source is divided into several sections, from the distance, isolation medium, and metal overlap The area and other aspects greatly reduce the parasitic gate-source capacitance and parasitic resistance; second, the arched connection part between the source field plate and the source is designed to be rectangular or arc-shaped (wide at both ends and narrow in the middle), ensuring On the basis of electrical connection, the overlapping area between the metal of the source field plate and the lower gate and the two-dimensional electron gas conduction channel can be further reduced, and the parasitic gate-source capacitance and parasitic resistance can be further reduced; third, part of the dielectric below the source field plate The layer is thinned or removed, which is equivalent to being replaced by air of the same thickness, which further strengthens the isolation effect of the source field plate metal from the gate and the two-dimensional electron gas conduction channel, thus further reducing the gate-source parasitic capacitance and Parasitic resistance, at the same time, the source field plate is closer to the device surface in the gate-drain region, and the electric field modulation effect on the device surface is more obvious; Fourth, the entire source field plate metal is combined with metal evaporation or metal sputtering or metal plating process through the air bridge process Formation, the metal layer is thicker, generally about 1 μm to 5 μm in thickness, which ensures the reliability of the air bridge structure. By further thickening the metal on both sides of the arch, the reliability of the air bridge structure can be further strengthened; fifth, Since the arched connection part between the source field plate and the source electrode is divided into several sections (generally 2-5 sections, each section 1-10um), it is beneficial to remove the residual glue and air in the bridge hole during the manufacturing process, and improve device reliability.

In order to achieve the above object, the technical solutions provided by the embodiments of the present invention are as follows:

A semiconductor device, comprising: a substrate; a semiconductor layer on the substrate; a source, a drain on the semiconductor layer, and a gate between the source and the drain; A source-field plate connected to the source on the layer, where:

The source field plate straddles the gate, the gate-source region and part of the gate-drain region, and is isolated by air;

One end of the source field plate is connected to the source, and the connection between the source field plate and the source is formed by parallel connection of two or more metal field plates;

The other end of the source field plate is located on the semiconductor layer close to the gate between the gate and the drain.

As a further improvement of the present invention, a dielectric layer is provided on the semiconductor layer, and the source field plate is located on the dielectric layer.

As a further improvement of the present invention, part of the dielectric layer below the source field plate may be thinned or removed.

As a further improvement of the present invention, the source field plate is composed of one or more metals.

As a further improvement of the present invention, the connection between the source field plate and the source electrode is formed by parallel connection of 2 to 5 metal field plates.

As a further improvement of the present invention, the cross-sectional shape of the metal field plate is arc-shaped or arched.

As a further improvement of the present invention, the thickness of the metal field plate is uneven.

As a further improvement of the present invention, the thickness of the middle of the metal field plate is thinner than that of both sides.

As a further improvement of the present invention, the planar shape of the metal field plate is a rectangle or an arc.

As a further improvement of the present invention, the width of the metal field plate is 1 μm˜10 μm.

As a further improvement of the present invention, the maximum height difference between the metal field plate and the semiconductor layer or dielectric layer is 1 μm˜5 μm.

As a further improvement of the present invention, the thickness of the metal field plate is 1 μm˜5 μm.

As a further improvement of the present invention, the other end of the source field plate has a certain area on the semiconductor layer or the dielectric layer.

As a further improvement of the present invention, the dielectric layer further includes one or more of a grid field plate, a drain field plate, a floating field plate, and a grooved source field plate.

As a further improvement of the present invention, the medium layer is one or more layers.

As a further improvement of the present invention, the dielectric layer is one or more of SiN, SiO ₂ , SiON, Al ₂ O ₃ , HfO ₂ , and HfAlOx.

As a further improvement of the present invention, the gate is T-shaped or gamma-shaped.

As a further improvement of the present invention, the semiconductor layer includes: a nucleation layer on the substrate; a buffer layer on the nucleation layer; a channel layer on the buffer layer; The barrier layer on the channel layer.

Correspondingly, a manufacturing method of a semiconductor device, the manufacturing method includes the following steps:

S1, forming a semiconductor layer on the substrate;

S2, forming a source, a drain, and a gate between the source and the drain on the semiconductor layer;

S3 , forming a source field plate across the gate, the gate-source region and part of the gate-drain region and separated by air on the source electrode and the semiconductor layer.

As a further improvement of the present invention, the step S1 specifically includes:

forming a nucleation layer on the substrate;

forming a buffer layer on the nucleation layer;

A channel layer is deposited on the buffer layer.

A barrier layer is formed on the channel layer, the channel layer and the barrier layer form a heterojunction structure, a two-dimensional electron gas is formed at the heterojunction, and the source and the drain are connected to the two-dimensional electron gas respectively. Pneumatic contact.

As a further improvement of the present invention, the step S1 further includes: forming a dielectric layer on the semiconductor layer.

As a further improvement of the present invention, the step S3 is: forming a source field plate on the source electrode and the dielectric layer across the gate, the gate-source region and part of the gate-drain region and separated by air.

As a further improvement of the present invention, the source field plate in step S3 is realized by an air bridge process.

As a further improvement of the present invention, the source field plate in step S3 is formed by a metal electroplating process, a metal electron beam evaporation process, a metal sputtering process or a combination thereof.

The present invention has the following advantages:

The source field plate of the present invention reduces the effect of parasitic capacitance and parasitic resistance; and the source field plate of the present invention can continue to maintain the electric field modulation effect of the source field plate on the depletion layer of the gate drain region of the device, and the thickness of the thinner dielectric layer The effect of the source field plate in modulating the surface electric field is played to the greatest extent on the basis of the source field plate of the present invention; the reliability of the source field plate of the present invention is relatively high.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments described in the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic cross-sectional view of a semiconductor device with a conventional source field plate structure.

FIG. 2 is a schematic top view of a semiconductor device structure in which the connecting part of the source field plate and the source electrode is divided into several sections in the traditional source field plate structure.

3A is a schematic cross-sectional view of a semiconductor device with a segmented air-isolated source-field plate structure in the first embodiment of the present invention, and FIG. 3B is a schematic plan view of FIG. 3A .

4A-4B are schematic diagrams of the manufacturing process for forming the segmented air-isolated source-field plate structure in the first embodiment of the present invention.

5 is a schematic cross-sectional view of a semiconductor device with the second dielectric layer removed in the second embodiment of the present invention.

6 is a schematic cross-sectional view of a semiconductor device with thicker metals on both sides of the source field plate in the third embodiment of the present invention.

7 is a schematic cross-sectional view of a semiconductor device with an MIS structure in a fourth embodiment of the present invention.

8 is a schematic cross-sectional view of a semiconductor device with a segmented air-isolated source-field plate structure in which the bottom of the gate metal goes deep into the barrier layer according to the fifth embodiment of the present invention.

9 is a schematic cross-sectional view of a semiconductor device in which a segmented air-isolated source field plate structure is used in combination with a floating field plate in the sixth embodiment of the present invention.

10 is a schematic cross-sectional view of a semiconductor device in which a segmented air-isolated source-field plate structure is used in combination with a grooved source-field plate in a seventh embodiment of the present invention.

11 is a schematic cross-sectional view of a semiconductor device with a segmented air-isolated source field plate structure in which an AlN insertion layer is introduced between the barrier layer and the channel layer in the eighth embodiment of the present invention.

12 is a schematic cross-sectional view of a semiconductor device with a segmented air-isolated source field plate structure in which an AlGaN back barrier layer is inserted between the buffer layer and the channel layer in the ninth embodiment of the present invention.

detailed description

The present invention will be described in detail below in conjunction with specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, method, or functional changes made by those skilled in the art according to these embodiments are included in the protection scope of the present invention.

Furthermore, repeated reference numerals or designations may be used in different embodiments. These repetitions are merely for the sake of simplicity and clarity of describing the present invention, and do not imply any relationship between the different embodiments or structures discussed.

3A is a schematic cross-sectional view of a semiconductor device with a segmented air-isolated source-field plate structure in the first embodiment of the present invention, and FIG. 3B is a schematic plan view thereof.

As shown in Figure 3A, the semiconductor device includes:

Substrate 1, the substrate can be silicon carbide, sapphire, silicon, silicon-on-insulator substrate, gallium nitride, aluminum nitride, zinc oxide or a combination thereof, or any other material capable of growing Group III nitride materials;

On the substrate 1 is the nucleation layer 2. The nucleation layer affects the crystal quality, surface morphology and electrical properties of the heterojunction material above. The nucleation layer changes with different substrate materials, mainly for matching Substrate materials and the role of semiconductor material layers in heterojunction structures;

On the nucleation layer 2 is the buffer layer 3, the buffer layer is a transition layer between the nucleation layer and the channel layer, which plays the role of matching the substrate material and the high-quality epitaxial gallium nitride layer, the buffer layer includes GaN, AlN , AlGaN, or AlGaInN and other III-nitride materials;

On the buffer layer is a channel layer 4 comprising an undoped GaN layer;

On the channel layer 4 is a barrier layer 5 comprising AlGaN or other nitrides. The channel layer 4 and the barrier layer 5 together form a semiconductor heterojunction structure, form a high-concentration two-dimensional electron gas at the interface, and generate a conductive channel at the heterojunction interface of the GaN channel layer;

On the left and right ends of the barrier layer 5 are the source 6 and the drain 7, and the source and the drain are electrically connected to the two-dimensional electrons;

A first dielectric layer 9 is deposited on the barrier layer 5 to passivate and protect the surface of the material, and the first dielectric layer 9 includes one or more of SiN, SiO ₂ , SiON, Al ₂ O ₃ , HfO ₂ , HfAlOx combination;

In the region between the source 6 and the drain 7, the first dielectric layer 9 is etched to form a groove, and then metal is deposited to form the gate 8, which can be T-shaped or gamma-shaped;

A second dielectric layer 10 is deposited on the first dielectric layer 9 to protect the device, and the second dielectric layer 10 includes one or more of SiN, SiO ₂ , SiON, Al ₂ O ₃ , HfO ₂ , HfAlOx combination;

Above the dielectric layer of the gate, the gate-source region (the region between the gate and the source) and part of the gate-drain region (the region between the gate and the drain) is a segmented air-isolated source field plate 11, the source The distance between the field plate and the gate, the gate-source region and part of the gate-drain region dielectric layer must be kept at an appropriate distance. If the distance is too close, the isolation effect will not be obvious. If the distance is too far, the process will be difficult to realize. It is isolated by air, and is divided into several sections above the dielectric layer of the gate, gate-source region and part of the gate-drain region to realize electrical connection with the source. The segmentation should be reasonable. If there are too few segments, the electrical connection effect is not good. Segmentation If there is too much, the overlapping area between the metal on the source field plate and the lower gate and the two-dimensional electron gas conduction channel will be limited. It is generally divided into 2 to 5 sections. In this embodiment, 2 sections are used for illustration, and the width of each section of metal needs to be Reasonable, too narrow will affect the electrical connection effect, and the metal arch structure is easy to collapse. If it is too wide, the overlapping area of the source field plate metal and the lower gate and the two-dimensional electron gas conductive channel will be limited, generally about 1 μm to 10 μm. The plane shape of each piece of metal can be rectangular or arc-shaped (wide at both ends and narrow in the middle, as shown in Figure 3B), and the cross-sectional shape can be arc-shaped or arched; the source field plate structure can be realized by air bridge technology, The source field plate metal can be formed by metal electroplating process, metal electron beam evaporation process, metal sputtering process or a combination thereof. In order to ensure the firmness of the arched structure of the segmented air-isolated source field plate, the thickness of the metal is generally about 1 μm to 5 μm , the thickness of the metal field plate can be set uniformly or unevenly; the metal of the source field plate can be Ti, Al, Ni, Au, Pt or a combination thereof, and can also be metals commonly used in other semiconductor processes. The source field plate passes over the gate, the gate-source region and part of the gate-drain region dielectric layer, and then re-covers on the dielectric layer of the gate-drain region, and extends a certain distance to the drain.

The source field plate structure in this embodiment increases the distance between the gate and the two-dimensional electron gas conduction channel, uses air with a very small dielectric constant in the middle to isolate it, and reduces the distance between the metal and the gate and the two-dimensional electron gas conduction channel. The overlapping area of the electron gas conduction channel finally greatly reduces the parasitic capacitance and parasitic resistance.

4A-4B are schematic diagrams of the manufacturing process for forming the segmented air-isolated source-field plate structure of the present invention. After forming the source, drain, gate metal electrodes and the first and second dielectric layers according to the conventional process, the photolithography supporting the segmented air isolation source field plate is formed on the gate, gate source region and part of the gate drain region by photolithography glue 12, the photoresist is baked to form an arch, as shown in Figure 4A, and then photoetched again to expose and develop the place covered by the source field plate metal, and the place not covered is blocked by photoresist 13, and then through the metal Electroplating process, or metal evaporation process, or metal sputtering process produces a metal source field plate, as shown in Figure 4B, and finally washes off all photoresist to form a segmented air-isolated source field plate structure, as shown in Figure 3A and 3B. Segmented air-isolated source-field plate structures with different shapes can be realized by optimizing the photolithography process. For example, by adjusting the photolithography process and baking conditions, different shapes of supporting photoresist 12 can be designed, and different shapes can be formed by designing the layout. Shaped photoresist 13, thereby realizing segmented air-isolated source-field plate structures with different structures and shapes.

5 is a schematic cross-sectional view of a semiconductor device in which the second dielectric layer is removed in the second embodiment of the present invention. The second dielectric layer 10 is removed, which is equivalent to the second dielectric layer of the gate region, gate-source region and part of the gate-drain region. 10 is replaced by air with the same thickness, which can further reduce the parasitic capacitance and parasitic resistance. At the same time, the end of the source field plate covers the first dielectric layer 9, which is closer to the surface of the device, and can more effectively control the electric field in the gate-drain region. modulation.

6 is a schematic cross-sectional view of a semiconductor device with thickened metal on both sides of the source field plate in the third embodiment of the present invention. The thickness of the metal field plate in the present invention can be uneven, preferably in the middle of the metal field plate in this embodiment. The thickness of the metal on both sides of the source field plate is thinner than that on both sides, and the reliability of the source field plate structure can be improved by increasing the thickness of the metal on both sides of the source field plate.

7 is a schematic cross-sectional view of a semiconductor device with an MIS structure in the fourth embodiment of the present invention. The third dielectric layer 14 below the gate is not only a passivation layer for the device, but also a gate insulating layer. Combining field plate technology can effectively reduce the gate Pole leakage current, adjust the turn-on voltage. The third dielectric layer includes one or a combination of SiN, SiO ₂ , SiON, Al ₂ O ₃ , HfO ₂ , and HfAlOx.

8 is a schematic cross-sectional view of a semiconductor device with a segmented air-isolated source field plate structure in which the bottom of the gate metal goes deep into the barrier layer according to the fifth embodiment of the present invention. A recess etch is formed by etching the barrier layer, and then Depositing metal to form the gate can reduce the influence of surface defects and surface states of the material under the gate metal, reduce leakage, and increase breakdown voltage; at the same time, because the distance between the gate and the conductive channel is closer, the control effect on the two-dimensional electron gas is better. Strong, which improves the high-frequency characteristics of the device; if the etching depth of the barrier layer is large, the two-dimensional electron gas under the groove will be reduced or disappeared, and a nitride-enhanced device can also be realized.

9 is a schematic cross-sectional view of a semiconductor device in which the segmented air-isolated source field plate structure is used in combination with the floating field plate in the sixth embodiment of the present invention. The floating field plate 15 can effectively increase the barrier layer between the gate and the drain. The area of the depletion region, that is, the area of the high-resistance region is greatly increased, which makes the depletion region withstand a greater voltage, thereby greatly increasing the breakdown voltage of the device.

10 is a schematic cross-sectional view of a semiconductor device in which the segmented air-isolated source-field plate structure is used in combination with the recessed source-field plate in the seventh embodiment of the present invention. In the recess (Recess) structure 16, the source-field plate is closer to the gate-drain The surface of the device in the region can effectively modulate the electric field in the depletion layer of the gate-drain region and increase the breakdown voltage of the device. The air-isolated source field plate can just cover the groove, or extend a part toward the drain.

11 is a schematic cross-sectional view of a semiconductor device with a segmented air-isolated source field plate structure with an AlN insertion layer introduced between the barrier layer and the channel layer in the eighth embodiment of the present invention. In this embodiment, an AlN insertion layer 17 is introduced between the barrier layer and the channel layer, because AlN has a very high band gap, which can more effectively confine electrons in the heterojunction potential well, improving the two-dimensional electron gas concentration; the AlN insertion layer 17 also isolates the conductive channel from the AlGaN barrier layer, reducing the scattering effect of the barrier layer on electrons, thereby increasing the mobility of electrons and improving the overall characteristics of the device.

12 is a schematic cross-sectional view of a semiconductor device with a segmented air-isolated source field plate structure with an AlGaN back barrier layer inserted between the buffer layer and the channel layer in the ninth embodiment of the present invention. In this embodiment, an AlGaN back barrier layer 18 is inserted between the buffer layer and the channel layer. Under a certain applied voltage, the electrons in the channel will enter the buffer layer, especially in short-channel devices. Seriously, the control of the gate to the channel electrons is relatively weak, and the short channel effect appears; in addition, there are many defects and impurities in the buffer layer, which will affect the two-dimensional electron gas in the channel, such as current collapse. The introduction of the AlGaN back barrier layer 18 can isolate the channel electrons from the buffer layer, effectively confine the two-dimensional electron gas in the channel layer, and improve the short channel effect and current collapse effect.

As can be seen from the foregoing embodiments, compared with the prior art, the present invention has the following advantages:

First of all, the source field plate of the present invention is not in direct contact with the dielectric layer of the gate, gate-source region, and part of the gate-drain region, and the distance between them is relatively long, and air with a very small dielectric constant is used for isolation. On this basis Then the arched connection part between the source field plate and the source is divided into several sections, which greatly reduces the parasitic gate-source capacitance and parasitic resistance in terms of distance, isolation medium, and metal overlapping area;

Second, the arched connection part between the source field plate and the source is designed as a rectangle or an arc, which can further reduce the source field plate metal and the lower gate and the two-dimensional electron gas conduction channel on the basis of ensuring electrical connection. The overlapping area of the channel further reduces the parasitic gate-source capacitance and parasitic resistance;

Third, part of the dielectric layer under the source field plate is thinned or removed, which is equivalent to being replaced by air of the same thickness, which further strengthens the isolation effect of the source field plate metal from the grid and the two-dimensional electron gas conduction channel, so The gate-source parasitic capacitance and parasitic resistance are further reduced, and the source field plate is closer to the device surface in the gate-drain region, and the electric field modulation effect on the device surface is more obvious;

Fourth, the entire source field plate metal is formed through the air bridge process combined with metal evaporation or metal sputtering or metal plating process. The metal layer is thicker, which ensures the reliability of the air bridge structure. Thick, can further strengthen the reliability of the air bridge structure;

Fifth, since the arched connection part between the source field plate and the source electrode is divided into several sections, it is beneficial to remove the residual glue and air in the bridge hole during the manufacturing process, thereby improving the reliability of the device.

To sum up, the semiconductor device and its manufacturing method of the present invention can not only give full play to the electric field modulation function of the source field plate, but also fully reduce the parasitic gate-source capacitance and parasitic on-resistance, and can also improve the reliability of the device.

It will be apparent to those skilled in the art that the invention is not limited to the details of the above-described exemplary embodiments, but that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Accordingly, the embodiments should be regarded in all points of view as exemplary and not restrictive, the scope of the invention being defined by the appended claims rather than the foregoing description, and it is therefore intended that the scope of the invention be defined by the appended claims rather than by the foregoing description. All changes within the meaning and range of equivalents of the elements are embraced in the present invention. Any reference sign in a claim should not be construed as limiting the claim concerned.

In addition, it should be understood that although this specification is described according to implementation modes, not each implementation mode only contains an independent technical solution, and this description in the specification is only for clarity, and those skilled in the art should take the specification as a whole , the technical solutions in the various embodiments can also be properly combined to form other implementations that can be understood by those skilled in the art.

Claims (24)

1. A semiconductor device, comprising: a substrate; a semiconductor layer positioned on the substrate; a source electrode, a drain electrode positioned on the semiconductor layer, and a grid between the source electrode and the drain electrode; The source field plate connected to the source on the semiconductor layer is characterized in that: The source field plate spans the gate, the gate-source region and part of the gate-drain region, and the source field plate is isolated from the gate, the gate-source region and part of the gate-drain region by air; One end of the source field plate is in direct contact with the source, and the connection between the source field plate and the source is formed by parallel connection of two or more metal field plates; the two ends of the metal field plate The width is greater than its middle width; the cross-sectional shape of the metal field plate is arched; The other end of the source field plate is located on the semiconductor layer close to the gate between the gate and the drain. 2. The semiconductor device according to claim 1, wherein a dielectric layer is disposed on the semiconductor layer, and the source field plate is located on the dielectric layer. 3. The semiconductor device according to claim 2, wherein a part of the dielectric layer below the source field plate is thinned or removed. 4. The semiconductor device according to claim 1 or 2, wherein the source field plate is composed of one or more metals. 5. The semiconductor device according to claim 1 or 2, wherein the connection between the source field plate and the source electrode is formed by parallel connection of 2 to 5 metal field plates. 6. The semiconductor device according to claim 5, wherein the thickness of the metal field plate is not uniform. 7 . The semiconductor device according to claim 6 , wherein the thickness of the middle of the metal field plate is thinner than that of both sides. 8. The semiconductor device according to claim 1 or 2, wherein the planar shape of the metal field plate is a rectangle or an arc. 9. The semiconductor device according to claim 1 or 2, wherein the metal field plate has a width of 1 μm˜10 μm. 10 . The semiconductor device according to claim 1 , wherein the maximum height difference between the metal field plate and the semiconductor layer is 1 μm˜5 μm. 11 . 11. The semiconductor device according to claim 2, wherein the maximum height difference between the metal field plate and the semiconductor layer or dielectric layer is 1 μm˜5 μm. 12. The semiconductor device according to claim 1 or 2, wherein the metal field plate has a thickness of 1 μm˜5 μm. 13. The semiconductor device according to claim 1 or 2, wherein the other end of the source field plate has a certain area on the semiconductor layer or the dielectric layer. 14 . The semiconductor device according to claim 2 , wherein the dielectric layer further includes one or more of a gate field plate, a drain field plate, a floating field plate, and a grooved source field plate. 15. The semiconductor device according to claim 2, wherein the dielectric layer is one or more layers. 16. The semiconductor device according to claim 15, wherein the dielectric layer is one or more of SiN, SiO2, SiON, Al2O3, HfO2, HfAlOx. 17. The semiconductor device according to claim 1 or 2, wherein the gate is T-shaped or gamma-shaped. 18. The semiconductor device according to claim 1 or 2, wherein the semiconductor layer comprises: a nucleation layer on the substrate; a buffer layer on the nucleation layer; a buffer layer on the buffer a channel layer on a layer; a barrier layer on said channel layer. 19. A method of manufacturing a semiconductor device as claimed in claim 1, wherein the method of manufacturing comprises the following steps: S1, forming a semiconductor layer on the substrate; S2, forming a source, a drain, and a gate between the source and the drain on the semiconductor layer; S3 , forming a source field plate across the gate, the gate-source region and part of the gate-drain region and separated by air on the source electrode and the semiconductor layer. 20. The method for manufacturing a semiconductor device according to claim 19, wherein the step S1 specifically comprises: forming a nucleation layer on the substrate; forming a buffer layer on the nucleation layer; depositing a channel layer on the buffer layer; A barrier layer is formed on the channel layer, the channel layer and the barrier layer form a heterojunction structure, a two-dimensional electron gas is formed at the heterojunction, and the source and the drain are connected to the two-dimensional electron gas respectively. Pneumatic contact. 21. The manufacturing method of a semiconductor device according to claim 19, characterized in that, the step S1 further comprises: forming a dielectric layer on the semiconductor layer. 22. The manufacturing method of a semiconductor device according to claim 21, characterized in that, the step S3 is: forming a bridge across the gate, the gate-source region and part of the gate-drain on the source and the dielectric layer source field plates separated by air. 23. The manufacturing method of a semiconductor device according to claim 19, characterized in that, in the step S3, the source field plate is realized by an air bridge process. 24. The manufacturing method of a semiconductor device according to claim 19, characterized in that, in the step S3, the source field plate is formed by a metal electroplating process, a metal electron beam evaporation process, a metal sputtering process or a combination thereof.