CN115249681A - Thin film flip chip packaging structure - Google Patents

Abstract

The present invention provides a film-on-chip packaging structure, comprising a flexible substrate, a first circuit layer, a second circuit layer and a chip. The flexible substrate has opposite first and second surfaces and a chip coverage area located on the first surface, wherein the chip coverage area is divided into a first side area, a central area and a second side area along the longitudinal direction. The flexible substrate includes a first area, a second area and a third area respectively corresponding to the first side area, the central area and the second side area. The first circuit layer and the second circuit layer are respectively located on the first surface and the second surface. The chip is disposed in the chip coverage area and is bonded to the first circuit layer. The ratio of the line laying area of the second line layer to the line laying area of the first line layer is between 0.9 and 1.2 in the first zone and the third zone.

Description

Chip-on-Film Package Structure

technical field

The invention relates to a packaging structure, in particular to a film-on-chip packaging structure.

Background technique

With the increasing functional requirements of electronic products and the continuous improvement of the integrated circuit density of chips, the number of pins on the flexible circuit carrier board of the film-on-chip package structure must also increase. The single-sided circuit that was widely used can be The wiring of flexible substrates is becoming more and more difficult. Therefore, flexible circuit carriers are beginning to be designed in a way of double-sided circuits.

Further, under the double-sided circuit design of the flexible circuit carrier, the coefficient of thermal expansion between different materials (such as the flexible material used in the flexible substrate and the metal material used in the circuit layer) Expansion, CTE) mismatch (mismatch) The thermal stress generated on the two opposite surfaces will depend on the size of the laying area of the circuit layer. When the difference between the laying areas of the two opposite surfaces is greater, the stress is uneven. The more serious it is, the deformation and warpage of the flexible substrate are caused. When the film-on-chip package structure is subjected to the Inner Lead Bonding (ILB) process by means of thermocompression, the thermal effect of high temperature on the chip footprint is particularly obvious, so the flexible substrate is affected by thermal stress in this area. The warpage deformation caused by unevenness will be more serious, and it may further lead to the problem of poor pin bonding, peeling (peeling) or breakage.

SUMMARY OF THE INVENTION

The present invention provides a film-on-chip package structure, which can improve the warpage deformation of the flexible substrate and the problems of poor pin bonding, peeling or breakage, thereby improving its reliability.

A film-on-chip packaging structure of the present invention includes a flexible substrate, a first circuit layer, a second circuit layer and a chip. The flexible substrate has opposite first and second surfaces and a chip coverage area located on the first surface, wherein the chip coverage area is divided into a first side area, a central area and a second side area along the longitudinal direction. The flexible substrate includes a first area, a second area and a third area respectively corresponding to the first side area, the central area and the second side area. The first circuit layer and the second circuit layer are respectively located on the first surface and the second surface. The chip is disposed in the chip coverage area and is bonded to the first circuit layer. The ratio of the line laying area of the second line layer to the line laying area of the first line layer is between 0.9 and 1.2 in the first zone and the third zone.

In an embodiment of the present invention, the length of the first side region in the longitudinal direction and the length of the second side region in the longitudinal direction are respectively 1/4 to 1/4 of the long side length of the chip coverage area. 1/6.

In an embodiment of the present invention, the length of the first side region in the longitudinal direction and the length of the second side region in the longitudinal direction are respectively 1/5 of the length of the long side of the chip coverage area.

In an embodiment of the present invention, the above-mentioned chip coverage area is expanded by a distance to form the edges of the first area, the second area and the third area.

In an embodiment of the present invention, the edge and the chip coverage area include a first expansion area surrounding three sides of the first side area, a second expansion area adjacent to two opposite sides of the central area and a second expansion area surrounding the first side area. The third outer expansion area on the three sides of the two side areas, wherein the first area includes the first side area and the first outer expansion area, the second area includes the central area and the second outer expansion area, and the third area includes the second outer expansion area. The side area and the third expansion area.

In an embodiment of the present invention, the above-mentioned distance is 1/8 to 1/12 of the length of the long side of the chip coverage area.

In an embodiment of the present invention, the above-mentioned distance is 1/10 of the length of the long side of the chip coverage area.

In an embodiment of the present invention, the above-mentioned distance is 400 microns.

In an embodiment of the present invention, the ratio of the above-mentioned line laying area of the second line layer to the line laying area of the first line layer is not greater than 1.5 in the second area.

In an embodiment of the present invention, the above-mentioned chip is bonded to the first circuit layer through a plurality of bumps.

Based on the above, in the packaging process (such as the internal pin bonding process) of the film-on-chip packaging structure of the present invention, the chip coverage area of the flexible substrate is most affected by the thermal effect, especially the warping at the two sides of the corresponding chip. The amount of warpage is larger than that at the center of the corresponding chip. Therefore, the circuit layout on the flexible substrate is designed to be the ratio of the circuit laying area of the second circuit layer to the circuit laying area of the first circuit layer. The first area and the third area on both sides of the chip are between 0.9 and 1.2, so that the ratio of the laying area of the lines on the two opposite surfaces of the flexible substrate is similar, so the flexible substrate can be avoided. The warpage deformation caused by the uneven stress caused by the difference in the thermal expansion coefficients of the two surfaces, thereby improving the problems of poor pin bonding, peeling or cracking, and improving the reliability of the film-on-chip package structure.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Description of drawings

FIG. 1A is a partial top schematic view of a chip on film package structure according to an embodiment of the present invention;

Fig. 1B is a partial enlarged view of region B in Fig. 1A;

2A is a schematic bottom view of a portion of a chip on film package structure according to an embodiment of the present invention;

Fig. 2B is a partial enlarged view of region C in Fig. 2A;

FIG. 3 is a schematic cross-sectional view of the chip on film package structure of FIG. 1A along the line A-A.

It should be noted that the chips, bumps and solder mask in FIG. 1A and FIG. 1B are represented by perspective drawing, and the encapsulation compound is omitted. The solder mask layers in FIGS. 2A and 2B are also represented by perspective drawing.

Detailed ways

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or like parts.

Directional terms (eg, top, bottom, right, left, front, back, top, bottom) as used herein are used only for reference to the drawings and are not intended to imply absolute orientation.

The present invention will be more fully explained with reference to the accompanying drawings of this embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses, dimensions or dimensions of layers or regions in the drawings may be exaggerated for clarity. The same or similar reference numerals denote the same or similar elements, and the detailed description in the following paragraphs will not be repeated.

FIG. 1A is a partial top schematic view of a chip on film package structure according to an embodiment of the present invention. FIG. 1B is a partial enlarged view of area B in FIG. 1A . FIG. 2A is a schematic bottom view of a portion of a chip on film package structure according to an embodiment of the present invention. FIG. 2B is a partial enlarged view of area C in FIG. 2A . FIG. 3 is a schematic cross-sectional view of the chip on film package structure of FIG. 1A along the line A-A. Please refer to FIG. 1 to FIG. 3 , in this embodiment, the chip on film package structure 100 includes a flexible substrate 110 , a first circuit layer 120 , a second circuit layer 130 and a chip 140 , wherein the flexible substrate 110 has a relatively The first surface 110a and the second surface 110b of the first surface 110a and the chip coverage area 112 located on the first surface 110a. Further, the chip coverage area 112 may include two opposite long sides 112L and two opposite short sides 112S, and the chip coverage area 112 is divided into a second area adjacent to one of the two short sides 112S along the long side direction D A side area 1121, a central area 1122, and a second side area 1123 adjacent to the other one of the two short sides 112S, wherein the flexible substrate 110 includes a first side area 1121, a central area 1122, and a second side area 1122 corresponding respectively The first region R1 , the second region R2 and the third region R3 of the side region 1123 . On the other hand, the first circuit layer 120 and the second circuit layer 130 are respectively located on the first surface 110 a and the second surface 110 b , and the chip 140 is disposed in the chip coverage area 112 and bonded to the first circuit layer 120 . For example, the chip 140 is bonded and electrically connected to the first wiring layer 120 through a plurality of bumps 142, but the invention is not limited thereto.

Here, the material of the flexible substrate 110 is, for example, polyethylene terephthalate (PET), polyimide (PI), polyethersulfone (PES), and polycarbonate (PC). ) or other suitable flexible materials, the material of the first circuit layer 120 and the second circuit layer 130 is, for example, copper (a double-sided copper foil substrate can be formed) or other suitable conductive metal materials, and the chip 140 can be a driver chip or any suitable chip.

In this embodiment, the chip on film package structure 100 designs the circuit layout on the flexible substrate 110 such that the ratio of the circuit laying area of the second circuit layer 130 to the circuit laying area of the first circuit layer 120 is in the first region R1 The inner and third regions R3 are between 0.9 and 1.2, so that the ratio of the laying area of the lines on the two opposite surfaces (the first surface 110 a and the second surface 110 b ) of the flexible substrate 110 is similar, so it can be avoided. The flexible substrate 110 is warped and deformed due to the uneven stress caused by the difference in the thermal expansion coefficients of the two surfaces, thereby improving the problems of poor pin bonding, peeling or cracking, and improving the film-on-chip package structure 100. reliability. Further, because the mismatch of the thermal expansion coefficient between the flexible substrate 110 of the flexible material and the circuit layer of the metal material is positively related to the laying area of the circuit layer, and the larger the mismatch of the thermal expansion coefficient, the greater the Therefore, if the difference in the ratio of the laying area of the lines on the two opposite surfaces of the flexible substrate 110 is larger, the more uneven thermal stress will be formed on the two opposite surfaces accordingly, resulting in the flexible substrate 110 110 more obvious warping deformation. In addition, in the inner pin bonding process, the chip 140 is generally bonded to the chip footprint 112 of the flexible substrate 110 by thermocompression, so the thermal effect on the chip footprint 112 is more intense, and the flexible substrate 110 The warpage deformation of the first side region 1121 and the second side region 1123 corresponding to the two sides of the chip 140 (that is, adjacent to the two short sides 112S) of the chip coverage area 112 is larger than that of the central region 1122 corresponding to the center of the chip 140 Therefore, the thin film-on-chip package structure 100 of the present embodiment targets the flexible substrate 110 in the first region R1 and the third region R3 corresponding to the first side region 1121 and the second side region 1123 At this point, the layout area of the circuit layers on the opposite two surfaces (the first surface 110 a and the second surface 110 b ) is designed to be approximated, so that the circuit layout area of the second circuit layer 130 is the same as the circuit layout area of the first circuit layer 120 The ratio is between 0.9 and 1.2, so that the ratio of the laying area of the circuit is similar, so it can reduce the warpage caused by uneven thermal stress, improve the problem of poor pin bonding, peeling or breaking, and then improve the thin film flip chip packaging. Reliability of structure 100.

In some embodiments, the length L1 of the first side region 1121 in the longitudinal direction D and the length L2 of the second side region 1123 in the longitudinal direction D are respectively 1 of the long side length L of the chip footprint 112 . /4 to 1/6. Further, the length L1 of the first side region 1121 in the longitudinal direction D and the length L2 of the second side region 1123 in the longitudinal direction D may be respectively 1/1 of the long side length L of the chip footprint 112 5, but the present invention is not limited to this.

In some embodiments, the length L1 of the first side region 1121 in the longitudinal direction D is the same as the length L2 of the second side region 1123 in the longitudinal direction D, but the present invention is not limited to this, depending on the actual design The length L1 of the first side region 1121 in the longitudinal direction D and the length L2 of the second side region 1123 in the longitudinal direction D may be different.

In some embodiments, the chip coverage area 112 is expanded by a distance d to form the edge e of the first area R1 , the second area R2 and the third area R3 . Further, the edge e and the chip coverage area 112 may include three sides surrounding the first side area 1121 (eg, one of the two short sides 112S and one of the two long sides 112L connecting the aforementioned short sides 112S) The first outer expansion area E1 of the side part section), the second outer expansion area E2 adjacent to the opposite sides of the central area 1122 (such as the middle part section of the two long sides 112L), and the second outer expansion area E2 surrounding the second side area 1123. The third expansion area E3 of three sides (eg, the other one of the two short sides 112S and the other side part section connecting the two long sides 112L of the aforementioned short sides 112S), wherein the first area R1 includes the first The side area 1121 and the first expanding area E1, the second area R2 includes the central area 1122 and the second expanding area E2, and the third area R3 includes the second side area 1123 and the third expanding area E3. Since the thermal effect during the inner pin bonding process mainly acts on the chip coverage area 112 and its adjacent areas, especially the warping deformation caused by the heat in the area adjacent to the two short sides 112S is more obvious. Therefore, for the two adjacent short sides 112S respectively The first region R1 (corresponding to the first side region 1121 ) and the third region R3 (corresponding to the second side region 1123 ) are designed to design the area ratio of the lines on the two surfaces, which can more effectively improve the film-on-chip packaging structure. The warpage deformation of 100 and the problems of poor pin bonding, peeling or fracture further improve the reliability of the chip on film package structure 100, but the present invention is not limited thereto.

In some embodiments, the distance d is 1/8 to 1/12 of the length L of the long side of the chip footprint 112 . Further, the distance d may be 1/10 of the length L of the long side of the chip footprint 112 . For example, the distance d may be 400 microns. It should be noted that the present invention is not limited to the numerical value and range of the above-mentioned outward expansion distance, and the outward expansion distance may be determined according to actual design requirements.

In some embodiments, since the deformation of the flexible substrate 110 in the central area of the chip coverage area 112 is relatively small, warpage is likely to be caused when the difference in the thermal expansion coefficients of the two surfaces is too large. The ratio of the circuit laying area of the second circuit layer 130 in the second area R2 to the circuit laying area of the first circuit layer 120 is designed to be no greater than 1.5, compared to the second circuit in the first area R1 and the third area R3. The ratio of the circuit laying area of the layer 130 to the circuit laying area of the first circuit layer 120 has greater flexibility in spatial application, but the invention is not limited thereto.

In some embodiments, the chip on film package structure 100 further includes a solder mask layer 150 , wherein the solder mask layer 150 is located on the flexible substrate 110 and partially covers the first circuit layer 120 and the second circuit layer 130 to prevent The electrical capability of the first circuit layer 120 and the second circuit layer 130 is affected by contamination by water vapor or foreign matter, but the invention is not limited thereto.

In some embodiments, the chip on film package structure 100 further includes an encapsulating compound 160 , and the encapsulating compound 160 can be filled into the gap between the chip 140 and the flexible substrate 110 , so as to electrically connect the chip 140 and the flexible substrate 110 . Sex contacts are protected. The encapsulant 160 is, for example, underfill, but the present invention is not limited thereto.

To sum up, in the packaging process (such as the inner pin bonding process) of the film-on-chip package structure of the present invention, the chip coverage area of the flexible substrate is subjected to the strongest thermal effect, especially at the two sides of the corresponding chip. The warpage deformation is larger than that at the center of the corresponding chip. Therefore, the circuit layout on the flexible substrate is designed as the ratio of the circuit laying area of the second circuit layer to the circuit laying area of the first circuit layer. The first area and the third area at the two sides of the corresponding chip are between 0.9 and 1.2, so that the circuit laying area ratios on the two opposite surfaces of the flexible substrate are similar, so that the flexible substrate can be avoided. The warpage deformation caused by the uneven stress caused by the difference in the thermal expansion coefficients of the two surfaces of the flexible substrate, thereby improving the problems of poor pin bonding, peeling or cracking, and improving the reliability of the film-on-chip package structure.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features thereof can be equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present invention. scope.

Claims (10)

1. A film-on-chip packaging structure, characterized in that, comprising: A flexible substrate having opposite first and second surfaces and a chip coverage area located on the first surface, the chip coverage area is divided into a first side area, a central area and a second side along the longitudinal direction an edge region, the flexible substrate includes a first region, a second region and a third region corresponding to the first side region, the central region and the second side region respectively; a first circuit layer, located on the first surface; a second wiring layer on the second surface; and a chip, disposed in the chip coverage area and bonded to the first circuit layer, wherein The ratio of the line laying area of the second line layer to the line laying area of the first line layer is between 0.9 and 1.2 in the first area and the third area. 2 . The chip-on-film package structure according to claim 1 , wherein the length of the first side region in the longitudinal direction is the same as the length of the second side region in the longitudinal direction. 3 . The lengths are respectively 1/4 to 1/6 of the length of the long side of the chip coverage area. 3 . The chip-on-film package structure according to claim 2 , wherein the length of the first side region in the longitudinal direction is the same as the length of the second side region in the longitudinal direction. 4 . The lengths are respectively 1/5 of the length of the long side of the chip coverage area. 4 . The chip-on-film package structure of claim 1 , wherein the chip coverage area is extended by a distance to form edges of the first area, the second area, and the third area. 5 . 5 . The chip-on-film package structure according to claim 4 , wherein the edge and the chip coverage area comprise a first expansion area surrounding three sides of the first side area, and adjacent to The second outer expansion area on the opposite two sides of the central area and the third outer expansion area surrounding the three sides of the second side area, wherein the first area includes the first side area and the third outer expansion area. an expansion area, the second area includes the central area and the second expansion area, and the third area includes the second side area and the third expansion area. 6 . The chip on film package structure according to claim 4 , wherein the distance is 1/8 to 1/12 of the length of the long side of the chip coverage area. 7 . 7 . The chip on film package structure according to claim 6 , wherein the distance is 1/10 of the length of the long side of the chip coverage area. 8 . 8 . The chip on film package structure according to claim 4 , wherein the distance is 400 μm. 9 . 9 . The chip-on-film package structure according to claim 1 , wherein the ratio of the circuit laying area of the second circuit layer to the circuit laying area of the first circuit layer in the second region is 10 . not greater than 1.5. 10 . The chip on film package structure of claim 1 , wherein the chip is bonded to the first circuit layer through a plurality of bumps. 11 .

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