KR101279469B1 - Cof package having improved heat dissipation - Google Patents

Abstract

The present invention discloses a chip on film package having improved heat dissipation. Chip on film package according to an embodiment of the present invention is an insulating layer formed via holes for heat dissipation, a circuit pattern portion located on one surface of the insulating layer, is located on the via hole in the same layer as the circuit pattern portion At least one heat dissipation dummy part, and an electronic device chip mounted on the heat dissipation dummy part. According to the present invention, it is possible to efficiently dissipate heat generated from the COF package to the outside to prevent the COF chip from overheating and malfunction or damage.

Description

Chip-on-film package with improved heat dissipation {COF PACKAGE HAVING IMPROVED HEAT DISSIPATION}

The present invention relates to a chip on film package, and more particularly to a chip on film package with improved heat dissipation.

Recently, with the trend of thinning, miniaturization, high integration, high speed, and pinning of semiconductor devices, the use of tape wiring boards is increasing in the field of semiconductor chip mounting technology. The tape wiring board has a structure in which a wiring pattern and a lead connected thereto are formed on a thin film made of an insulating material such as polyimide resin, and a tab (TAB) for collectively joining bumps previously formed on a semiconductor chip and the leads of the tape wiring board (TAB) Tape Automated Bonding technology can be applied. Due to these characteristics, the tape wiring board is also called a TAB tape. In addition, an example of a tape wiring board and a semiconductor package to which the tape wiring board is applied is a tape carrier package (TCP).

However, due to lower cost, fine pitch, flexibility, and capable of carrying passive elements, chip-on-glass (COG) in large TFT-LCD panels The proportion of driver ICs employing on-glass packaging and chip-on-film (COF) packaging is increasing.

Therefore, there are more market requirements for driver ICs with COG and COF packaging.

Due to the demand for higher frame frequencies, drive voltages, and higher display channels of TFT-LCD panels, the thermal dissipation capability of driver ICs is becoming increasingly important.

1 shows a COF packaging structure according to the prior art.

As shown in FIG. 1, the COF packaging structure includes a polyimide film 110, an adhesive layer 120 located on one side of the polyimide film 110, and a metal layer located on the adhesive layer 120. 130, a solder resist layer 140 disposed on the metal layer 130. The metal layer 130 becomes the circuit pattern layer 130 through an etching process, and the electronic device chip 160 is bonded through the metal bumps 150 as a bonding pad on the circuit pattern layer 130. In addition, the molding unit 170 may be formed using a resin or the like to fix and protect the electronic device chip 160.

In this COF packaging structure, the circuit pattern layer 130 is surrounded by the polyimide film 110 and the solder resist layer 140, and the electronic device chip 16 is also molded by the molding unit 170, thereby providing a COF. The exothermicity of the packaging structure is very low.

However, the proportion of driver ICs employing chip-on-glass (COG) and chip-on-film (COF) packaging in large TFT-LCD panels is increasing. Accordingly, there are more market requirements for driver ICs with COG and COF packaging, and there is a need to improve the heat generation of the COF packaging structure.

The present invention has been made to solve the above-described problem, an object of the present invention is to provide a COF package excellent in heat dissipation.

According to an embodiment of the present invention, a chip on film (Chip On Flim) package includes an insulating layer having a via hole for heat dissipation, a circuit pattern part disposed on one surface of the insulating layer, and the circuit And at least one heat dissipation dummy part positioned on the via hole in the same layer as the pattern part, and an electronic device chip mounted on the heat dissipation dummy part.

The heat dissipation dummy part may be simultaneously formed with the circuit pattern layer.

The chip on film package may further include a heat sink formed by filling the via hole with a heat sink material.

The heat sink material may be a material having high thermal conductivity.

The heat sink portion may include a heat sink material attached to the vicinity of the via hole in succession to the heat sink material filling the via hole.

The insulating layer may be implemented as a polyimide (PI) film.

The heat dissipation dummy part may be connected to the circuit pattern part.

The heat dissipation dummy part may include a connection part extending from the heat dissipation dummy part and connected to the circuit pattern part.

The via hole may have a size smaller than that of the heat radiation dummy part.

The present invention includes a heat dissipation dummy part for dissipating heat of an electronic circuit chip mounted on a circuit pattern part on an insulating layer in a COF package in the same layer as the circuit pattern part, and via holes exposing the heat dissipation dummy part to the outside in the insulating layer. It is possible to efficiently dissipate heat generated from the COF package to the outside to prevent the semiconductor chip from overheating, malfunction or damage. That is, according to the present invention, the temperature of the chip is lowered, thereby reducing the defective rate due to heat of the electronic device chip.

1 shows a COF packaging structure according to the prior art.
2 is a view for explaining the concept of the present invention.
3 illustrates COF packages in accordance with one embodiment of the present invention.
4 is a view showing the front view with the electronic device chip removed from the COF package.
5 illustrates COF packages in accordance with other embodiments of the present invention.
6 is a view showing a front view in the state in which the electronic device chip is removed from the COF package.
7 shows an enlarged actual photograph of a portion of a COF package according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail to avoid unnecessarily obscuring the subject matter of the present invention. In addition, the size of each component in the drawings may be exaggerated for the sake of explanation and does not mean a size actually applied.

2 is a view for explaining the concept of the present invention.

Referring to FIG. 2A, the COF package includes an insulating layer 210 having a heat dissipation via hole 212, a circuit pattern portion 230 formed on one surface of the insulating layer 210, and a circuit pattern portion ( And a heat dissipation dummy part 240 formed on the same layer as 230. In addition, the COF package may include a solder resist layer, an electronic device chip, and the like. The insulating layer 210 is preferably implemented with a polyimide (PI) film. Referring to FIG. 2A, a via hole 212 for heat dissipation is formed in the insulating layer 210 in a region where an electronic device chip (not shown) is mounted. The heat dissipation dummy part 240 is disposed on the via hole 212 of the insulating layer 210 and radiates heat generated from the electronic device chip to the outside through the via hole 212. The via hole 212 may be formed by etching a portion of the insulating layer 210 with a laser. In other words, a via hole for exposing the heat dissipation dummy part 240 to the outside is formed in the insulating layer.

In other words, a heat dissipation dummy part 240 for dissipating heat of the electronic circuit chip mounted on the circuit pattern part 230 on the insulating layer 210 is formed on the same layer as the circuit pattern part 230. In detail, the heat dissipation dummy part 240 is positioned between the electronic device chip and the heat dissipation via hole 212, and thus, heat generated from the electronic device chip is conducted to the heat dissipation dummy part 240 to be transferred to the via hole 212. Can be divergent through.

The heat dissipation dummy part 240 may be simultaneously formed on the insulating layer 210 with the circuit pattern part 230. Specifically, the circuit pattern portion 230 is formed by forming a metal layer on the insulating layer 210, and then performing an etching process for the metal layer, wherein the metal layer is used for heat radiation as well as the circuit pattern portion 230. It is etched in a pattern including the dummy part 240. Since the heat dissipation dummy part 240 is made from the metal layer on which the circuit pattern part is formed, the thermal conductivity is high. In addition, the heat dissipation dummy part 240 is physically connected to the circuit pattern part 230, in this case, the circuit pattern. Heat generated from the unit 230 is transferred to the heat dissipation dummy unit 240. The heat dissipation dummy part 240 may be connected to the direct circuit pattern part 230. Alternatively, the heat dissipation dummy part 240 may include a connection part 242 extending from the heat dissipation dummy part and connected to the circuit pattern part 230.

According to another exemplary embodiment of the present invention, the heat sink may be formed by filling the via hole 212 formed in the insulating layer 210 with a heat sink material. In this case, heat generated in the circuit pattern layer 230 is discharged through the heat sink material filling the via hole 212 formed in the insulating layer 210. Here, the material of the heat sink may be selected from a material having high thermal conductivity, and a material having high thermal conductivity is well known in the art.

Referring to FIG. 2B, according to another embodiment of the present invention, the heat sink material 290 may be formed by attaching a heat sink material not only to the via hole 212 but also to the vicinity of the via hole 70. . That is, as shown, the heat sink material may be attached adjacent to the via hole 70 to be continuous with the heat sink material filling the via hole 70. Accordingly, heat transferred through the via hole 212 may be dissipated through the heat sink 290.

3 illustrates COF packages in accordance with one embodiment of the present invention. Referring to FIGS. 3A and 3B, the COF package includes an insulating layer 310 having a heat dissipation via hole 312, a circuit pattern portion 330 formed on one surface of the insulating layer 310, The heat dissipation dummy part 340, the electronic device chip 360, and the sealing part 370 molding the electronic device chip 360 are formed on the same layer as the circuit pattern part 330.

In FIGS. 3A and 3B, the electronic device chip 360 is directly connected to the circuit pattern unit 330. According to an embodiment, in FIG. 3A, the electronic device chip 360 is mounted on the circuit pattern part 330 so as not to directly contact the heat dissipation dummy part 340, and according to another embodiment, in FIG. 3B. The electronic device chip 360 is mounted on the circuit pattern part 330 to directly contact the heat radiating dummy part 340.

Referring to FIGS. 3A and 3B, the circuit pattern part 330 and the heat dissipation dummy part 340 are located on one surface of the insulating layer 310, and the circuit pattern part 330 and the heat dissipation dummy. The unit 340 may be formed at the same time. For example, after the metal layer is formed on one surface of the insulating layer 310, an etching process may be performed such that the circuit pattern part 330 and the heat dissipation dummy part 340 are formed on the metal layer.

The electronic device chip 360 is positioned on the circuit pattern part 330 and the heat dissipation dummy part 340. Specifically, the electronic device chip 360 covers the heat dissipation dummy part 340 and is positioned to be in contact with a part of the circuit pattern part 330. In this case, the size of the heat dissipation dummy part 340 is the electronic device chip ( It is desirable to be smaller than the size of 360).

In the insulating layer 310, a via hole 312 for heat dissipation is formed at a position corresponding to the heat radiating dummy part 340. In other words, the via hole 312 is formed in a portion of the insulating layer 310 in which the heat dissipation dummy part 340 is located, and the via hole 312 has a smaller size than the heat dissipation dummy part 340.

Accordingly, when heat is generated from the electronic device chip 360, the heat is transferred to the heat dissipation dummy part 340 positioned directly below the electronic device chip 360. In addition, the heat dissipation dummy part 340 is heated by heat generated by the electronic device chip 360, and the heat of the heat dissipation dummy part 340 is a via hole 312 exposing the heat dissipation dummy part 340 to the outside. Is emitted through). Thus, heat dissipation of the COF package is facilitated.

4 is a view showing the front view with the electronic device chip removed from the COF package.

Referring to FIGS. 4A and 4B, the circuit pattern part 330 and the heat dissipation dummy part 340 are formed on the insulating layer 310. A via hole 312 is formed directly under the heat dissipation unit 340, which is indicated by a dotted line in the drawing. In addition, a dotted line 362 covering the heat dissipation dummy part 340 and a part of the circuit pattern part 330 indicates a region in which the circuit device chip 360 is mounted later.

As shown, according to one embodiment, a plurality of via holes 312 may be formed in the mounting area of the heat dissipation dummy part 340 (FIG. 3A), and one via hole 312 according to another embodiment. ) May be formed (FIG. 3 (b)). The number of via holes 312 may be determined according to various conditions, for example, the design of a circuit pattern.

5 illustrates COF packages in accordance with other embodiments of the present invention.

Since the COF packages shown in FIG. 5 are basically similar in structure to the COF packages shown in FIG. 3, the related description of FIG. 3 is referred to. Also, a detailed description thereof is omitted except for the difference between the COF packages of FIG. 3 and the COF packages of FIG. 5.

In FIGS. 5A and 5B, the electronic device chip 460 is mounted on the heat dissipation dummy part 340. According to an embodiment, the electronic device chip 460 is partially bonded to the heat dissipation dummy part 440 through the adhesive 450 in FIG. 5A, and the electronic device chip (FIG. 5B) is according to another embodiment. The 460 may contact the entire heat dissipation dummy part 440 through the adhesive 452.

Referring to FIGS. 5A and 5B, the COF package includes an insulating layer 410 having a heat dissipation via hole 412, a circuit pattern part 430 formed on one surface of the insulating layer 410, The heat dissipation dummy part 440, the electronic device chip 460, and the molding part 470 molding the electronic device chip 460 are formed on the same layer as the circuit pattern part 430. In addition, the COF packages further include a wire 480 for connecting the electronic device chip 460 and the circuit pattern unit 430. The electronic device chip 460 is mounted on the heat dissipation dummy part 440 and is connected or connected to the circuit pattern part 430 through the wire 480.

As shown, the circuit pattern part 430 and the heat dissipation dummy part 440 are located on one surface of the insulating layer 410. As described above, the circuit pattern part 430 and the heat dissipation dummy part 440 are Can be formed at the same time.

The electronic device chip 460 is positioned on the heat radiating dummy part 440. Specifically, the electronic device chip 460 is disposed directly above the heat dissipation dummy part 440 and arranged to be connected to the circuit pattern part 430 through the wire 480.

6 is a view showing a front view in the state in which the electronic device chip is removed from the COF package.

6A and 6B, a circuit pattern part 430 and a plurality of heat dissipation dummy parts 440 are formed on the insulating layer 410. The plurality of heat dissipation dummy parts 440 are located in an area 462 in which the circuit device chip 360 is mounted. In addition, a plurality of via holes 412 are formed at positions corresponding to the plurality of heat dissipation dummy parts 440, which are indicated by dotted lines in the drawing. The size of the via hole 412 is smaller than that of the corresponding heat dissipation dummy part 440, and the shape of the via hole 412 may be similar to that of the heat dissipation dummy part 440. However, the present invention is not limited thereto and may have any shape as long as the size of the via hole 412 is smaller than the size of the corresponding heat dissipation dummy part 440.

As shown in FIG. 6A, the heat dissipation dummy part 440 may include a connection part 442 extending from the heat dissipation dummy part and physically connected to the circuit pattern part 430. Likewise, the heat radiating dummy part 440 may be physically spaced apart from the circuit pattern part 430. When the heat dissipation dummy part 440 is connected to the circuit pattern part 430 through the connection part 442, heat generated from the circuit pattern part 430 may be better transmitted to the heat dissipation dummy part 440. 7 shows an enlarged actual photograph of a portion of a COF package according to the present invention.

Referring to FIG. 7, the photographs indicated by reference numerals 10, 30, 50 and 60 show a circuit design diagram of a circuit pattern portion in an OCF package, and reference numerals 12, 32, 52 and 62 are actually implemented according to the corresponding circuit design diagram. The corresponding parts of the generated COF package.

Referring to the upper left of FIG. 7, one heat dissipation dummy part 240 is formed, and a plurality of via holes 212 are formed on the insulating layer 210 in the mounting region of the heat dissipation dummy part 240. . The heat dissipation dummy part 240 is spaced apart from the circuit pattern part 230. Referring to the upper left of FIG. 7, a plurality of heat dissipation dummy parts 240 are formed, and via holes 212 are formed to correspond to the heat dissipation dummy parts 240, respectively.

In addition, referring to the upper right side of FIG. 7, a plurality of heat dissipation dummy parts 240 are formed, and via holes 212 are formed to correspond to the heat dissipation dummy parts 240, respectively. Each of the heat dissipation dummy parts 240 is physically connected to the circuit pattern part 230 through the connection part 242. Referring to the lower right side of FIG. 7, one heat dissipation dummy part 240 is formed, and one via hole 212 is formed on the insulating layer 210 in the mounting region of the heat dissipation dummy part 240. .

As described above, the present invention includes a via hole for dissipating heat from an electronic circuit chip mounted on a circuit pattern portion on an insulating layer in a COF package in the same layer as the circuit pattern portion and exposing the heat dissipation dummy portion to the outside. It is formed on the insulating layer to efficiently dissipate heat generated from the COF package to the outside to prevent the semiconductor chip from overheating, malfunction or damage.

Although not shown in FIGS. 3 to 7, as described with reference to FIG. 2, the heat sink may be formed by filling the via hole formed in the insulating layer with a heat sink material. In this case, heat generated in the circuit pattern portion is released through the heat sink material filling the via holes formed in the insulating layer. In another embodiment, the heat sink material may be formed by attaching the heat sink material not only in the via hole but also in the vicinity of the via hole. Thus, heat transferred through the heat sink material filling the via holes can be dissipated through the heat sink portion.

In the foregoing detailed description of the present invention, specific examples have been described. However, various modifications are possible within the scope of the present invention. The technical spirit of the present invention should not be limited to the above-described embodiments of the present invention, but should be determined by the claims and equivalents thereof.

210: insulating layer 212: via hole
230: circuit pattern portion 240: heat dissipation dummy portion

Claims (9)

An insulating layer having a via hole for heat dissipation;
A circuit pattern part located on one surface of the insulating layer;
At least one heat dissipation dummy part disposed on the via hole in the same layer as the circuit pattern part;
An electronic device chip mounted on the heat dissipation dummy part,
The heat dissipation dummy part is connected to the circuit pattern part, a chip on film (Chip On Flim) package. The method of claim 1,
The heat dissipation dummy portion is a chip on film package formed at the same time as the circuit pattern portion. The method of claim 1,
The chip on film package further comprises a heat sink formed by filling the via hole with a heat sink material. delete The method of claim 3,
And the heat sink portion includes a heat sink material attached adjacent to the via hole so as to be continuous with the heat sink material filling the via hole. The method of claim 1,
The insulating layer is a chip-on film package implemented with a polyimide (PI) film. delete The method of claim 1,
The heat dissipation dummy portion is a chip on film package including a connection portion extending from the heat dissipation dummy portion connected to the circuit pattern portion. The method of claim 1,
The via hole is a chip on film package having a smaller size than the heat radiation dummy portion.

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