CN115117150B - GaN HEMT power device and preparation method thereof - Google Patents

Abstract

The invention discloses a GaN HEMT power device and a preparation method thereof, belonging to the technical field of semiconductors, wherein the device comprises a third substrate, a second middle layer, a buffer layer, a GaN layer and an AlGaN layer which are sequentially connected from bottom to top; a source electrode, a drain electrode and a grid electrode are arranged on the AlGaN layer, wherein the source electrode and the drain electrode are both connected into the GaN layer in an extending mode; the GaN layer is provided with a cavity, the lower end of the cavity extends into the buffer layer, and the upper end of the cavity is located below the source electrode and the drain electrode. According to the invention, the cavity is formed on the GaN layer, so that the thickness of the GaN layer below the channel is reduced, the leakage is reduced, and the two-dimensional electron gas density of the AlGaN/GaN interface is increased, and the performance of the device is improved.

Description

A GaN HEMT power device and its manufacturing method

technical field

The invention relates to the technical field of semiconductors, in particular to a GaN HEMT power device and a preparation method thereof.

Background technique

Traditional GaN HEMT devices need to grow AlGaN/GaN materials on silicon substrates, and then manufacture HEMT devices. The two factors that affect GaN HEMT devices are the tensile strain of the AlGaN layer and the leakage of the GaN layer. The core working principle of the GaN HEMT device is The AlGaN layer exhibits tensile strain and has two polarization effects: spontaneous polarization and piezoelectric polarization, while the GaN layer only has a spontaneous polarization effect. Because of the difference in polarization effects, an induced two-dimensional electron gas is generated at the AlGaN/GaN interface. , the concentration of two-dimensional electron gas determines the conductivity of the device, so increasing the tensile strain of the AlGaN layer is conducive to increasing the concentration of two-dimensional electron gas and improving device performance. In addition, when growing AlGaN/GaN on a silicon substrate, due to lattice mismatch and thermal mismatch problems, after the growth is completed, the GaN layer is subjected to huge tensile stress, which causes a large number of dislocations to be generated in the AlGaN/GaN layer. Mistakes will lead to increased leakage of power devices and seriously affect device performance.

Contents of the invention

The purpose of the present invention is to overcome the problems of insufficient concentration of two-dimensional electron gas induced at the interface of AlGaN/GaN and electric leakage in existing GaN HEMT devices, and provide a GaN HEMT power device and a preparation method thereof.

The purpose of the present invention is achieved through the following technical solutions:

In one solution, a GaN HEMT power device is provided, comprising a third substrate, a second intermediate layer, a buffer layer, a GaN layer, and an AlGaN layer sequentially connected from bottom to top; the AlGaN layer is provided with a source, a drain electrode and gate, wherein the source and drain are both extended and connected to the GaN layer; a cavity is arranged in the GaN layer, and the lower end of the cavity extends into the buffer layer, the The upper end of the cavity is located below the channel of the source and drain.

As a preferred item, in a GaN HEMT power device, the thickness of the GaN layer above the cavity is 0.2 um-1 um.

As a preferred item, in a GaN HEMT power device, the third substrate is a silicon substrate or an SOI wafer.

As a preferred item, in a GaN HEMT power device, p-type GaN is epitaxially formed on the AlGaN layer, and the gate is located on the p-type GaN.

As a preferred item, a GaN HEMT power device, an enhancement silicon MOSFET device is connected to the AlGaN layer.

In another solution, a method for preparing a GaN HEMT power device is provided, the method comprising the following steps:

S1, sequentially epitaxially epitaxial buffer layer, GaN layer and AlGaN layer on the first substrate;

S2. Spin coating or depositing a first intermediate layer on the AlGaN layer, and bonding a second substrate on the first intermediate layer;

S3. Grinding and selective etching to remove the first substrate leaking the buffer layer, spin-coating a photoresist on the buffer layer and opening a window;

S4, sequentially etching the buffer layer and the GaN layer to form an etching groove, where the etching groove extends to the inside of the GaN layer and then stops etching and removes the photoresist;

S5, bonding a third substrate on which a second intermediate layer is spin-coated or deposited on the buffer layer, and allowing the second intermediate layer to cover the etching groove to form a cavity;

S6, removing the first intermediate layer and the second substrate, and manufacturing a source, a drain, and a gate on the AlGaN layer to obtain a GaN HEMT power device.

As a preferred item, a method for manufacturing a GaN HEMT power device, the first substrate, the second substrate and the third substrate are all selected from silicon substrates.

As a preferred item, in a method for manufacturing a GaN HEMT power device, in the step S6, the channels of the source and the drain are arranged at the upper end of the cavity.

As a preferred item, a method for preparing a GaN HEMT power device, the method further includes:

P-type GaN is epitaxially formed on the AlGaN layer, and a gate is formed on the p-type GaN.

As a preferred item, a method for preparing a GaN HEMT power device, the method further includes:

An enhancement mode silicon MOSFET device is connected on the AlGaN layer.

It should be further explained that the technical features corresponding to the above options can be combined or replaced to form a new technical solution if there is no conflict.

Compared with prior art, the beneficial effect of the present invention is:

In the present invention, a cavity is provided in the GaN layer, and the lower end of the cavity is extended into the buffer layer, and the upper end of the cavity is located below the channel of the source electrode and the drain electrode. The formation of the cavity leads to stress redistribution, and the corresponding cavity The lattice in the area above the cavity is further stretched, and the AlGaN laminated electric polarization increases significantly, which increases the two-dimensional electron gas density at the AlGaN/GaN interface; at the same time, a cavity is formed under the channel of the source and drain, which significantly reduces the The thickness of the GaN layer reduces the leakage channel, which is beneficial to reduce the leakage and greatly improves the performance of the device.

Description of drawings

Fig. 1 is a structural diagram of a GaN HEMT power device shown in the present invention;

Fig. 2 is a schematic structural diagram showing p-type GaN epitaxially on a GaN HEMT power device shown in the present invention;

FIG. 3 is a schematic structural diagram of an epitaxially enhanced silicon MOSFET device on a GaN HEMT power device shown in the present invention;

FIG. 4 is a schematic structural diagram of an epitaxial AlGaN/GaN layer on an SOI substrate based on FIG. 3 shown in the present invention;

FIG. 5 is a schematic diagram of another GaN HEMT power device based on FIG. 3 shown in the present invention;

6 is a schematic diagram of sequentially epitaxial buffer layer, GaN layer and AlGaN layer on the first substrate shown in the present invention;

7 is a schematic diagram of spin-coating or depositing a first intermediate layer on the AlGaN layer and bonding a second substrate on the first intermediate layer shown in the present invention;

FIG. 8 is a schematic diagram of sequentially etching the buffer layer and the GaN layer to form an etching groove shown in the present invention;

Fig. 9 is a schematic diagram of forming a cavity shown in the present invention.

Explanation of symbols in the figure: 1. third substrate; 2. second intermediate layer; 3. buffer layer; 4. GaN layer; 5. AlGaN layer; 6. cavity; 7. p-type GaN; 8. first substrate bottom; 9, the first intermediate layer; 10, the second substrate.

detailed description

The technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms belonging to "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated direction or positional relationship is based on the direction or positional relationship described in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, or in a specific orientation. construction and operation, therefore, should not be construed as limiting the invention. In addition, belonging to "first" and "second" is only for descriptive purposes, and should not be understood as indicating or implying relative importance.

In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as there is no conflict with each other.

In the present invention, mainly by setting a cavity in the GaN layer, the AlGaN lamination polarization is significantly increased, the two-dimensional electron gas density of the AlGaN/GaN interface is increased, the leakage channel is reduced, and the purpose of improving device performance is achieved.

Example 1

In an exemplary embodiment, a GaN HEMT power device is provided. As shown in FIG. 1, the device includes a third substrate 1, a second intermediate layer 2, a buffer layer 3, and a GaN layer 4 connected in sequence from bottom to top. and an AlGaN layer 5; the AlGaN layer 5 is provided with a source, a drain and a gate, wherein the source and the drain are both extended and connected to the GaN layer 4; the GaN layer 4 is provided with A cavity 6 , the lower end of the cavity 6 extends into the buffer layer 3 , and the upper end of the cavity 6 is located below the channel of the source and the drain. The third substrate 1 is a silicon substrate or an SOI wafer.

Specifically, during the epitaxial growth process, because the thermal expansion coefficient of the GaN layer 4 is greater than that of the silicon substrate, it is in a lattice expansion state when growing at high temperature, and when the temperature is lowered to normal temperature, the silicon substrate and the GaN layer 4 lattice shrink simultaneously. However, affected by the silicon substrate, the GaN layer 4 cannot shrink to the normal lattice at room temperature, but is larger than the normal lattice, so both the GaN layer 4 and the AlGaN layer 5 are subject to tensile strain. The tensile strain of GaN layer 4 is only due to thermal expansion and not fully contracted. The direct reason for the tensile strain of AlGaN layer 5 is because AlGaN is very thin, and it grows co-lattice with GaN layer 4, but the lattice constant of AlGaN is smaller than that of GaN, and the co-lattice When growing, the AlGaN lattice is the same as GaN, so it exhibits large tensile strain. Therefore, the piezoelectric polarization of AlGaN is strong. Because the GaN layer 4 is very thick, although it has a small tensile strain, the piezoelectric polarization effect is not obvious and can be ignored.

Furthermore, the formation of the cavity 6 leads to stress redistribution, and the regional lattice on both sides of the cavity 6 further shrinks, approaching the normal lattice state, and the corresponding lattice of the region above the cavity 6 is further stretched, showing a stronger tensile strain , so that the piezoelectric polarization of the corresponding AlGaN layer 5 increases significantly. Although the GaN layer 4 also has a piezoelectric polarization enhancement effect, because its film thickness is relatively large, the piezoelectric polarization enhancement effect is not obvious. The overall effect is that the enhancement of the piezoelectric polarization of the AlGaN layer 5 leads to an increase in the two-dimensional electron gas density at the AlGaN/GaN interface and an increase in device performance.

Furthermore, in the figure, the cavity 6 is mainly located under the source and drain channels, which significantly reduces the thickness of the GaN layer 4, thereby reducing leakage channels, which is beneficial to reducing leakage.

Further, the GaN layer 4 cannot be completely etched away in the cavity 6, otherwise the two-dimensional electron gas does not exist, and the thickness of the GaN layer 4 above the cavity 6 is preferably 0.2 um-1 um.

Example 2

Based on Embodiment 1, a GaN HEMT power device is provided. As shown in FIG. 2 , p-type GaN7 is epitaxially formed on the AlGaN layer 5 , and the gate is located on the p-type GaN7.

Specifically, the device obtained in Example 1 is a normally-on device (depletion-mode DMODE), and most applications need to use a normally-off device (enhanced EMODE), and a layer of p-type GaN7 needs to be epitaxially grown on the AlGaN layer 5 , re-manufacturing the gate on the p-type GaN, this device structure makes the electrons in the channel region under the gate depleted, and the device is in a normally-off state. When actually preparing the device, the epitaxial pGaN layer can be selected in the first step, or the epitaxial layer can be directly formed before the device in the structure of the first embodiment.

Example 3

Based on Embodiment 1, a GaN HEMT power device is provided. As shown in FIG. 3 , an enhancement silicon MOSFET device is connected to the AlGaN layer 5 .

Specifically, the manufacture of p-type GaN in Example 2 is very difficult, because the activation efficiency of P-type doping elements (generally magnesium) in GaN materials is very low, and P-type doping of GaN materials is very difficult, and the quality of p-type GaN is not ideal. , On the other hand, the threshold voltage of the EMODE device based on this structure is low, and the driving circuit support needs to be designed during use. Therefore, another solution is provided in this embodiment, by connecting an enhancement mode silicon MOSFET in series with a depletion mode GaN HEMT, using the source and gate of the silicon MOSFET as the source and gate of the entire device, the GaN HEMT The drain of the device is used as the drain of the entire device, which is the so-called CASCODE mode.

Furthermore, the two devices are designed on the same substrate, and the silicon layer is isolated from the underlying GaN layer through the intermediate layer, without affecting each other. The two devices can be interconnected through the metal layer in the process, or they can be interconnected through packaging and wiring after the completion of the overall device to realize the CASCODE structure. The reason why the SOI material is used in this step is that the SOI material can define the thickness of the silicon layer very well, and the realization process is simple. In theory, it is also possible to directly use silicon instead of SOI, and then obtain a certain thickness of silicon through grinding and polishing processes, so that this structure can also be obtained, but it is more difficult to realize.

Example 4

Based on Embodiment 1, a GaN HEMT power device is provided, as shown in Figure 4, the difference between this device and the previous device is that an SOI sheet is bonded on one side downward, an additional silicon layer is added on the middle layer, and the top layer is used Silicon SOI is used as the initial substrate, because the silicon layer is thin, which can reduce the dislocation caused by the lattice mismatch of the GaN layer, and further improve the performance of the device.

Further, in another example, as shown in FIG. 5 , another GaN HEMT power device is provided, which is bonded to the SOI substrate during spin coating or deposition of an intermediate layer.

Example 5

Based on the same inventive concept as in Embodiment 1, referring to FIGS. 6-9 , a method for preparing a GaN HEMT power device is provided, the method comprising the following steps:

S1. As shown in FIG. 6 , epitaxially epitaxially buffer layer 3 , GaN layer 4 and AlGaN layer 5 on first substrate 8 ;

S2. As shown in FIG. 7 , spin-coat or deposit a first intermediate layer 9 on the AlGaN layer 5, and bond a second substrate 10 on the first intermediate layer 9; wherein, the first intermediate layer 9 When the deposition method is selected, the deposition material can be SiO2 or other materials, and if necessary, chemical mechanical polishing needs to be added;

S3. Grinding and selective etching to remove the first substrate 8 and leak the buffer layer 3, spin-coat photoresist on the buffer layer 3 and open a window;

S4. As shown in FIG. 8 , sequentially etch the buffer layer 3 and the GaN layer 4 to form an etching groove, wherein the etching groove extends to the inside of the GaN layer 4 and then stops etching and removes the photoresist;

S5. As shown in FIG. 9 , bond the third substrate 1 spin-coated or deposited with the second intermediate layer 2 on the buffer layer 3, and let the second intermediate layer 2 cover the etching groove , forming a cavity 6;

S6, removing the first intermediate layer 9 and the second substrate 10, and manufacturing a source, a drain, and a gate on the AlGaN layer 5 to obtain a GaN HEMT power device as shown in FIG. 1 .

Further, the first substrate 8 , the second substrate 10 and the third substrate 1 are all silicon substrates. In the step S6 , the channels of the source and the drain are arranged at the upper end of the cavity 6 .

Further, the method also includes:

P-type GaN7 is epitaxially formed on the AlGaN layer 5, and a gate is formed on the p-type GaN7.

Further, the method also includes:

An enhancement silicon MOSFET device is connected on the AlGaN layer 5 .

The above specific embodiment is a detailed description of the present invention, and it cannot be determined that the specific embodiment of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field of the present invention, they can also Making some simple deduction and substitution should be regarded as belonging to the protection scope of the present invention.

Claims (6)

1. A GaN HEMT power device, characterized in that it includes a third substrate (1), a second intermediate layer (2), a buffer layer (3), a GaN layer (4) and an AlGaN layer sequentially connected from bottom to top (5); the AlGaN layer (5) is provided with a source, a drain and a gate, wherein both the source and the drain are extended and connected to the GaN layer (4); the GaN layer ( 4) is provided with a cavity (6), the lower end of the cavity (6) extends into the buffer layer (3), and the upper end of the cavity (6) is located below the channels of the source and the drain ; The preparation method of the GaN HEMT power device comprises the following steps: S1. Epitaxially epitaxially buffer layer (3), GaN layer (4) and AlGaN layer (5) on the first substrate (8); S2. Spin coating or depositing a first intermediate layer (9) on the AlGaN layer (5), and bonding a second substrate (10) on the first intermediate layer (9); S3. Grinding and selective etching to remove the first substrate (8) leaking the buffer layer (3), spin-coating a photoresist on the buffer layer (3) and opening a window; S4, sequentially etching the buffer layer (3) and the GaN layer (4) to form an etching groove, wherein the etching groove extends to the inside of the GaN layer (4) and then stops etching and removes the photoresist; S5. Bonding the third substrate (1) on which the second intermediate layer (2) is spin-coated or deposited on the buffer layer (3), and allowing the second intermediate layer (2) to cover the engraved Etching grooves to form cavities (6); S6, removing the first intermediate layer (9) and the second substrate (10), and manufacturing a source, a drain, and a gate on the AlGaN layer (5), to obtain a GaN HEMT power device. 2. A GaN HEMT power device according to claim 1, characterized in that the thickness of the GaN layer (4) above the cavity (6) is 0.2 um-1 um. 3. A GaN HEMT power device according to claim 1, characterized in that the third substrate (1) is a silicon substrate or an SOI wafer. 4. A GaN HEMT power device according to claim 1, characterized in that p-type GaN (7) is epitaxially formed on the AlGaN layer (5), and the gate is located on the p-type GaN (7) superior. 5. A GaN HEMT power device according to claim 1, characterized in that an enhancement mode silicon MOSFET device is connected to the AlGaN layer (5). 6. A GaN HEMT power device according to claim 1, characterized in that the first substrate (8), the second substrate (10) and the third substrate (1) are all silicon substrates .

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