KR940003096A - High electron mobility transistor and manufacturing method - Google Patents

Abstract

The present invention relates to an improved high electron mobility transistor capable of operating at high speed and a method of manufacturing the same.

The present invention forms a GaAs layer which is not doped with impurities having a triangular void by using crystal growth characteristics according to the crystal direction on a semi-insulating semiconductor substrate on which a dielectric is formed, and selenium (Se) A doped A1 _x Ca _1-x AS layer.

With the above configuration, the present invention allows the current channel and the semiconductor substrate to be electrically separated by the triangular voids, thereby preventing leakage current and backgate effects, reducing the effective gate length, and preventing the DX center. A high speed high electron mobility transistor can be realized.

Description

High electron mobility transistor and manufacturing method

Since this is an open matter, no full text was included.

3A to 3D are manufacturing process diagrams of FIG.

Claims (19)

A semi-insulating compound semiconductor substrate, an insulating film formed in a stripe shape with a predetermined angle with a crystal direction on the semiconductor substrate 110, a first semiconductor layer having triangular voids formed on the insulating film formed therein, A second semiconductor layer formed on the first semiconductor layer, a gate electrode formed on the second semiconductor layer, a third semiconductor layer formed on the second semiconductor layer with the gate electrode interposed therebetween, and a source formed on the third semiconductor layer And a high electron mobility transistor comprising a drain electrode. The high electron mobility transistor of claim 1, wherein the semiconductor substrate is formed of any one of GaAs, InP, or GaP. The high electron mobility transistor of claim 1, wherein the semiconductor substrate is formed of any one of (100), (010), and (001). The high electron mobility transistor of claim 1, wherein the insulating layer is formed to be tilted at an angle of about 20 ° to about 30 ° with a crystal direction of (110). The high electron mobility transistor of claim 1, wherein the insulating layer is formed of one of SiO ₂ or Si ₃ N ₄ . The high electron mobility transistor of claim 1, wherein the first semiconductor layer serves as an electron channel layer, and the second semiconductor layer serves as an electron supply layer. 2. The high electron mobility transistor of claim 1, wherein the first semiconductor layer is a GaAs layer that is not doped with impurities, and the second semiconductor layer is an Al _x Ga _1-x AS layer doped with selenium (Se). 8. The high electron mobility transistor of claim 7, wherein an X value in the selenium-doped A1 _x Ga _1-x AS layer is 0.2 to 0.3. 8. The high electron mobility transistor of claim 7, wherein the doping concentration of selenium in the selenium _- doped Al _x Ga _1-x AS layer is 1x10 ¹⁸ to 3x10 ¹⁸ cm ^-3 . 2. The high electron mobility transistor of claim 1, wherein a current channel is formed on an upper point of the triangular void, and an effective length of the current channel is independent of a length of a gate. A first step of forming an insulating film on the semi-insulating compound semiconductor substrate 110 to be tilted at a predetermined angle with a crystal direction; and selectively epitaxially performing the epitaxial coating on the semiconductor substrate using the insulating film as a mask to include triangular voids therein; A second step of forming a first semiconductor layer having a flat top surface, a third step of forming a second semiconductor layer on the first semiconductor layer, and a fourth step of forming a third semiconductor layer on the second semiconductor layer; And etching the third semiconductor layer to expose the second semiconductor layer on a position corresponding to the void, and source and drain electrodes on the third semiconductor layer not removed by a normal lift-off process. And a seventh step of forming a gate electrode on the second semiconductor exposed by the fifth step. 12. The method of claim 11, wherein the semiconductor substrate is any one of GaAs, InP, or GaP. 12. The method of claim 11, wherein the semiconductor substrate has any one of (100), (010) and (001) crystal planes. The method of manufacturing a high electron mobility transistor according to claim 11, wherein the insulating film is formed to be tilted at an angle of 20 to 30 degrees with a crystal direction (110). The method of claim 1, wherein the insulating layer is formed of any one of SiO ₂ or Si ₃ N ₄ . The method of manufacturing a high electron mobility transistor according to claim 1, wherein the formation of the first semiconductor layer is achieved by forming a GaAs layer which is not doped with impurities by a selective MOCVD method. 2. The method of claim 1, wherein the formation of the second semiconductor layer is achieved by forming an A1 _x Ga _1-x AS layer doped with selenium (Se) by either MBE or MOCVD. Manufacturing method. 18. The method of claim 17, wherein the X value in the selenium-doped Al _x Ga _lx AS layer is 0.2 to 0.3. ^18. The method of claim 17, wherein the doping concentration of selenium in the selenium _- doped Al _x Ga _1-x AS layer is 1 × 10 ¹⁸ to 3 × 10 ¹⁸ cm ^-3 . . ※ Note: The disclosure is based on the initial application.