CN114937645A - Chip package structure - Google Patents

Abstract

The invention provides a chip packaging structure, which relates to the technical field of electronic packaging. It includes a substrate and at least one chip arranged thereon. The surface of the substrate is provided with a solder resist layer. The non-functional surface of the chip, the functional surface of the chip is flip-mounted on the substrate, and is electrically connected to the substrate through an electrical connection structure, the chip and the substrate are filled with an underfill, and the surface of the solder resist layer is provided with at least one groove, and the bottom is The filler is filled in the groove, and the groove includes at least the orthographic projection area of one vertex of the functional surface of the chip on the solder resist layer. The bottom filler in the groove is thicker than the bottom filler in other areas, which plays the role of transition of thermal stress transfer and buffering of thermal stress, making the stress streamline more gentle, effectively dispersing thermal stress, and thicker bottom. The filler can increase the structural strength of the place, reduce the stress concentration factor, thereby reduce the risk of failure at the place, and achieve thermal stress relief from multiple dimensions.

Description

Chip package structure

technical field

The invention relates to the technical field of electronic packaging, in particular to a chip packaging structure.

Background technique

In the chip packaging process, due to the difference in thermal expansion coefficient between the chip and the underfill, the chip package structure has undergone several process steps such as reflow soldering and reliability tests such as temperature cycle testing. Different, there will be a problem of thermal stress concentration at the contact interface. When the thermal stress value exceeds the ultimate strength, the chip will warp and the delamination or cracks will occur between the underfill and the underfill, resulting in the failure of the package structure. Moreover, with the increase of chip size in package structures such as flip-chip ball arrays, the problem becomes more and more serious, especially at the apex of the side of the chip, because the shape of this place is close to a right angle, the stress is more concentrated than other areas, and it is more likely to occur. risk of failure of the above.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a chip packaging structure.

The present invention provides a chip packaging structure, comprising a substrate and at least one chip disposed thereon, a solder resist layer is provided on the surface of the substrate, and the chip has a functional surface provided with an electrical connection structure and a non-functional surface opposite to it. The functional surface of the chip is flip-chip mounted on it facing the substrate, and is electrically connected to the substrate through an electrical connection structure, an underfill is filled between the chip and the substrate, and the surface of the solder resist layer is provided There is at least one groove, the underfill is filled in the groove, and the groove includes at least an orthographic projection area of one vertex of the functional surface of the chip on the solder resist layer.

As a further improvement of the present invention, the surface of the solder resist layer is provided with four grooves, and each of the grooves respectively includes an orthographic projection area of one vertex of the chip on the solder resist layer.

As a further improvement of the present invention, a curved surface structure is formed at the top of the functional surface of the chip, the functional surface of the chip transitions to the side surface of the chip along the curved structure, the underfill covers the curved structure, and the The groove includes at least an orthographic projection area of the curved structure area on the solder resist layer.

As a further improvement of the present invention, an S-shaped curved surface structure is formed at the top of the functional surface of the chip, and the S-shaped curved surface structure includes a first curved surface structure protruding outward along the chip surface and an inward concave structure along the chip surface The second curved surface structure of the chip, the functional surface of the chip transitions to the side surface of the chip along the first curved surface structure and the second curved surface structure in sequence.

As a further improvement of the present invention, along the longitudinal section direction of the package structure, the length of the curved surface structure in the orthographic projection area of the solder resist layer is L, and the outer end of the groove at least exceeds the curved surface structure in the solder resist layer. The outer end L/2 of the layer orthographic projection area.

As a further improvement of the present invention, along the longitudinal section direction of the package structure, the length of the curved surface structure in the orthographic projection area of the solder resist layer is L, and the inner end of the groove at least exceeds the curved surface structure in the solder resist layer. The inner end L/2 of the orthographic projection area of the layer.

As a further improvement of the present invention, the depth of the groove is 50% of the thickness of the solder resist layer.

As a further improvement of the present invention, the inner wall surface and the outer wall surface of the groove are arc-shaped curved surfaces.

As a further improvement of the present invention, the inner wall surface and the outer wall surface of the groove form a combination of multiple vertical surfaces extending along the outer contour of the curved structure.

As a further improvement of the present invention, rounded chamfers are formed at the four vertices of the bottom surface of the groove.

The beneficial effects of the present invention are: the present invention provides a groove on the surface of the solder resist layer, and makes the groove include the orthographic projection area of the chip vertex on the solder resist layer, so that the underfill at this location is compared to The underfill in other areas is thicker, which plays a role in the transition of thermal stress transfer and buffering of thermal stress, making the stress streamline more gentle, effectively dispersing thermal stress, and thicker underfill can increase the structural strength of the place, The stress concentration factor is reduced, thereby reducing the risk of failure at this location, and realizing the effect of thermal stress mitigation from multiple dimensions. In addition, in the present invention, the top area of the chip is further provided with a curved surface structure, and the uniform and excessive interface can make the transfer of stress more continuous and uniform, thereby avoiding the occurrence of an obvious thermal stress concentration area.

Description of drawings

FIG. 1 is a schematic diagram of a chip package structure in Embodiment 1 of the present invention.

FIG. 2 is a schematic diagram of a chip package structure in Embodiment 2 of the present invention.

3 is a top view of the chip packaging structure in Embodiment 2 of the present invention (the inner wall of the groove is in an arc shape, and some structures are omitted for ease of understanding).

4 is a top view of the chip packaging structure in Embodiment 2 of the present invention (the inner wall of the groove is polygonal, and some structures are omitted for ease of understanding).

FIG. 5 is a schematic diagram of a chip package structure in Embodiment 3 of the present invention.

FIG. 6 is a schematic diagram of a chip package structure in Embodiment 4 of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be clearly and completely described below in conjunction with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, only used to explain the present invention, and should not be construed as a limitation of the present invention.

For the convenience of description, the term used to describe the relative position in space, such as "upper", "lower", "rear", "front", etc., is used to describe one unit or feature shown in the drawings relative to another A unit or feature relationship. The term spatially relative position may include different orientations of the device in use or operation other than the orientation shown in the figures. For example, if the device in the figures is turned over, elements described as "below" or "above" other elements or features would then be oriented "below" or "above" the other elements or features. Thus, the exemplary term "below" can encompass both a spatial orientation of below and above.

Example 1

As shown in FIG. 1 , Embodiment 1 of the present invention provides a chip package structure, which includes a substrate 1 and at least one chip 2 disposed thereon.

The substrate 1 is provided with a circuit layer, the surface of the substrate 1 is provided with a solder resist layer 11 and a pad, the pad and the circuit layer are electrically connected, and the solder resist layer 11 is coated on the substrate 1 except for the pad area. A layer of solder resist can play the role of preventing solder spillage and protecting the substrate 1.

The chip 2 has a functional surface 2a provided with an electrical connection structure and a non-functional surface 2b opposite to it. The functional surface 2a of the chip is flip-mounted on the substrate 1, and the chip 2 is welded to the surface pads of the substrate 1 through the electrical connection structure. , so as to be electrically connected to the circuit layer. Specifically, in Embodiment 1, the electrical connection structure of the functional surface 2 a of the chip is a solder ball disposed on the surface of the chip 2 . In other embodiments of the present invention, the chip 2 may also have other structures or be electrically connected to the substrate 1 by other means, which is not specifically limited in the present invention.

The underfill 3 is filled between the chip 2 and the substrate 1, and the underfill 3 is filled in the gap between the substrate 1 and the chip 2. Usually, epoxy resin with additives is used as the matrix material. 2 and substrate 1 for the protection of the connection solder joints, protecting the device from moisture, ionic contaminants, radiation and harmful operating environments such as mechanical stretching, shearing, twisting, vibration, etc., and the underfill 3 also The mismatch of thermal expansion coefficients between the chip 2 and the substrate 1 can be reduced, and the reliability of the package structure can be improved.

In a conventional package structure, the underfill 3 usually completely fills the gap between the substrate 1 and the chip 2, and extends upward along the side of the chip 2, partially covering the side area of the chip 2, and at least completely covering the functional surface of the chip. The four vertex regions of 2a.

Further, at least one groove 111 is provided on the surface of the solder resist layer 11 , the bottom filler 3 is filled in the groove 111 , and the groove 111 at least includes the orthographic projection area of a vertex of the chip functional surface 2 a on the solder resist layer 11 . , that is, the orthographic projection of the vertex of the chip functional surface 2 a on the solder resist layer 11 is completely located in the groove 111 .

The shape of the side vertex of chip 2 is close to a right-angle structure, and the area where the structural cross section changes abruptly will have serious stress concentration. The thermal expansion coefficient difference between 3, the thermal stress value of the side vertex of the chip 2 and the underfill 3 in contact with it gradually increases. When the ultimate strength is exceeded, the chip 2 will warp and the underfill 3 Delamination or crack initiation occurs between them, resulting in the failure of the package structure. In addition, during long-term use, fatigue failure may also occur, which reduces the reliability of the package structure.

In the present invention, by opening the groove 111 on the solder resist layer 11 below the vertex of the functional surface 2a of the chip, the underfill 3 there is thicker than the underfill 3 in other areas, and the groove 111 will make the vertex of the underfill 3 thicker. The area is included, which plays a role in the transition of thermal stress transfer and buffering of thermal stress, making the stress streamline more gentle and effectively dispersing thermal stress, thereby reducing the thermal stress concentration and reducing the maximum stress peak. In addition, the thicker underfill 3 can increase the structural strength of the place, reduce the stress concentration factor, thereby reducing the risk of failure at the place, and realize the effect of alleviating thermal stress from multiple dimensions.

Preferably, in Embodiment 1, the depth of the groove 111 is 50% of the thickness of the solder resist layer 11 . In order to alleviate the thermal stress concentration, on the other hand, the risk of failure of the solder resist layer 11 due to too thinness can be avoided. In other embodiments of the present invention, the depth of the groove 111 can be adjusted according to different thicknesses of the solder resist layer 11 to ensure that the solder resist layer 11 does not fail. specific restrictions.

Specifically, in Embodiment 1, the surface of the solder resist layer 11 is provided with four grooves 111, and each groove 111 includes the orthographic projection area of one vertex of the chip 2 on the solder resist layer 11, so that the chip 2. All four vertices can play a role in relieving thermal stress concentration, so that the overall force of the chip 2 and the underfill 3 is more uniform, and the reliability of the chip packaging structure is increased.

Preferably, the plane shape of the groove 111 can be a shape composed of curves such as a circle or an ellipse, so as to avoid sharp edges and corners, and the uniform transition interface makes the force transmission more continuous and uniform, thereby further reducing the thermal stress concentration. .

In this embodiment, only one chip 2 is used for description. In the actual package structure, multiple chips or other passive devices may be provided on the substrate 1. When multiple chips 2 are provided, the functional surface of each chip may be The groove 111 is provided in the area of the solder resist layer 11 corresponding to the vertex of 2a, or the groove 111 can be provided in the area of the solder resist layer 11 corresponding to some vertexes of some chips 2 according to parameters such as the size or type of the specific chip 2. No specific restrictions are imposed.

Example 2

As shown in FIG. 2, Embodiment 2 of the present invention provides a chip packaging structure, the structure of which is generally similar to that of Embodiment 1, and the difference from Embodiment 1 is:

A curved surface structure 2a1 is formed at the top of the chip functional surface 2a. The chip functional surface 2a transitions to the side of the chip 2 along the curved surface structure 2a1. The underfill 3 covers the curved surface structure 2a1. The orthographic projection area is included.

It should be noted that the position at the top of the chip functional surface 2a is used for the convenience of explanation. In the actual structure, since the curved surface structure 2a1 is formed there, there is no exact topmost position. Refers to the entire surface area.

In Embodiment 2, the top area of the chip 2 is formed into a curved structure 2a1, so as to avoid forming a sharp edge structure at the bonding surface of the chip 2 and the underfill 3. As mentioned above, a uniform and excessive interface can make the stress transfer more efficient. Continuous and uniform, thus avoiding significant areas of thermal stress concentration.

Specifically, in Embodiment 2, the curved surface structure 2a1 is an arc-shaped surface that protrudes outward along the surface of the chip 2, and can form an elliptical arc-shaped surface, so as to play a better transition role.

By forming the groove 111 in the solder resist layer 11 and forming the curved surface structure 2a1 at the top of the chip functional surface 2a, the combined effect of reducing thermal stress concentration can be achieved, thereby significantly improving the reliability of the chip packaging structure.

Preferably, in Embodiment 2, along the longitudinal section direction of the package structure, the length of the curved surface structure 2a1 in the orthographic projection area of the solder resist layer 11 is L, and the outer end of the groove 111 at least exceeds the curved surface structure 2a1 outside the orthographic projection area of the solder resist layer 11 and the inner end of the groove 111 at least exceeds the inner end L/2 of the orthographic projection area of the solder resist layer 11 beyond the curved surface structure 2a1. That is, along the longitudinal section direction of the package structure, when the length of the curved surface structure 2a1 in the orthographic projection area of the solder resist layer 11 is L, the width of the groove 111 is at least 2L. Here, by defining the width of the groove 111 based on the width of the outer contour of the curved structure 2a1, it is ensured that the two ends of the groove 111 are separated from the curved structure 2a1 by a sufficient distance to avoid the occurrence of the bonding surface between the chip 2 and the underfill 3 The situation where the area with the strongest stress overlaps with the area with the strongest stress at the joint surface of the solder mask layer 11 and the underfill 3 will lead to stress concentration and separation or fracture of the interface of the package structure.

It can be understood that since the projected widths of the different regions of the curved structure 2a1 on the solder mask layer 11 are different, that is, in terms of plane, the minimum width of the groove 111 is also dynamically changed. In order to facilitate the implementation of the slotting process, you can choose The maximum value among the different minimum widths is taken as the minimum width of the groove 111 as a whole.

In other embodiments of the present invention, the width of each groove and the projection of the groove 111 beyond the curved structure 2a1 on the solder resist layer 11 can also be determined according to the dimensional characteristics of the chip 2 and the radian of the curved structure 2a1. The length of the region is specifically adjusted, and the present invention only provides a preferred solution, and there is no specific limitation on this.

Specifically, as shown in FIG. 3 , in this embodiment, the inner wall surface and the outer wall surface of the groove 111 are arc-shaped curved surfaces, including the curved surface structure 2a1 .

As shown in FIG. 4 , in other embodiments, the inner and outer walls of the groove 111 form a combination of multiple vertical surfaces extending along the outer contour of the curved structure 2a1 , and the overall planar shape forms a polygon similar to “c”. In the production process, the groove 111 structure formed by the combination of the vertical planes is easier to realize by a process such as laser cutting.

Example 3

As shown in FIG. 5 , Embodiment 3 of the present invention provides a chip packaging structure, the structure of which is generally similar to that of Embodiment 1, and the difference from Embodiment 1 is:

An S-shaped curved surface structure 2a1 is formed at the top of the chip functional surface 2a. The S-shaped curved surface structure 2a1 includes a first curved surface structure protruding outward along the surface of the chip 2 and a second curved surface structure recessed inward along the surface of the chip 2. The chip functional surface 2a Transition to the side of the chip 2 along the first curved structure and the second curved structure in sequence.

Compared with the completely arc-shaped curved surface structure 2a1, the S-shaped curved surface structure 2a1 is easier to realize through a process such as laser cutting during the production process.

Example 4

As shown in FIG. 6 , Embodiment 4 of the present invention provides a chip packaging structure, the structure of which is generally similar to that of Embodiment 3, and the difference from Embodiment 1 is:

Rounded chamfers are formed at the four vertices of the bottom surface of the groove 111. As mentioned above, by forming a smooth transition rounded chamfered on the bottom surface of the groove 111, the transmission of stress can be more continuous and uniform, thereby further reducing the heat there. Stress buildup.

In summary, the present invention provides a groove on the surface of the solder resist layer, and makes the groove include the orthographic projection area of the chip vertex on the solder resist layer, so that the underfill at this place is compared with other areas. The bottom filler is thicker, which plays the role of transition of thermal stress transfer and buffering of thermal stress, making the stress streamline more gentle and effectively dispersing thermal stress. And thicker underfill can increase the structural strength of the place, reduce the stress concentration factor, thereby reduce the risk of failure at the place, and achieve thermal stress relief from multiple dimensions. In addition, the top area of the chip is further provided with a curved surface structure, and the uniform and excessive interface can make the transfer of stress more continuous and uniform, thereby avoiding the occurrence of an obvious thermal stress concentration area.

It should be understood that although this specification is described in terms of embodiments, not every embodiment only includes an independent technical solution, and this description in the specification is only for the sake of clarity, and those skilled in the art should take the specification as a whole, and each The technical solutions in the embodiments can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

The series of detailed descriptions listed above are only specific descriptions for the feasible embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any equivalent embodiments or changes made without departing from the technical spirit of the present invention All should be included within the protection scope of the present invention.

Claims (10)

1. A chip packaging structure comprises a substrate and at least one chip arranged on the substrate, wherein the surface of the substrate is provided with a solder mask layer, the chip is provided with a functional surface provided with an electric connection structure and a non-functional surface opposite to the functional surface, the functional surface of the chip is arranged on the substrate in an inverted way and is electrically connected with the substrate through the electric connection structure, and a bottom filler is filled between the chip and the substrate,

at least one groove is arranged on the surface of the solder resist layer, the underfill is filled in the groove,

the groove at least includes an orthographic projection area of one vertex of the chip functional surface on the solder mask layer.

2. The chip packaging structure according to claim 1, wherein the solder resist layer is provided with four grooves, and each groove includes an orthographic projection area of a vertex of the chip on the solder resist layer.

3. The chip package structure according to claim 2, wherein a curved surface structure is formed at a top end of the chip functional surface, the chip functional surface transitions to the chip side surface along the curved surface structure, the underfill covers the curved surface structure, and the groove at least includes an orthographic projection area of the curved surface structure area on the solder resist layer.

4. The chip package structure according to claim 3, wherein an S-shaped curved surface structure is formed at a top end of the chip functional surface, the S-shaped curved surface structure includes a first curved surface structure protruding outward along the chip surface and a second curved surface structure recessed inward along the chip surface, and the chip functional surface transitions to the chip side surface along the first curved surface structure and the second curved surface structure in sequence.

5. The chip packaging structure according to claim 3, wherein along a longitudinal cross section of the packaging structure, the length of the curved surface structure in an orthographic projection area of the solder mask layer is L, and the outer end of the groove at least exceeds the outer end of the curved surface structure in the orthographic projection area of the solder mask layer by L/2.

6. The chip package structure according to claim 5, wherein along a longitudinal cross section of the package structure, a length of the curved surface structure in an orthographic projection area of the solder mask layer is L, and an inner end of the groove at least exceeds an inner end L/2 of the curved surface structure in the orthographic projection area of the solder mask layer.

7. The chip package structure according to claim 1, wherein the groove depth is 50% of the solder resist layer thickness.

8. The chip package structure according to claim 5, wherein the inner wall surface and the outer wall surface of the groove are curved surfaces in the shape of circular arcs.

9. The chip package structure according to claim 5, wherein the inner wall surface and the outer wall surface of the groove are a combination of multiple vertical surfaces extending along the outer contour of the curved surface structure.

10. The chip package structure according to claim 5, wherein the four vertices of the bottom surface of the groove form a rounded chamfer.

Images