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CN1147928C - 具有亚芯片规模封装构造的半导体器件制造方法 - Google Patents

具有亚芯片规模封装构造的半导体器件制造方法

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CN1147928C
CN1147928C CNB981228127A CN98122812A CN1147928C CN 1147928 C CN1147928 C CN 1147928C CN B981228127 A CNB981228127 A CN B981228127A CN 98122812 A CN98122812 A CN 98122812A CN 1147928 C CN1147928 C CN 1147928C
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substrate
semiconductor
peripheral dimension
die
semiconductor die
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CN1219763A (zh
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������¡�M�����
里奥·M·海金斯三世
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NXP USA Inc
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Motorola Inc
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Abstract

一种半导体器件的形成方法，其特征是具有下述步骤：提供具有多个半导体管芯的晶片，多个半导体管芯的每一半导体管芯都具有一个表面和外围尺寸X及外围尺寸Y，每一半导体管芯的外围尺寸X和外围尺寸Y彼此互相垂直；在所述每一半导体管芯的表面上形成多个电接触；把多个基板覆盖到多个半导体管芯上，使得多个基板的每一基板都电连到多个半导体管芯的各自半导体管芯的多个电接触上，其中，所述每一基板都具有彼此互相垂直的外围尺寸X′和外围尺寸Y′，且至少下述两者之一得到满足：(i)所述每一基板的外围尺寸X′小于所述各自半导体管芯的外围尺寸X，(ii)所述每一基板的外围尺寸Y′小于所述各自半导体管芯的外围尺寸Y；以及在覆盖多个基板后将多个半导体管芯切割成单个管芯。根据本发明的方法允许在晶片级别即在切割成半导体管芯之前进行半导体管芯封装。

Description

具有亚芯片规模封装构造的半导体器件制造方法
技术领域
本发明涉及封装后的半导体器件和半导体器件的封装方法，特别是涉及芯片规模式封装。
背景技术
芯片规模封装(CSP)是当前令人感兴趣的现代半导体封装。芯片规模封装是一种相对新的封装技术，在该技术中，半导体管芯被键合到诸如塑料或陶瓷之类的基板上，而该基板的尺寸和半导体管芯的尺寸大体上相同或比半导体管芯的尺寸稍大一点。现在把注意力集中到芯片规模封装上主要是为了减小这种封装的占板面积，占板面积的减小使得电子装置的最后装配人员可以采用在给定的空间之内装配最大数目的半导体器件的办法改善该装置的功能。
日本专利特开平9-213838A公开了一种形成封装结构的方法，其中基板比管芯小。该方法通过切单或切割管芯然后封装管芯来进行。
根据目前的工艺水平，芯片规模封装是相对昂贵的并且具有许多主要是由这种封装的相对复杂性引起的可靠性方面的问题。除此之外，芯片规模封装以及任何封装后的半导体器件的可靠性直接比例于管芯的尺寸。随着半导体厂家在一个管芯上实现越来越多的功能，管芯尺寸增加，同时缺少能够减少管芯特征尺寸的技术。随着管芯尺寸的增加在半导体管芯和基板(即，第1级封装互连)之间的布线的可靠性变成为更值得怀疑。此外，随着封装后的半导体器件的尺寸的增加(因而，占板尺寸增加)，在封装后的半导体器件和印制电路板之间的连接(即，第2级封装互连)的可靠性变成为更加令人关心。这样的可靠性问题基本上是由于在半导体管芯材料，基板，和印制电路板之间的热膨胀系数之差引起的，该热膨胀系数之差在环境温度和功率循环变化期间在布线上引起应力。
除减小封装尺寸和保持可靠性不变的问题之外，在晶片级封装，即在被切割成单个管芯(singulated)之前，以晶片的形式对半导体管芯进行封装方面的兴趣也已有所增加。人们认为通过减少必须用自动机构处理的单个元件的个数，晶片级封状可以改善可靠性并可以减少造价。但是，利用现有的封装技术来产生一种可靠地去除在半导体管芯和封装基板之间的热膨胀不匹配应力同时保证BGA(网格焊球阵列)可靠性的低价位方法还没有发展成为可以进行晶片级封装。
发明内容
因此，在目的为应用标准装配设备改善芯片规模封装的工作中存在着的一种要求是造价低，可靠性高，且允许晶片级封状。
根据本发明，提供一种半导体器件的形成方法，其中该半导体器件包括具有表面和外围尺寸X和外围尺寸Y的半导体管芯，半导体管芯的外围尺寸X和外围尺寸Y彼此垂直，并且该半导体器件包括具有彼此垂直的外围尺寸X′和外围尺寸Y′的基板，所述基板的外围尺寸X′小于所述相应的半导体管芯的外围尺寸X，所述基板的外围尺寸Y′小于所述相应的半导体管芯的外围尺寸Y，其中所述方法的特征是具有下述步骤：提供具有多个半导体管芯的晶片；把多个基板覆盖到多个半导体管芯上，使得多个基板的每一基板都电连到多个半导体管芯的各自半导体管芯的多个电接触上；以及在覆盖多个基板后将多个半导体管芯切割成单个管芯。
附图说明
参考下边的附图阅读下述详细说明，可以得到对本发明的更好了解。
图1和图2示出了本发明的实施例，其中管芯已经被连接到基板上，而且已经用一个下部填充密封层(underfill encapsulation layer)进行了下部填充。
图3以平面视图的形式示出了本发明的一个实施例，其中，在晶片级规模上多个管芯被同时封装。
图4，图5和图6示出了本发明的另外的实施例，它们描绘出半导体管芯/基板尺寸的相对差别。
应当指出，为了图面的简单和清楚起见，图中所画出的组成部分并未按比例画出。例如，为了清楚起见，某些组成部分的尺寸相对于其它组成部分被夸大了。还有，那些经过恰如其分地考虑的地方，在这些图中已经被多次重复以指明相应的或类似的组成部分。
具体实施方式
如图1所示，提供一个半导体管芯10，该管芯包括有源部分11和在有源部分11上边的层间电介质(ILD)层12，该层间电介质层12已被图形化为提供电路接触焊盘14的形状，并被安排为靠近管芯外周30。注意，就象专业人员所熟知的那样，有源部分11包括一个硅衬底，在硅衬底上边形成确定有源表面11a的有源器件，有源器件11a用更高一级的金属层(没画出来)进行布线。就象专业人员所熟知的那样，更高一级的金属层理想的是例如M1(金属层1)到M6(金属层6)。有源部分11的细节，一个普通的专业人员都会知道，而且，对于完全了解本发明并非特别重要。重新分布接触线16被连接到电路接触焊盘14上，以便确定向着半导体管芯中心方向向内进行电连。如图所示，重新分布接触线16在下部突出电极金属化(UBM)焊盘15上端接。之后，淀积一层钝化层18并图形化为在UBM焊盘15上留下一个窗口，分别在UBM焊盘15上形成焊锡突出电极20。
倘采用上述半导体管芯10，则焊锡突出电极20被电连到半导体管芯10的有源表面上。就象专业人员所熟知的那样，示于图1的半导体管芯10被看作是’突出电极式’的管芯。该突出电极式管芯，使有源表面面朝下(如图所示)进行倒装以便接着键合到基板上。焊锡突出电极可以采用已知的控制熔塌电路连接(C4)技术形成，或者用可供选择的突出电极成型技术(即模板印制或应用焊锡喷射)形成。此外，沿着管芯外周30描画出一条划片线102，这条划片线在后边用图3将会更详细地说明。ILD层12可以用任何合适的电介质材料，诸如二氧化硅、氮化硅、氮氧化硅，聚酰亚胺等形成。钝化膜18被形成为保护有源表面，而且可以采用包括磷硅玻璃、氮化硅、聚酰亚胺层等的混合物构造。还有，为了参照图1中所用的说明用的术语，与UBM焊盘15组合到一起的焊锡突出电极20通常一块被看作是形成在半导体管芯的表面上的电接触是理想的。很清楚，这样的电接触可以用另一种形式实施。例如，焊锡突出电极20可以用例如金丝大头钉焊球和无电镍/金电镀焊球，或者导电聚合物焊球代替。该电接触还可以作为非突出电极式金属焊盘来实施，该金属焊盘与包括一个诸如镍粉或镀金聚合物珠的导电性成分的聚合物形成多层，所述导电性成分分散在热固性或热塑性薄膜或浆料中。就象专业人员所熟知的那样，在半导体管芯和基板之间加压形成电连接，使得在非突出电极式金属接触焊盘和衬底上边成对的接触线(例如，直接管芯连接(DCA)键合焊盘)之间留下一薄层导电性成分的办法执行。这种类型的聚合物材料一般地说理想的是用做一种各向异性导电性粘接剂。这种粘接剂也可以与上述金丝大头钉焊球，无电镍/金电镀焊球，和类似的构造一起使用。
关于图1和图2的基板50，图中示出了一种构造，该构造具备一个理想地说形成于有机聚合物上边的绝缘层51。但是，绝缘层51也可以就象专业人员所熟知的那样用绝缘陶瓷材料以及用具有已在相向表面上形成的绝缘膜和遍布各处的贯通孔的金属层形成。根据本发明的一个实施例，形成绝缘层51的有机聚合物可以由聚酰亚胺柔软电路或用环氧树脂叠层板增强的玻璃纤维构成。诸如芳族聚酰胺纤维之类的有机增强也可以用来代替玻璃纤维成分。如图1所示，在绝缘层51的第1表面(即，顶部表面)上边形成多个直接管芯连接(DCA)键合焊盘52。它们分别与半导体管芯10的焊锡突出电极20排列成行。焊锡掩模53用来在回流焊工序期间防止不希望的由焊锡突出电极构成的焊锡材料流以便在基板50和半导体管芯10之间形成连接。众所周知，在基板的第2个表面即底面上边，形成以通孔54或电镀贯通孔的形式把DCA键合焊盘连接到网格焊球阵列(BGA)键合焊盘56上的多条电连布线。在BGA键合焊盘56上边形成第2个焊锡突出电极57，在它上边用焊锡材料形成网格焊球阵列(BGA)焊球58。参考标号60示出了基板的一个外周表面。就象今后所使用的那样，术语’基板’被看成是机械组成部分，它承载半导体管芯，而且它还具有(即支持)通过诸如印制电路板提供从半导体管芯到下一级布线的电连的电连元件(在这里是元件52，54，56和58)。
下面转向图2，一个完整的封装后的半导体器件示于图2，其中，基板50连接到半导体管芯10上。基板50被放置到半导体管芯10上。下部填充密封层包括一个内圆角(fillet)72，该内圆角72束缚住在基板近旁露出来的半导体管芯的有源表面和基板外周表面60。内圆角因下部填充密封层70的材料的变湿作用沿着基板的外周表面60形成。电连是借助于下部填充密封层70的形成同时形成的，或者也可以在下部填充密封层70的形成之前，用诸如回流法形成。下部填充密封层的材料通常由球形熔化二氧化硅粒子填充式环氧树脂构成，该环氧树脂是用常规的技术(即加热技术)进行固化处理的。下部填充密封层70可以用任何一种已知的技术淀积，例如采用在管芯的最后一个边沿的周围淀积该材料并借助于被推进到半导体管芯10和极板50之间的界面中的材料的毛细作用进行淀积的办法进行淀积。
还有，所有的多个电接触(即焊锡突出电极20，UBM和焊盘15)都位于基板50的外周之内。本发明的这一特有的特点在使所有的从外部环境到封装后的半导体器件的电连方面是有利的。此外，本发明还允许在半导体管芯和基板之间在CSP内进行阵列键合而不是在外表面进行键合。再有，本发明的阵列键合允许在半导体管芯和基板之间，在应用外表面键合技术的已知CSP的整个范围内有相对大的尺寸差别。在这样的已知CSP中，基板的尺寸的减小将会在管芯和基板之间形成非常长的键合引线。这种长的键合引线缺乏在现在的外表面键合式CSP中使用的相对短的键合引线的热稳定性，可能更容易地产生危险。
虽然在示于图1和图2的实施例中BGA球58在附加到半导体管芯10上之前就被提供到基板50上，人们很清楚，BGA球58也可以在附加到半导体管芯10上之后以理想的晶片形式或在被切割成管芯之后再附加到基板50上。根据示于图1和图2的实施例，在基板50和半导体管芯10之间利用焊锡突出电极20形成电连，接着用下部填充密封材料进行下部填充密封。下部填充密封可以在形成电连的同一时间形成。在本实施例中，形成下部填充密封层70的材料首先被淀积到半导体管芯上，然后把基板放置到其上边。在接下来的工艺中，完成在突出电极20和DCA键合焊盘52(例如采用回流法)之间的电连，和附加下部填充密封层70(例如采用硬化处理技术)。回流和硬化可以同时进行。
下面转到图3，图3示出了以晶片的形式封装多个半导体管芯的平面图。如图所示，同时封装进了多个半导体管芯(在本实施例中是16个)。基板的尺寸X′和Y′以及半导体管芯的尺寸X和Y彼此垂直。在这里，示出的下述两者皆得到满足：(i)基板的X′尺寸小于半导体管芯X的尺寸，(ii)基板的Y′尺寸小于半导体管芯Y的尺寸。但是，应当说明的是，根据本发明，一个或另一个X′和Y′尺寸可以作成为小于相应的半导体管芯的X和Y尺寸。在本实施例中，在沿着切割线102进行管芯切割期间，伸出到管芯10的边沿之外的基板边沿，将以与基板的边沿对准的形式同时切掉管芯的边沿。但是，理想的是使基板尺寸X′和Y′都小于半导体管芯的尺寸X和Y。
如图3所示，半导体晶片100具有使单个管芯彼此分开的切割线102。如图1和图2中用虚线所示，沿着切割线的材料基本上已被去掉。
图4，5和6示出了本发明的另一实施例，该实施例和上边用图1-3所说明的实施例有些相似，半导体管芯10是10mm平方，厚度为0.4mm，并有100个电接触。基板的厚度为0.5mm。虽然图4-6示出了一个本质上相同的半导体管芯10，但是却示出了3个不同的重新分布图。
首先，在图4中，示出了一种大胆的重新分布图，其中，81个BGA球58被配置到5mm见方的基板上，步距为0.5mm。图5示出了配置到7.5mm见方的基板上的120个BGA球58，步距为0.65mm。最后，在图6中示出了配置到9.5mm见方的基板上的144个BGA球58，步距为0.80mm。根据图4，图中示出了相对大胆的重新分布图，从减小基板50的占板面积的观点来看是有好处的。基板50的占板面积的减小将会改善基板50和要装配基板50的印制电路板之间的布线的可靠性。如图所示，在基板周围伸出到基板外边的半导体管芯10的部分对于由BGA球确定的连到电路板上的连线(没有画出来)上的应力没有什么重要的贡献，该应力是由热膨胀系数不匹配引起的。伸出到极板50的边沿之外的这一管芯部分仅仅是通过示于图3的下部填充密封层70的内圆角72热-机械性地耦合到基板50上的。尽管有这一优点，假设电路接触焊盘形成在半导体管芯10的外周附近，就象与图1-2结合起来示出的实施例那样，就需要一个相对长的重新分布网络，而该网络可能感应出不希望的寄生损耗，而且对于从半导体管芯10到基板50的热传输还可能具有负的冲击。还应当指出，管腿的数目从100个电接触(管芯和基板之间)减少到81个接触。这样一种在电接触数目上的减少是通过在基板中应用公用电源和接地平面，或者平面段(segment)来实现的。
从具有示于图1的大胆的重新分布图的相对设计的紧张状态的观点来看，更高频率和/或更高功率的器件需要示于图5和6的那样的不怎么大胆的重新分布图。如图所示，图5和6在改善电性能和功耗的BGA球的数目上有了增加。应当指出，所有的实施例都与现代技术水平的散热片，例如，那些可以附加到半导体管芯10的钝化表面上的散热片兼容。
就象上边所讨论过的那样，很显然，本发明提供一种改善后的亚芯片规模封装，这种封装满足现代技术水平的几种要求。倘采用本发明，则不仅在管芯和基板之间的布线的可靠性得到改善，在基板和印制电路板之间的布线的可靠性，借助于减小基板的占板面积也得到改善。从这种意义上说，与基板和管芯的尺寸相同的芯片规模封装不一样，本发明提供一种下部填充密封内圆角形式，该下部填充密封内圆角涂敷到伸出到基板边沿之外的管芯的区域上，以代替基板段，在典型的CSP中，下部填充密封内圆角在该区域内盖住管芯。在缓和因基板和管芯之间的热膨胀系数的不匹配而产生的应力方面这种做法表明是有效的。此外，与现有技术水平的芯片规模封装不同，由于其在这里公开的相对简单易做的构造，本发明能够以相对低的成本来制造和完成。再有，本发明还提供一种归因于基板尺寸减小而带来的把基板价格减少到40％～80％的方法。还有，本发明不需要因为制造半导体而增加额外的或更多的设备支出，因为现有的倒装管芯封装设备可以用来形成采用本发明技术的封装后的半导体器件。本发明还能够进行晶片级封装，借助于此，所有的半导体管芯可以同时封装到晶片上。
另外，本发明在封装操作期间还提供具有更高产率的已得到增加的吞吐率。特别是与以前的技术不同，以本发明的实施例为根据的基板，在被切割之前以晶片的形式被放置到半导体管芯上。归因于借助于它在晶片上形成半导体管芯的精度，在晶片上边可以在整个范围内形成高度精确的基准(fiducial)，该基准对于晶片上的管芯本质上具有确切的关系。一个性能合适的图象系统可以检测晶片上的普适的基准，以便仅仅用该基准就可以把每一片基板放置到垂直的管芯上边。与此相对，根据现有的技术，将提供一个将被切割成多个基板的印制电路板，在该印制电路板上装配切割后的管芯。但是倘采用现有技术，则该印制电路板用精度相对低的普适基准进行制作，该基准不能提供象根据本发明的晶片的普适基准所提供的那样的对准度。这将会减少产品吞吐率，因为观察系统必须定位于管芯和基板上的本地基准上。
应当指出，可以有许多变形而不背离在后边的权利要求中确定的本发明的精神和范围。例如，尽管在图中没有画出来，基板可以以单片或者几个多单元段的形式连接到一起然后盖住整个晶片。接着进行切割以使基板彼此分开。理想的是使用单个基板，因为这样将消除浪费和降低放到预先经过探针测试的晶片上的基板的价格。

Claims (3)

1、一种半导体器件的形成方法，其中该半导体器件包括具有表面和外围尺寸X和外围尺寸Y的半导体管芯，半导体管芯的外围尺寸X和外围尺寸Y彼此垂直，并且该半导体器件包括具有彼此垂直的外围尺寸X′和外围尺寸Y′的基板，所述基板的外围尺寸X′小于所述相应的半导体管芯的外围尺寸X，所述基板的外围尺寸Y′小于所述相应的半导体管芯的外围尺寸Y，其中所述方法的特征是具有下述步骤：
提供具有所述多个半导体管芯的晶片；
在所述每一个半导体管芯的表面上形成多个电接触；
把多个基板覆盖到多个半导体管芯上，使得多个基板的每一基板都电连到多个半导体管芯的各自半导体管芯的多个电接触上；以及
在覆盖多个基板后将多个半导体管芯切割成单个管芯。
2、权利要求1所述的方法，其特征是：所述每一基板都具有一个外周，多个电接触位于所述每一半导体基板的外周之内。
3、权利要求1所述的方法，其特征是：还具有在所述每一基板和所述每一半导体管芯之间淀积下部填充密封层的步骤。
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