CN114650079B - Reverse modulation method for contactless communication and corresponding transponder - Google Patents

Abstract

Embodiments of the present disclosure relate to a reverse modulation method for contactless communication, and a corresponding transponder. A contactless communication method includes reversely modulating a carrier signal received at a terminal of an antenna in alternation between a modulated state and an unmodulated state. The modulated state includes modulating a load at the antenna terminal with zero impedance, and controlling a transition from the modulated state to the unmodulated state at a time determined by a first delay.

Description

Reverse modulation method for contactless communication, and corresponding transponder

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of French application No. 2013523, filed on December 17, 2020, which is incorporated herein by reference.

Technical Field

Implementations and embodiments relate to contactless communication, in particular contactless communication using amplitude inversion modulation of a carrier signal.

Background Art

Contactless communication, such as communication according to a technology called "near field communication" (commonly "NFC") and communication according to a technology called "radio frequency identification" (commonly "RFID"), is a wireless connection technology that allows short-range communication (e.g. 10 cm) between electronic devices, such as between a contactless integrated circuit card or tag and a reader.

NFC technology is an open technology platform, standardized in ISO-14443, EMVCo, NFC Forum standards, but incorporates other existing compatible communication standards. RFID technology is specifically standardized through ISO-18092 standards, and also combines other existing compatible communication standards.

Contactless communication can be achieved between two contactless peer communication devices (in particular devices compatible with NFC technology), such as multifunction phones (commonly called "smartphones"); or between a reader device and a transponder device, such as an NFC or RFID card or tag or a multifunction phone emulated in card mode.

When information is transmitted between the reader and the transponder, the reader generates a magnetic field with its antenna, which is usually a 13.56 MHz sine wave (called the carrier or carrier signal).

To transmit information from a reader to a transponder, the reader uses amplitude modulation of a carrier wave, and the transponder is able to demodulate the received carrier wave to obtain the data transmitted by the reader.

To transmit information from the transponder to the reader, the reader generates a magnetic field (carrier wave) without modulation. The transponder then modulates the field generated by the reader according to the information to be transmitted. The frequency of this modulation corresponds to a subcarrier of said carrier wave. The frequency of this subcarrier wave depends on the communication protocol used and can be equal to 848 kHz, for example.

Modulation is performed by modifying the load connected to the transponder antenna terminals.

Then there are two possible modes of operation, passive mode or active mode.

In active mode of operation, both the reader and the active transponder generate an electromagnetic field. Typically, this operating mode is used when the active transceiver has its own power source, such as a battery.

Specifically, a passive transponder has no power source and uses the energy from the carrier transmission from the reader to power its integrated circuit.

In passive mode, the transponder back-modulates the waves coming from the reader to transmit the information and does not integrate an actual transmitter for transmitting the information, such as a transmitter capable of generating its own magnetic field during transmission.

A passive transponder modifies the impedance connected to its antenna by inductive coupling through a reverse modulation visible on the reader side to transmit the data frame.

During frame transmission, the reverse modulation is defined in an unmodulated state when the reverse modulation load is not connected to the antenna, or in a modulated state when the reverse modulation load is connected to the transponder antenna.

The greater the impedance change generated by the transponder (i.e. the load difference between the modulated and unmodulated states), the greater the impedance seen from the reader side, and therefore the easier it is for the reader to demodulate the data. One of the main performance criteria for a transponder is the load modulation amplitude "LMA". The method of measuring LMA is to measure the difference in the current amplitude in the antenna Lc of the transponder CRD between the modulated and unmodulated states.

One difficulty encountered in contactless transponder design is optimizing the LMA while maintaining a coherent frame, that is to say synchronization with the reader's carrier signal, regardless of the electromagnetic field conditions (particularly the distance between the reader and the transponder).

In conventional contactless transponders, the load modulation is designed so that the carrier signal is available on the transponder antenna both in the modulated and unmodulated states. This allows to keep the clock extraction from the carrier in activity and to clock the transmission on the clock period of the extracted signal as the only time reference, in particular to define the transition instants between the unmodulated and modulated states.

The disadvantage of these conventional solutions is that the impedance at the antenna terminal is prohibited from being zero or too low in principle due to the need to extract the clock signal. Therefore, conventional solutions provide for adjusting the impedance value in the modulation state according to the effective level of the electromagnetic field, which complicates the design of the reverse modulation and limits the load modulation amplitude LMA.

There is a need to increase the load modulation amplitude LMA of contactless transponders, especially passive contactless transponders.

Summary of the invention

According to one aspect, a contactless communication method is provided, the method comprising: reversely modulating a carrier signal received at an antenna terminal while alternating between a modulated state and an unmodulated state. According to the general characteristics of this aspect, the unmodulated state comprises modulation with a non-zero impedance of a load at the antenna terminal, the modulated state comprises modulation with a zero impedance or nearly zero impedance of a load at the antenna terminal, and the transition from the modulated state to the unmodulated state is controlled at a moment determined by a first delay.

"Zero impedance or almost zero impedance" refers to an impedance that is as low as possible given the material constraints that implement it, e.g., a transistor in an on state is considered to have zero impedance or almost zero impedance at its conduction terminal. For example, in particular, "almost zero impedance" refers to an impedance that is at most a few percent (e.g., 2%) of the non-zero impedance value in the unmodulated state.

In other words, delays are used in the modulation state to maintain precise synchronization of frame transmission to provide full zero impedance reverse modulation.Thus, the first delay is used to define the time of the modulation state, since the clock signal cannot be extracted from a modulated carrier signal with zero impedance.

Therefore, the load modulation amplitude LMA is maximized (strictly speaking, the modulation state component of the LMA is optimized), which allows, among other things, an increase in the range of the contactless communication.

According to one implementation, the transition from an unmodulated state to a modulated state is controlled at a moment determined by a duration measured on a clock cycle generated by a clock signal extracted from a carrier signal, the measurement of the duration starting from a moment determined by a second delay, the moment determined by the second delay being after the moment of transition to the unmodulated state.

In other words, the second delay allows avoiding the use of the clock signal extracted when clock extraction is restarted at the beginning of the modulation state, thereby allowing avoiding instability in the extracted clock signal when its generation is restarted.

In particular, this allows the timing of the transitions to be defined very precisely over time and to be adapted to different conditions.

According to one embodiment, the measurement of the second delay and the measurement of the first delay are started at a time coordinated with a modulation control signal, the modulation control signal initiates the control transition to the modulation state, and the second delay is greater than the first delay.

For example, the modulation control signal is at the origin of the modulation state control and can be generally generated by a digital controller. The start of the measurement of the first delay and the second delay is controlled based on the modulation control signal and is offset from each other by, for example, half a clock cycle to ensure robust operation of the system.

The difference between the second delay and the first delay is advantageously designed to be just long enough to ensure that the clock signal extraction has restarted and is stable when the measurement of the clock period starts.

According to one embodiment, a masking signal is generated during the second delay duration, which blocks the extracted clock signal at a constant reference level.

According to one embodiment, the second delay is obtained by the time during which the second capacitive element is loaded with the second reference current.

According to one embodiment, the load modulation at the antenna terminals in the case of a modulation state in which the impedance is zero or almost zero is controlled by a reverse modulation signal generated for a duration determined by the first delay.

According to one embodiment, the first delay is obtained by the time during which the first capacitive element is loaded with the first reference current.

According to another aspect, there is provided a contactless communication transponder, such as a tag, comprising: an antenna intended to receive a carrier signal, and a modulator configured to reversely modulate the carrier signal in alternation between a modulated state and an unmodulated state. According to the general features of this aspect, the modulator comprises a first delay circuit configured to generate a first delay, and the modulator is configured to modulate the load at the antenna terminal to a non-zero impedance in the unmodulated state, modulate the load at the antenna terminal to zero impedance or nearly zero impedance in the modulated state, and control the transition from the modulated state to the unmodulated state at a time determined by the first delay.

According to one embodiment, the transponder also includes a clock extraction circuit configured to generate a clock signal extracted from the carrier signal, and the modulator includes a second delay circuit configured to generate a second delay, and a control circuit configured to measure a duration over a clock cycle from the extracted clock signal from a moment determined by the second delay, the moment determined by the second delay being after a moment of transition to an unmodulated state, and to generate a modulation control signal that controls the transition from the unmodulated state to the modulated state at a moment determined by the measured duration.

According to one embodiment, the first delay circuit and the second delay circuit are configured to start measurement of the first delay and measurement of the second delay at a time coordinated with a modulation control signal generated by a digital controller, the modulation control signal being used to initiate control of a transition to a modulation state, the second delay being greater than the first delay.

According to one embodiment, the second delay circuit is configured to generate a masking signal adapted to block the extracted clock signal at a constant reference level for the duration of the second delay.

According to one embodiment, the second delay circuit comprises a second capacitive element and a second current generator adapted to generate a second reference current adapted to obtain a second delay at a time when the second reference current is loaded through the second capacitive element.

According to one embodiment, the first delay circuit is configured to generate a reverse modulation signal suitable for modulating the load at the antenna terminal to zero or almost zero impedance in the modulation state for the duration of the first delay.

According to one embodiment, the first delay circuit comprises a first capacitive element and a first current generator adapted to generate a first reference current, the first delay circuit being configured to obtain a first delay when the first capacitive element is loaded with the first reference current.

BRIEF DESCRIPTION OF THE DRAWINGS

Other advantages and features of the invention will become apparent upon examination of the detailed description of examples and embodiments, which are not limiting, and in which:

FIG1 shows a contactless communication system;

FIG2 shows a timing diagram of a transponder;

FIG3 shows a first delay circuit and a digital controller incorporated into a modulator;

FIG4 shows some details of the timing diagram of FIG2 ;

FIG5 shows a second delay circuit incorporated into the modulator; and

FIG6 shows some details of the timing diagram of FIG2 .

DETAILED DESCRIPTION

FIG. 1 shows a contactless communication system SYS, for example compatible with the near field communication technology “NFC” or the radio frequency identification technology “RFID”.

The system SYS comprises a card reader RDR and a passive transponder CRD, such as an integrated circuit card (eg a bank card) or a tag.

The reader comprises an antenna Lr and a magnetic field generator. The reader includes a carrier signal on the antenna Lr, typically a sine wave at 13.56 MHz.

The passive transponder CRD comprises an antenna Lc intended to be inductively coupled with an antenna Lr of a reader RDR and an electronic circuit, for example produced in an integrated manner. The total impedance of the electronic circuit of the transponder CRC at the terminals of the antenna Lc is represented by the load LD.

The term "passive" in the general sense in the field of contactless communication means, in particular of the NFC or RFID type, that the transponder is passive, i.e. the reference clock signal it uses to clock the contactless communication is based exclusively on a carrier signal provided by the reader.

In this respect, the transponder CRD comprises a clock extraction circuit CLK_EXTR configured to generate a clock signal RF_CLK extracted from a carrier signal received at the terminals of its antenna Lc.

The transponder CRD comprises a modulator MMOD configured to reversely modulate the amplitude of the carrier signal in alternation between modulated and unmodulated states. The modulator MMOD is configured to generate a reverse modulation signal to control the coupling of the modulation load LDMOD to the terminals of the antenna Lc.

In the unmodulated state, the modulation load LDMOD is not coupled to the terminals of the antenna Lc, and the impedance at the antenna terminals is defined by the (non-zero) impedance of the transponder CRD circuit, called the total load LD. In the modulated state, the modulation load LDMOD is additionally coupled to the terminals of the antenna Lc in parallel with the total load LD, and the impedance at the antenna terminals is mainly defined by the impedance of the modulation load LDMOD.

The modulation load LDMOD has zero impedance and is represented by a switch diagram coupled to the antenna Lc terminal. However, the modulation load LDMOD can be implemented by a transistor controlled by an inverse modulation signal or a resistor or capacitor circuit optionally having zero impedance.

Zero or almost zero impedance refers to an impedance that is negligible compared to the impedance of the total load LD of the transponder CRD circuit coupled to the antenna Lc, especially the impedance considered at the carrier signal frequency. For example, it can be considered that the zero impedance or almost zero impedance is limited to a maximum value of a few percent (e.g. 2%) of the non-zero impedance at the antenna terminals in the unmodulated state, i.e. a few percent of the total load LD.

The total load LD of the electronic circuit at the antenna Lr terminal includes the impedance of the clock extraction circuit CLK_EXTR and the modulator MMOD, as well as typical circuits such as a power manager (not shown) of the limiting and rectifying circuit type.

2 to 6 illustrate exemplary embodiments and implementations of the modulator MMOD.

FIG. 2 illustrates a timing diagram G1 - G6 of the main signals involved in the transponder CRD, in particular the modulator MMOD, during the transmission of a data frame.

Figure G1 shows the sinusoidal carrier signal from the reader RDR, whose two components are AC0 and AC1, located at the two terminals of the transponder antenna Lc.

FIG. G2 shows the clock signal RF_CLK extracted from the carrier signal by the clock extraction circuit CLK_EXTR.

FIG. G3 shows the shielded clock signal RF_CLK_MSK, which is described below in conjunction with FIG. 5 and FIG. 6 .

FIG. G4 shows the modulation control signal mod_dig at the origin (before resynchronization) of the transition control from the non-modulation state ENMOD to the modulation state EMOD.

Graph G5 shows the generation of the masking signal MSK (solid line), in particular the second delay t2 generated by the load VC2 of the second capacitive circuit (dashed line), as described below with respect to FIGS. 5 and 6 .

Graph G6 shows the reverse modulation signal retromod (solid line) generated by the first delay t1 generated by the load VC1 of the first capacitive circuit (dashed line), as described below with respect to FIGS. 3 and 4 .

The transmission of the data frames takes place by means of bursts of alternating modulation states EMOD and unmodulation states ENMOD, for example in a Manchester type encoding.

The rising edge of the modulation control signal mod_dig controls the generation of the reverse modulation signal tromod to a high level “1”.

The high level "1" reverse modulation signal controls the modulation state EMOD, that is, controls the load LDMOD at the antenna Lc terminal to be modulated to zero impedance. Therefore, when the reverse modulation signal retromod is at "1", the amplitude of the carrier signals AC0 and AC1 is reduced to a value substantially equal to zero, and the clock extraction circuit CLK_EXTR can no longer detect the period of the carrier signal, and the clock signal RF_CLK is maintained at a constant level.

When the load VC1 of the first capacitive circuit MF1, C1 (FIG. 3) switches the CMOS inverter circuit (FIG. 3), ie, exceeds half of the high level, the generation duration of the reverse modulation signal is determined by the first delay t1.

Switching the CMOS inverter circuit can control the falling edge of the reverse modulation signal retromod to a low level “0”, thereby causing a transition from the modulated state EMOD to the unmodulated state ENMOD.

In the unmodulated state ENMOD, the load LDMOD at the terminal of the antenna Lc is no longer modulated to zero impedance, the carrier signals AC0 , AC1 have their original amplitudes, and the extraction of the clock signal RF_CLK is restored.

Refer to Figure 3.

FIG. 3 shows that the first delay circuit MF1 and the digital controller DIG_CNT generate the modulation control signal mod_dig, and the first delay circuit MF1 and the digital controller DIG_CNT are incorporated into the modulator MMOD.

In this example, the first delay circuit MF1 has a "one-shot" or "monostable latch" type architecture, comprising a CMOS input inverter component P1-N1, whose output reaches the input of a CMOS output inverter component P2-N2, powered by a high reference voltage Vdd and a low reference voltage gnd.

The first synchronization control signal MF1_in derived from the modulation control signal mod_dig is provided to the input of the CMOS input inverter component P1 - N1 through the inverter INV_in.

The capacitive element C1 is coupled between the output of the first CMOS inverter component P1 - N1 and a terminal at a low reference voltage gnd.

The current source Igen1 applies a first current I1 , for example, a maximum current, in the conduction terminal of the P-type transistor P1 of the CMOS input inverter component P1 - N1 through the current mirror component P3 - P4 .

Thus, when the control signal MF1_in is at a low level, the capacitive element C1 is short-circuited by the transistor N1 in the on-state, and the delay circuit MF1 directly transmits the high reference level Vdd at its output MF1_out. When the control signal MF1_in is at a high level, the capacitive element C1 is loaded by the current I1 via the transistor P1 in the on-state, the voltage VC1 ( FIG. 2 , G6 ) has the shape of a rising slope at the input of the CMOS output inverter component P2 - N2, and the delay circuit MF1 transmits the low reference level gnd at its output MF1_out, with a delay of the duration t1 taken by the voltage VC1 to reach the threshold voltage of the transistor N2.

An AND gate between the control signal MF1_in and the output MF1_out of the first delay circuit MF1 allows generating a clear falling edge on the modulation signal retromod at the switching instant defined by the delay t1 .

Therefore, the duration of the modulation state is precisely defined at a time determined by the first delay t1 after receiving the modulation control signal mod_dig.

In fact, the first synchronization control signal MF1_in is derived from the modulation control signal mod_dig, and in a simple exemplary embodiment, the modulation control signal mod_dig can directly control the input on the inverter INV_in of the delay circuit MF1.

However, in this exemplary embodiment, the first synchronization control signal MF1_in is derived from the modulation control signal mod_dig, and further, through the corresponding flip-flop D, its transitions on the falling edge of the masking clock signal RF_CLK_MSK and the rising edge of the extraction clock signal RF_CLK are synchronized.

The signal generated by synchronizing the modulation control signal mod_dig on the falling edge of the masking clock signal RF_CLK_MSK is called the second control signal (inverse latch), and is used to control the second delay circuit (MF2) described below in conjunction with Figures 5 and 6.

Therefore, the first control signal MF1_in and the second control signal retro_latch are coordinated from the modulation control signal mod_dig so as to be shifted relative to each other. This allows to ensure a robust operation of the contactless communication, avoiding spurious effects in the signal generation of the clock cycle desynchronization type.

FIG. 4 shows details of graphs G1 , G2 and G6 of FIG. 2 , and graph G41 shows the synchronization control signal MF1_in.

Therefore, it can be seen in Figure 4 that the rising edge of the synchronization control signal MF1_in is synchronized with the rising edge of the clock signal RF_CLK, and through the action of the AND gate at the output of the first delay circuit MF1, a rising edge is directly generated in the signal retromod (thereby receiving the values MF1_in = "1" and MF1_out = "1").

After duration t1 , when the voltage slope VC1 at the terminals of the capacitive element C1 switches the transistor P2 , the AND gate generates a falling edge in the signal retromod (MF1_in=“1” and MF1_out=“0”).

The falling edge of the control signal MF1_in occurs after the falling edge of the reverse modulation signal retromod and directly switches the output of the first delay circuit MF1_out to "1", and the output of the AND gate remains at 0 (MF1_in="0" and MF1_out="1").

The falling edge of the reverse modulation signal retromod marks the end of the modulation state EMOD and the moment of transition from the modulation state to the unmodulation state ENMOD.

In summary, the modulator MMOD comprises a first delay circuit MF1 configured to generate a first delay t1 and a reverse modulation signal retromod which controls, on the one hand, the modulation of the load LDMOD at the terminals of the antenna Lc at zero impedance in the modulation state and, on the other hand, the transition from the modulation state EMOD to the unmodulated state ENMOD at a moment determined by the first delay t1.

At the beginning of the unmodulated state ENMOD, the carrier signals AC0, AC1 at the terminals of the transponder antenna Lc may have an unstable phase, wherein a stabilization time STB is required to recover a level of sufficient amplitude to guarantee a correct extraction of the signal RF_CLOCK, depending on the nature of the total load RD and the distance between the reader RDR and the transponder CRD.

During the stabilization time, the extraction of the clock signal RF_CLK may be disturbed, which may introduce a risk of errors in the timing based on the extracted clock signal RF_CLK.

Reference is made to Figures 5 and 6 in this regard.

FIG. 5 shows a second delay circuit MF2 integrated in the modulator MMOD, which is configured to generate a masking signal MSK that masks the clock signal RF_CLK during a stabilization time STB.

Like the first delay circuit MF1 , the second delay circuit MF2 has a “one-shot” or “monostable latch” type architecture. Common elements between the first delay circuit MF1 and the second delay circuit MF2 have the same reference numerals and will not be described in full detail.

However, it should be noted that in the second delay circuit MF2, the current generator Igen2 generates a current I2 different from the current I1, and/or the second capacitive element C2 has a different capacitance value from the first capacitive element C1.

The input of the second delay circuit MF2 is located at the input of the inverter INV_in, and the output signal MF2_out of the second delay circuit MF2 is provided by the inverter INV_out connected to the CMOS output inverter component P2 - N2 .

The signal for controlling the second delay circuit MF2 provided at the input of the inverter INV_in comes from the output RS_out of the NOR latch RS.

The initialization input (“set”) of the latch RS receives a pulse retro_latch_pulse generated by the pulse generator PLSGEN on a rising edge of the modulation control signal mod_dig or, advantageously, in the framework of the exemplary embodiments described with respect to 2 to 6 , on a rising edge of the second synchronization control signal.

A reset input of the latch RS receives the output signal MF2_out from the second delay circuit MF2.

In addition, the output RS_out of the latch RS provides a shielding signal MSK through an inverter INV_MSK. The shielding signal controls the follower amplifier GT_CLK so that if the shielding signal is "1" (therefore, if the signal on RS_out is "0"), the follower amplifier retransmits the extracted clock signal RF_CLK on its output RF_CLK_MSK, and if the shielding signal is "0" (therefore, if the signal on RS_out is "1"), it retransmits a constant signal at a low level "0" on its output RF_CLK_MSK.

In other words, the masking signal MSK is adapted to block the extracted clock signal RF_CLK_MSK at a constant reference level.

Refer to Figure 6.

Figure 6 shows details of Figures G2 and G3 in Figure 2, Figure G41 shows the second synchronization control signal retro_latch, Figure G42 shows the pulse retro_latch_pulse, Figure G51 shows the output MF2_out (solid line) of the second delay circuit MF2 and the voltage at the terminal of the second capacitor element C2 (dashed line), and Figure G52 shows the signal at the latch RS output RS_out.

5 and 6 , when the modulation control signal (retro_latch) is at a high level “1”, the pulse retro_latch_pulse initializes the output RS_out to “1”. Using the pulse retro_latch_pulse instead of the signal retro_latch can avoid conflicts between the initialization and reset inputs of the latch RS.

On the one hand, the masking signal MSK is at "0", and the masking clock signal RF_CLK_MSK is blocked at "0" regardless of the behavior of the extracted clock signal RF_CLK.

On the other hand, the output RS_out at "1" controls the loading mechanism of the second capacitive element C2 according to the voltage slope VC2. The duration t2 required for the voltage slope VC2 to reach half of the high level "1" is configured to be greater than the duration of the first delay t1.

After the second delay t2, the output MF2_out of the second delay circuit switches to "1" and resets the output RS_out of the latch RS to "0".

On the one hand, the output MF2_out of the delay circuit MF2 switches to "0" immediately.

On the other hand, the mask signal MSK returns to "1", and the follower amplifier GT_CLK retransmits the clock signal RF_CLK at its output RF_CLK_MSK.

The first delay t1 determines the transition to the unmodulated state and the etching of recovering the extracted clock signal, and the second delay t2 determines the end of the clock signal RF_CLK_MSK masking, and the difference between the first delay t1 and the second delay t2 is selected to mask the extracted clock signal RF_CLK during the stabilization time STB.

Therefore, after the second delay t2, the operation of the control circuit DIG_CNT (FIG. 4) can be clocked using the masked clock signal RF_CLK_MSK without generating risks.

Specifically, the control circuit DIG_CNT is configured to generate a modulation control signal mod_dig, which controls a transition from a non-modulated state to a modulated state, at a time defined by measuring a duration over a clock period of the masked clock signal RF_CLK_MSK.

Knowing the duration of delays t1 and t2, the counting of the number of clock cycles is adapted to the number remaining after counting the difference t2-t1.

In summary, the modulator MMOD advantageously comprises a second delay circuit MF2 configured to generate a second delay t2 at the origin of the control transition to the modulation state from the modulation control signal mod_dig, the second delay t2 starting from a moment coordinated with the start of the measurement of the first delay t1. The control circuit DIG_CNT is configured to measure the remaining time of the unmodulated state on the clock cycle of the masked clock signal RF_CLK_MSK derived from the extracted clock signal RF_CLK after the second delay t2. Therefore, the control circuit DIG_CNT can initiate the next control of the transition from the unmodulated state to the modulated state in a coherent and precisely synchronized manner with the carrier signals AC0, AC1 by means of the modulation control signal mod_DIG, although this signal is lost in the modulation state.

Furthermore, given that the first delay t1 and the second delay t2 are defined by the magnitude of the constant currents I1 , I2 and the capacitance values of the first capacitive element C1 and the second capacitive element C2 , embodiments and implementations may provide calibration of the delays t1 , t2 according to the actual extracted clock signal.

For example, such calibration can be performed before data transmission, for example when starting the transponder CRD, or during the "emd" (for "electromagnetic interference") time provided by typical contactless communication standards before transponder data transmission, during which the transponder must have a constant impedance.

By adjusting the strength of the first current I1 and the second current I2 and adjusting the capacitance values of the first capacitive element C1 and the second capacitive element C2 , the duration of the first delay t1 and the second delay t2 can be easily and accurately calibrated.

Thus, the above described embodiments and implementations allow the use of zero impedance in the modulation state TX to improve the performance of the transponder, thereby increasing the communication distance. This improvement is possible by using a mechanism that uses a delay to compensate for the fact that the clock is not available in the modulation state. This ensures the consistency of the frame TX with the clock frequency of the carrier RF.

Claims (20)

1.A method of contactless communication, comprising:

Receiving a carrier signal at a terminal of an antenna; and

-Reverse modulating the carrier signal in an alternation of a modulated state and an unmodulated state, the reverse modulating comprising:

in the unmodulated state, modulating a load at a terminal of the antenna to a non-zero impedance;

Modulating a load at a terminal of the antenna to zero impedance or impedance modulation less than 2% of the non-zero impedance in the modulated state; and

A transition from the modulated state to the unmodulated state is controlled at a first time determined by a first delay.

2. The method of claim 1, further comprising: controlling a transition from the unmodulated state to the modulated state at a second time determined by a duration measured over a clock period generated from a clock signal extracted from the carrier signal, the measurement of the duration beginning at a third time determined by a second delay, the third time determined by the second delay being subsequent to the first time of transition to the unmodulated state.

3. The method of claim 2, further comprising coordinating a measurement of the second delay and a measurement of the first delay starting at respective times with a modulation control signal that initiates a transition to the modulation state, the second delay being greater than the first delay.

4. The method of claim 2, further comprising generating a mask signal that blocks the extracted clock signal at a constant reference level for a duration of the second delay.

5. The method of claim 2, further comprising obtaining the second delay by loading a time of a second capacitive element with a second reference current.

6. The method of claim 1, further comprising controlling modulation of the load at a terminal of the antenna with a zero impedance of the modulation state or an impedance that is less than 2% of the non-zero impedance by a reverse modulation signal generated for a duration determined by the first delay.

7. The method of claim 1, further comprising obtaining the first delay by loading a time of the first capacitive element with a first reference current.

8. A contactless communication transponder comprising:

An antenna comprising a terminal and configured to receive a carrier signal; and

A modulator comprising a first delay circuit configured to generate a first delay, the modulator configured to reverse modulate the carrier signal in an alternation of a modulated state and an unmodulated state, the reverse modulating comprising configuring the modulator to:

in the unmodulated state, modulating a load at a terminal of the antenna to a non-zero impedance;

modulating a load at a terminal of the antenna to a zero impedance or an impedance that is less than 2% of the non-zero impedance in the modulated state; and

A transition from the modulated state to the unmodulated state is controlled at a first time determined by the first delay.

9. The transponder of claim 8, further comprising a clock extraction circuit configured to generate a clock signal extracted from the carrier signal, wherein the modulator further comprises:

a second delay circuit configured to generate a second delay; and

Control circuitry configured to:

measuring a duration of a clock cycle of the extracted clock signal from a third time determined by the second delay, the third time determined by the second delay being after the first time of transition to the unmodulated state; and

A modulation control signal is generated at a second time determined by the measured duration, the modulation control signal controlling a transition from the non-modulated state to the modulated state.

10. The transponder of claim 9, wherein the first delay circuit and the second delay circuit are configured to start the measurement of the first delay and the measurement of the second delay, respectively, at respective times coordinated with a modulation control signal generated by the control circuit for controlling the transition to the modulation state, wherein the second delay is greater than the first delay.

11. The transponder of claim 9, wherein the second delay circuit is configured to generate a masking signal for a duration of the second delay to block the extracted clock signal at a constant reference level.

12. The transponder of claim 9, wherein the second delay circuit comprises:

A second capacitive element; and

A second current generator configured to generate a second reference current;

Wherein the second delay circuit is configured to obtain the second delay from a time of loading the second capacitive element with the second reference current.

13. The transponder of claim 8, wherein the first delay circuit is configured to generate an inverse modulation signal to control modulation of the load at a terminal of the antenna to be zero impedance or an impedance less than 2% of the non-zero impedance in the modulated state for a duration of the first delay.

14. The transponder of claim 8, wherein the first delay circuit comprises:

a first capacitive element; and

A first current generator configured to generate a first reference current;

Wherein the first delay circuit is configured to obtain the first delay from a time of loading the first capacitive element with the first reference current.

15. A contactless communication transponder comprising:

An antenna comprising a terminal and configured to receive a carrier signal;

A clock extraction circuit configured to generate a clock signal extracted from the carrier signal; and

A modulator configured to reverse modulate the carrier signal in an alternation of a modulated state and an unmodulated state, the modulator comprising:

A first delay circuit configured to generate a first delay,

A second delay circuit configured to generate a second delay; and

Control circuitry configured to:

in the unmodulated state, modulating a load at a terminal of the antenna to a non-zero impedance;

Modulating a load at a terminal of the antenna to a zero impedance or an impedance that is less than 2% of the non-zero impedance in the modulated state;

controlling a transition from the modulated state to the unmodulated state at a first time determined by the first delay;

measuring a duration of a clock cycle of the extracted clock signal from a third time determined by the second delay, the third time determined by the second delay being after the first time of transition to the unmodulated state; and

A modulation control signal is generated at a second time determined by the measured duration, the modulation control signal controlling a transition from the non-modulated state to the modulated state.

16. The transponder of claim 15, wherein the first delay circuit is configured to generate a reverse modulation signal to control modulation of the load at a terminal of the antenna to an impedance of the zero impedance or less than 2% of the non-zero impedance in the modulated state for a duration of the first delay.

17. The transponder of claim 15, wherein the first delay circuit and the second delay circuit are configured to start the measurement of the first delay and the measurement of the second delay, respectively, at respective times coordinated with a modulation control signal generated by the control circuit for controlling the transition to the modulation state, wherein the second delay is greater than the first delay.

18. The transponder of claim 15, wherein the second delay circuit is configured to generate a masking signal for a duration of the second delay to block the extracted clock signal at a constant reference level.

19. The transponder of claim 15, wherein the second delay circuit comprises:

A second capacitive element; and

A second current generator configured to generate a second reference current;

Wherein the second delay circuit is configured to obtain the second delay from a time of loading the second capacitive element with the second reference current.

20. The transponder of claim 15, wherein the first delay circuit comprises:

a first capacitive element; and

A first current generator configured to generate a first reference current;

Wherein the first delay circuit is configured to obtain the first delay from a time of loading the first capacitive element with the first reference current.