CN114650079A - Inverse modulation method for contactless communication, and corresponding transponder - Google Patents

Abstract

Embodiments of the present disclosure relate to a method of inverse modulation for contactless communication, and a corresponding transponder. A contactless communication method includes inversely modulating a carrier signal received at a terminal of an antenna in alternation of a modulated state and an unmodulated state. The modulation state includes modulating a load at the antenna terminal with zero impedance and controlling a transition from the modulated state to the unmodulated state at a time determined by the first delay.

Description

Inverse modulation method for contactless communication, and corresponding transponders

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of French Application No. 2013523, filed on December 17, 2020, which is incorporated herein by reference.

technical field

Implementations and embodiments relate to contactless communications, particularly contactless communications using amplitude inverse modulation of a carrier signal.

Background technique

Contactless communications, such as those according to a technology called "Near Field Communication" (usually "NFC"), and those according to a technology called "Radio Frequency Identification" (usually "RFID"), are permitted A wireless connection technology for short-distance (eg 10cm) communication between electronic devices, such as between a contactless integrated circuit card or a tag and a card reader.

NFC technology is an open technology platform, standardized in ISO-14443, EMVCo, NFC Forum standards, but incorporates other existing compatible communication standards. RFID technology is standardized in particular through the ISO-18092 standard, and also incorporates other existing compatible communication standards.

Contactless communication can be achieved between two contactless peer-to-peer communication devices (especially those compatible with NFC technology), such as multifunction phones (commonly referred to as "smartphones"); or between a card reader device and an answering device device, such as an NFC or RFID card or tag or a multifunction phone emulated in card mode.

When transferring information between the reader and the transponder, the reader generates a magnetic field with an antenna, which is typically a 13.56MHz sine wave (called a carrier or carrier signal).

To transmit information from the reader to the transponder, the reader uses amplitude modulation of the carrier wave, and the transponder is able to demodulate the received carrier wave to obtain the data transmitted by the reader.

In order to transmit information from the transponder to the card reader, the card reader generates a magnetic field (carrier wave) without modulation. The transponder then modulates the field generated by the reader according to the information to be transmitted. The frequency of this modulation corresponds to the sub-carriers of the carrier. The frequency of this sub-carrier depends on the communication protocol used, and may be equal to 848 kHz, for example.

Modulation is performed by modifying the load connected to the transponder antenna terminals.

Then there may be two modes of operation, passive or active.

In active operating mode, both the reader and the active transponder generate electromagnetic fields. Typically, this mode of operation is used when the active transceiver has its own power source, such as a battery.

Specifically, passive transponders do not have a power source and use the energy transmitted by the carrier wave from the card reader to power their integrated circuits.

In passive mode, the transponder inverse modulates the waves from the card reader to transmit the information and does not integrate an actual transmitter used to transmit the information, such as a transmitter capable of generating its own magnetic field during transmission.

A passive transponder modifies the impedance connected to its antenna by inductive coupling by inverse modulation visible on the reader side to transmit data frames.

During frame transmission, the inverse modulation is confined in the unmodulated state when the inverse modulation load is not connected to the antenna, or in the modulated state when the inverse modulation load is connected to the transponder antenna.

The greater the change in impedance generated by the transponder (ie, the difference in loading between the modulated and unmodulated states), the greater the impedance seen from the reader side, and therefore the easier it is for the reader to demodulate the data. One of the main performance criteria for transponders is the load modulation amplitude "LMA". The LMA is measured by measuring the difference in current amplitude in the antenna Lc of the transponder CRD between the modulated state and the unmodulated state.

A difficulty encountered in contactless transponder design is optimizing the LMA while maintaining a coherent frame, that is to say synchronizing with the reader's carrier signal, regardless of the electromagnetic field conditions (especially between the reader and the transponder). the distance).

In conventional contactless transponders, the load modulation is designed so that the carrier signal on the transponder antenna is available in both modulated and unmodulated states. This allows clock extraction from the carrier to remain active and to clock the transmission on the clock cycle of the extracted signal as the only time reference, in particular to define transition instants between unmodulated and modulated states.

The disadvantage of these conventional solutions is that the impedance at the antenna terminals is in principle prohibited to be zero or too low due to the need to extract the clock signal. Therefore, conventional solutions provide for adjusting the impedance value in the modulated state according to the effective level of the electromagnetic field, which complicates the design of the inverse modulation and limits the load modulation amplitude LMA.

There is a need to increase the load modulation amplitude LMA of contactless transponders, especially passive contactless transponders.

SUMMARY OF THE INVENTION

According to one aspect, there is provided a contactless communication method comprising inversely modulating a carrier signal received at an antenna terminal with alternating modulated and unmodulated states. According to a general feature of this aspect, the unmodulated state includes modulation with a non-zero impedance loaded at the antenna terminals, the modulated state includes modulation with zero or nearly zero impedance loaded at the antenna terminals, and the change from the modulated state to the unmodulated state The transition is controlled at the instant determined by the first delay.

"Zero impedance or nearly zero impedance" means as low an impedance as possible given the material constraints in which it is implemented, eg, a transistor in the conducting state is considered to have zero or nearly zero impedance at its conducting terminal. For example, "almost zero impedance" refers, in particular, to an impedance that is at most a few percent (eg, 2%) of the non-zero impedance value in the unmodulated state.

In other words, delays are used in the modulated state to maintain precise synchronization of frame transmissions to provide all-zero impedance inverse modulation. Therefore, the first delay is used to define the time of the modulated state, since the clock signal cannot be extracted from the modulated carrier signal with zero impedance.

Thus, the load modulation amplitude LMA is maximized (strictly speaking, the modulation state component of the LMA is optimized), which in particular allows to increase the range of contactless communication.

According to one implementation, the transition from the unmodulated state to the modulated state is controlled at a time instant determined by a duration measured over a clock period generated by the clock signal extracted from the carrier signal, the duration measured from the time determined by the second delay The time starts, the time determined by the second delay is after the time of transition to the unmodulated state.

In other words, the second delay allows avoiding the use of the clock signal extracted when the clock extraction is restarted at the beginning of the modulation state, thereby allowing to avoid instabilities in the clock signal extracted when it is generated restarting.

In particular, this allows the timing of transitions to be defined very precisely over time and can be adapted to different conditions.

According to one embodiment, the measurement of the second delay and the measurement of the first delay begin at a time in coordination with a modulation control signal that initiates a control transition to the modulation state, the second delay being greater than the first delay.

For example, the modulation control signal is at the origin of the modulation state control and can typically be generated by a digital controller. The start of the measurement of the first delay and the second delay is controlled based on the modulation control signal, and is offset from each other, for example, by half a clock cycle to ensure robust operation of the system.

The difference between the second delay and the first delay is advantageously designed to be just long enough to ensure that the clock signal extraction has restarted and is stable when the measurement of the clock cycle begins.

According to one embodiment, a mask signal blocking the extracted clock signal at a constant reference level is generated during the second delay duration.

According to one embodiment, the second delay is obtained by the time of loading the second capacitive element with the second reference current.

According to one embodiment, the load modulation at the antenna terminals with zero or almost zero modulation state impedance is controlled by the inverse modulation signal generated for a duration determined by the first delay.

According to one embodiment, the first delay is obtained by the time of loading the first capacitive element with the first reference current.

According to another aspect, there is provided a contactless communication transponder, such as a tag, comprising: an antenna intended to receive a carrier signal, and an antenna configured to inversely modulate the carrier signal in an alternation of modulated and unmodulated states Modulator. According to a general feature of this aspect, the modulator includes a first delay circuit configured to generate a first delay, and the modulator is configured to modulate the load at the antenna terminal to a non-zero impedance in the unmodulated state, and to modulate the load at the antenna terminal to a non-zero impedance in the modulated state The load at the antenna terminals is modulated to zero or nearly zero impedance, and the transition from the modulated state to the unmodulated state is controlled at the instant determined by the first delay.

According to one embodiment, the transponder further includes a clock extraction circuit configured to generate a clock signal extracted from the carrier signal, and the modulator includes a second delay circuit configured to generate a second delay , and a control circuit configured to measure the duration over clock cycles from the extracted clock signal from a time determined by the second delay after the time of transition to the unmodulated state , and a modulation control signal that controls the transition from the unmodulated state to the modulated state is generated at the instant determined by the duration of the measurement.

According to one embodiment, the first delay circuit and the second delay circuit are configured to start the measurement of the first delay and the measurement of the second delay at a time in coordination with a modulation control signal generated by the digital controller, the modulation control signal for Initiating control of transition to the modulated state, the second delay is greater than the first delay.

According to one embodiment, the second delay circuit is configured to generate a mask signal adapted to block the extracted clock signal at a constant reference level for the duration of the second delay.

According to one embodiment, the second delay circuit comprises a second capacitive element and a second current generator adapted to generate the second reference current at a time when the second reference current is loaded through the second capacitive element Get a second delay.

According to one embodiment, the first delay circuit is configured to generate an inverse modulated signal adapted to modulate the load at the antenna terminals with zero or almost zero impedance in a modulated state for the duration of the first delay .

According to one embodiment, the first delay circuit comprises a first capacitive element and a first current generator adapted to generate a first reference current, the first delay circuit being configured to load the first capacitive element with the first reference current Get the first delay.

Description of drawings

Other advantages and features of the present invention will become apparent upon examination of the detailed description of examples and implementations, which are not limiting of the accompanying drawings, in which:

Figure 1 shows a contactless communication system;

Fig. 2 shows the timing diagram of the transponder;

Figure 3 shows the first delay circuit and digital controller incorporated into the modulator;

Figure 4 shows details of some of the timing diagrams of Figure 2;

Figure 5 shows a second delay circuit incorporated into the modulator; and

FIG. 6 shows details of some of the timing diagrams of FIG. 2 .

Detailed ways

Figure 1 shows a contactless communication system SYS, for example compatible with the near field communication technology "NFC" or the radio frequency identification technology "RFID".

The system SYS includes a card reader RDR and a passive transponder CRD, such as an integrated circuit card (eg a bank card) or a tag.

The reader includes an antenna Lr and a magnetic field generator, and the reader contains a carrier signal on the antenna Lr, usually a sine wave at 13.56MHz.

The passive transponder CRD comprises an antenna Lc intended to be inductively coupled with the antenna Lr of the reader RDR, and an electronic circuit, eg generated in an integrated manner. The total impedance of the electronic circuit of the transponder CRC at the antenna Lc terminal is represented by the load LD.

The usual meaning of the term "passive" in the field of contactless communication means, especially the NFC or RFID type, more specifically the transponder is passive, i.e. it is used to clock the contactless communication The reference clock signal for timing is exclusively based on the carrier signal provided by the reader.

In this regard, the transponder CRD comprises a clock extraction circuit CLK_EXTR configured to generate a clock signal RF_CLK extracted from a carrier signal received at the terminals of its antenna Lc.

The transponder CRD includes a modulator MMOD configured to inversely modulate the amplitude of the carrier signal in alternating modulated and unmodulated states. The modulator MMOD is configured to generate a reverse modulation signal, thereby controlling the coupling of the modulation load LDMOD with the terminals of the antenna Lc.

In the unmodulated state, the modulation load LDMOD is not coupled to the terminals of the antenna Lc, the impedance at the antenna terminals is defined by the (non-zero) impedance of the transponder CRD circuit, called the total load LD. In the modulated state, the modulation load LDMOD is additionally coupled to the terminals of the antenna Lc in parallel with the total load LD, and the impedance at the antenna terminals is mainly defined by the impedance of the modulation load LDMOD.

The modulating load LDMOD has zero impedance and is represented by a switch diagram coupled to the antenna Lc terminal. However, modulating the load LDMOD may be performed by a transistor controlled by an inverse modulating signal or alternatively a resistive or capacitive circuit with zero impedance.

Zero or almost zero impedance refers to an impedance that is negligible compared to the impedance of the total load LD of the transponder CRD circuit coupled to the antenna Lc, especially the impedance considered at the carrier signal frequency. For example, zero or nearly zero impedance can be considered to be limited to a maximum of several percentages (eg 2%) of non-zero impedance at the antenna terminals in the unmodulated state, ie several percentages of the total load LD.

The total load LD of the electronic circuit at the antenna Lr terminal includes the clock extraction circuit CLK_EXTR and the impedance of the modulator MMOD, as well as typical circuits such as a limiting and rectifying circuit type power manager (not shown).

2-6 illustrate exemplary embodiments and implementations of the modulator MMOD.

Figure 2 illustrates the timing diagrams G1-G6 of the main signals involved in the transponder CRD, in particular the modulator MMOD, during the transmission of a data frame.

Figure G1 shows the sinusoidal carrier signal from the card reader RDR, whose two components are AC0, AC1, on the two terminals of the transponder antenna Lc.

Figure G2 shows the clock signal RF_CLK extracted from the carrier signal by the clock extraction circuit CLK_EXTR.

FIG. G3 shows the masked clock signal RF_CLK_MSK, which is described below in conjunction with FIGS. 5 and 6 .

Figure G4 shows the modulation control signal mod_dig at the origin (before resynchronization) of the transition control from the unmodulated state ENMOD to the modulated state EMOD.

FIG. G5 shows the generation of the mask signal MSK (solid line), in particular the second delay t2 generated by the load VC2 of the second capacitive circuit (dashed line), as described below with respect to FIGS. 5 and 6 .

FIG. G6 shows the reverse modulated signal retromod (solid line) generated by the first delay t1 generated by the load VC1 of the first capacitive circuit (dashed line), as described below with respect to FIGS. 3 and 4 .

The transmission of data frames takes place by alternating bursts of modulated state EMOD and unmodulated state ENMOD, eg in Manchester type coding.

The rising edge of the modulation control signal mod_dig controls the generation of the reverse modulation signal tromod to a high level "1".

The high-level "1" inverse modulation signal controls the modulation state EMOD, that is, the modulation of the load LDMOD at the terminal Lc of the control antenna is zero impedance. Therefore, when the reverse modulation signal retromod is at "1", the amplitudes of the carrier signals AC0, AC1 are reduced to substantially zero values, and the clock extraction circuit CLK_EXTR is no longer able to detect the period of the carrier signal, and the clock signal RF_CLK remains at constant level.

When the load VC1 of the first capacitive circuits MF1, C1 (FIG. 3) switches the CMOS inverter circuit (FIG. 3), that is, when it exceeds half of the high level, the generation duration of the inverse modulation signal is determined by the first delay t1 .

Switching the CMOS inverter circuit can control the falling edge of the reverse modulation signal retromod to a low level "0", resulting in a transition from the modulated state EMOD to the unmodulated state ENMOD.

In the unmodulated state ENMOD, the load LDMOD at the antenna Lc terminal is no longer modulated to zero impedance, the carrier signals AC0, AC1 have their initial amplitudes, and the extraction of the clock signal RF_CLK is resumed.

Refer to Figure 3.

FIG. 3 shows that the first delay circuit MF1 and the digital controller DIG_CNT generate the modulation control signal mod_dig, and that the first delay circuit MF1 and the digital controller DIG_CNT are incorporated into the modulator MMOD.

In this example, the first delay circuit MF1 has a "one-shot" or "one-shot" type of architecture, comprising CMOS input inverter components P1-N1, the outputs of which go to CMOS output inverter component P2 - Input of N2, powered by high reference voltage Vdd and low reference voltage gnd.

The first synchronization control signal MF1_in derived from the modulation control signal mod_dig is provided to the inputs of the CMOS input inverter components P1-N1 through the inverter INV_in.

The capacitive element C1 is coupled between the output of the first CMOS inverter component P1-N1 and the terminal at the low reference voltage gnd.

The current source Igen1 applies a first current I1, eg a maximum current, in the conduction terminal of the P-type transistor P1 of the CMOS input inverter components P1-N1 through the current mirror components P3-P4.

Therefore, when the control signal MF1_in is at a low level, the capacitive element C1 is short-circuited by the transistor N1 in the conducting state, and the delay circuit MF1 directly transmits the high reference level Vdd on its output MF1_out. When the control signal MF1_in is at a high level, the capacitive element C1 is loaded by the current I1 via the transistor P1 in the conducting state, the voltage VC1 (FIG. 2, G6) has a rising slope at the input of the CMOS output inverter assembly P2-N2 shape, and the delay circuit MF1 transmits a low reference level gnd on its output MF1_out, with a delay of the duration t1 taken by the voltage VC1 to reach the threshold voltage of the transistor N2.

The AND gate between the control signal MF1_in and the output MF1_out of the first delay circuit MF1 allows a sharp falling edge to be generated on the modulation signal retromod at the switching instant defined by the delay t1.

Thus, the duration of the modulation state is precisely defined at the instant determined by the first delay t1 after the reception of the modulation control signal mod_dig.

In fact, the first synchronization control signal MF1_in is derived from the modulation control signal mod_dig, and in a simple exemplary embodiment, the modulation control signal mod_dig may directly control the input on the inverter INV_in of the delay circuit MF1.

However, in this exemplary embodiment, the first synchronization control signal MF1_in is derived from the modulation control signal mod_dig, and furthermore, by the corresponding flip-flop D, which masks the falling edge of the clock signal RF_CLK_MSK and extracts the rising edge of the clock signal RF_CLK The transitions on the edges are synchronous.

The signal generated by synchronizing the modulation control signal mod_dig on the falling edge of the mask clock signal RF_CLK_MSK is called the second control signal (inverse latch), and is used to control the second delay circuit ( MF2).

Therefore, the first control signal MF1_in and the second control signal retro_latch are coordinated from the modulation control signal mod_dig so as to be shifted from each other. This allows to ensure robust operation of the contactless communication avoiding spurious effects in the generation of signals of the clock cycle desynchronization type.

FIG. 4 shows details of the graphs G1 , G2 and G6 of FIG. 2 , and graph G41 shows the synchronization control signal MF1_in.

Therefore, it can be seen in FIG. 4 that the rising edge of the synchronization control signal MF1_in is synchronized with the rising edge of the clock signal RF_CLK, and by the action of the AND gate at the output of the first delay circuit MF1, the rising edge is generated directly in the signal retromod (thereby receiving the values MF1_in="1" and MF1_out="1").

After the duration t1, when the voltage slope VC1 at the terminal of the capacitive element C1 switches the transistor P2, the AND gate generates a falling edge in the signal retromod (MF1_in="1" and MF1_out="0").

The falling edge of the control signal MF1_in occurs after the falling edge of the reverse modulation signal retromod, and directly switches the output of the first delay circuit MF1_out to "1", and the output of the AND gate remains at 0 (MF1_in="0" and MF1_out = "1").

The falling edge of the reverse modulation signal retromod marks the end of the modulated state EMOD and the moment of transition from the modulated state to the unmodulated state ENMOD.

In summary, the modulator MMOD comprises a first delay circuit MF1 configured to generate a first delay t1 and a reverse modulation signal retromod. The reverse modulation signal retromod controls on the one hand the modulation of the load LDMOD at the terminals of the antenna Lc at zero impedance in the modulated state, and on the other hand the transition from the modulated state EMOD to the unmodulated state ENMOD at the instant determined by the first delay t1 .

At the beginning of the unmodulated state ENMOD, the carrier signals AC0, AC1 at the terminals of the transponder antenna Lc may have unstable phases, where a settling time STB is required to recover a level of sufficient amplitude to ensure correct extraction of the signal RF_Clock, depending on depends on the nature of the total load RD and the distance between the reader RDR and the transponder CRD.

During the settling time, the extraction of the clock signal RF_CLK may be disturbed, which introduces a risk of errors in the timing based on the extracted clock signal RF_CLK.

Reference is made to Figures 5 and 6 in this regard.

FIG. 5 shows a second delay circuit MF2 integrated in the modulator MMOD, which is configured to generate a mask signal MSK of the mask clock signal RF_CLK during the settling time STB.

Like the first delay circuit MF1, the second delay circuit MF2 has a "one shot" or "one shot" type of architecture. Common elements between the first delay circuit MF1 and the second delay circuit MF2 have the same reference numerals and will not be described in full detail.

It should be noted, however, that in the second delay circuit MF2, the current generator Igen2 generates a current I2 different from the current I1, and/or the second capacitive element C2 has a capacitance value different from that of the first capacitive element C1.

The input of the second delay circuit MF2 is at the input of the inverter INV_in, and the output signal MF2_out of the second delay circuit MF2 is provided by the inverter INV_out connected to the CMOS output inverter component P2-N2.

The signal supplied at the input of the inverter INV_in to control the second delay circuit MF2 comes from the output RS_out of the NOR latch RS.

The initialization input ("set") of the latch RS receives the pulse retro_latch_pulse generated by the pulse generator PLSGEN on the rising edge of the modulation control signal mod_dig, or advantageously in the framework of the exemplary embodiments described in relation to 2 to 6 , on the rising edge of the second synchronization control signal.

The reset input of the latch RS receives the output signal MF2_out from the second delay circuit MF2.

Furthermore, the output RS_out of the latch RS provides the mask signal MSK through the inverter INV_MSK. The mask signal controls the follower amplifier GT_CLK so that if the mask signal is "1" (so if the signal on RS_out is "0"), the follower amplifier retransmits the extracted clock signal RF_CLK on its output RF_CLK_MSK, and if the mask is "0" The signal is '0' (so if the signal on RS_out is '1') then retransmitted on its output RF_CLK_MSK is a constant signal at low level '0'.

In other words, the mask signal MSK is adapted to block the extracted clock signal RF_CLK_MSK with a constant reference level.

Refer to Figure 6.

Figure 6 shows the details of Figures G2 and G3 in Figure 2, Figure G41 shows the second synchronization control signal retro_latch, Figure G42 shows the pulse retro_latch_pulse, Figure G51 shows the output of the second delay circuit MF2 MF2_out (solid line) and the first The voltage at the terminal of the two capacitive element C2 (dashed line), Figure G52 shows the signal at the output RS_out of the latch RS.

Therefore, referring to FIGS. 5 and 6 , when the modulation control signal (retro_latch) is at a high level “1”, the pulse retro_latch_pulse initializes the output RS_out to “1”. Using pulse retro_latch_pulse instead of signal retro_latch avoids conflicting initialization and reset inputs of latch RS.

On the one hand, the mask signal MSK is at "0" and the mask clock signal RF_CLK_MSK is blocked at "0" regardless of the behavior of the extracted clock signal RF_CLK.

On the other hand, the output RS_out at "1" controls the loading mechanism of the second capacitive element C2 according to the voltage slope VC2. The duration t2 required for the voltage slope VC2 to reach half of the high level "1" is configured to be greater than the duration of the first delay t1.

After the second delay t2, the output MF2_out of the second delay circuit switches to "1" and resets the output RS_out of the latch RS to "0".

On the one hand, the output MF2_out of the delay circuit MF2 switches to "0" immediately.

On the other hand, the mask signal MSK returns to "1" and the follower amplifier GT_CLK retransmits the clock signal RF_CLK on its output RF_CLK_MSK.

A first delay t1 determines the transition to the unmodulated state and recovery of the etch to extract the clock signal, and a second delay t2 determines the end of the clock signal RF_CLK_MSK mask, the difference between the first delay t1 and the second delay t2 is chosen to settling time The extracted clock signal RF_CLK is masked during STB.

Therefore, after the second delay t2, the operation of the control circuit DIG_CNT (FIG. 4) can be clocked with the mask clock signal RF_CLK_MSK without risk being generated.

In particular, the control circuit DIG_CNT is configured to generate a modulation control signal mod_dig, which controls the transition from an unmodulated state to a modulated state, at a time instant defined by measuring the duration over a clock period of the mask clock signal RF_CLK_MSK.

Knowing the duration of delays t1 and t2, the count of the number of clock cycles is adapted to count the number remaining after the difference t2-t1.

In summary, the modulator MMOD advantageously comprises a second delay circuit MF2 configured to generate a second delay t2 from the modulation control signal mod_dig at the origin of the control transition to the modulation state, the second delay t2 from and The first delay t1 begins at the moment when the measurement start is coordinated. The control circuit DIG_CNT is configured to measure the remaining time of the unmodulated state over a clock cycle of the masked clock signal RF_CLK_MSK derived from the extracted clock signal RF_CLK after the second delay t2. Thus, the control circuit DIG_CNT can initiate the next control of the transition from the unmodulated state to the modulated state by means of the modulation control signal mod_DIG in a coherent and precisely synchronized manner with the carrier signals AC0, AC1, although this signal is lost in the modulated state.

In addition, given that the first delay t1 and the second delay t2 are defined by the strengths of the constant currents I1, I2 and the capacitance values of the first capacitive element C1 and the second capacitive element C2, the embodiments and implementations can be provided according to the actually extracted clock signal Calibration of delays t1, t2.

For example, this calibration can be done before data transmission, such as when the transponder CRD is activated, or during the "emd" (for "electromagnetic interference") time provided by normal contactless communication standards prior to transponder data transmission proceed, during which the transponder must have a constant impedance.

By adjusting the intensities of the first current I1 and the second current I2, and adjusting the capacitance values of the first capacitive element C1 and the second capacitive element C2, the durations of the first delay t1 and the second delay t2 can be easily and accurately calibrated.

Thus, the above-described embodiments and implementations allow the use of zero impedance in the modulation state TX to improve the performance of the transponder, thereby increasing the communication distance. This improvement is possible through a mechanism that uses a delay to compensate for the fact that the clock is not available in the modulated state. This ensures the coherence of the clock frequency of the frame TX with the carrier RF.

Claims (20)

1. A contactless communication method, comprising:

receiving a carrier signal at a terminal of an antenna; and

-inverse modulating the carrier signal in alternation between modulated and unmodulated states, the inverse modulation comprising:

modulating a load at a terminal of the antenna with a non-zero impedance in the unmodulated state;

modulating a load at a terminal of the antenna with zero or nearly zero impedance in the modulated state; and

controlling a transition from the modulated state to the unmodulated state at a first time determined by a first delay.

2. The method of claim 1, further comprising: controlling the transition from the unmodulated state to the modulated state at a second time instant, the second time instant being determined by a duration measured on a clock cycle generated by a clock signal extracted from the carrier signal, the measurement of the duration being started from a third time instant determined by a second delay, the third time instant determined by the second delay being subsequent to the first time instant of the transition to the unmodulated state.

3. The method of claim 2, further comprising coordinating the measurement of the second delay and the measurement of the first delay starting at respective times with a modulation control signal that initiates controlling the transition to the modulation state, the second delay being greater than the first delay.

4. The method of claim 2, further comprising generating a mask signal that blocks the extracted clock signal at a constant reference level for the duration of the second delay.

5. The method of claim 2, further comprising obtaining the second delay by loading a time of a second capacitive element with a second reference current.

6. The method of claim 1, further comprising controlling the load modulation at the terminals of the antenna with zero or near zero impedance of the modulation state by an inverse modulation signal generated for a duration determined by the first delay.

7. The method of claim 1, further comprising obtaining the first delay by loading a time of a first capacitive element with a first reference current.

8. A contactless communication transponder, comprising:

an antenna comprising a terminal and configured to receive a carrier signal; and

a modulator comprising a first delay circuit configured to generate a first delay, the modulator configured to inverse modulate the carrier signal in alternation of modulated and unmodulated states, the inverse modulation comprising configuring the modulator to:

modulating a load at a terminal of the antenna with a non-zero impedance in the unmodulated state;

modulating a load at a terminal of the antenna with zero or nearly zero impedance in the modulated state; and

controlling a transition from the modulated state to the unmodulated state at a first time instant determined by the first delay.

9. The transponder of claim 8, further comprising a clock extraction circuit configured to generate a clock signal extracted from the carrier signal, wherein the modulator further comprises:

a second delay circuit configured to generate a second delay; and

a control circuit configured to:

measuring a duration of a clock cycle of the extracted clock signal from a third time instant determined by the second delay, the third time instant determined by the second delay being subsequent to the first time instant of the transition to the unmodulated state; and

generating a modulation control signal at a second time instant determined by the measured duration, the modulation control signal controlling the transition from the unmodulated state to the modulated state.

10. The transponder of claim 9, wherein the first delay circuit and the second delay circuit are configured to begin measurement of the first delay and measurement of the second delay, respectively, at respective times coordinated with a modulation control signal generated by the control circuit to control the transition to the modulation state, wherein the second delay is greater than the first delay.

11. The transponder of claim 9, wherein the second delay circuit is configured to generate a mask signal for the duration of the second delay to block the extracted clock signal at a constant reference level.

12. The transponder of claim 9, wherein the second delay circuit comprises:

a second capacitance element; and

a second current generator configured to generate a second reference current;

wherein the second delay circuit is configured to obtain the second delay from a time that the second capacitive element is loaded with the second reference current.

13. The transponder of claim 8, wherein the first delay circuit is configured to generate an inverse modulation signal to control modulation of the load at the terminals of the antenna to zero impedance or nearly zero impedance in the modulation state for the duration of the first delay.

14. The transponder of claim 8, wherein the first delay circuit comprises:

a first capacitive element; and

a first current generator configured to generate a first reference current;

wherein the first delay circuit is configured to obtain the first delay from a time that the first capacitive element is loaded with the first reference current.

15. A contactless communication transponder, comprising:

an antenna comprising a terminal and configured to receive a carrier signal;

a clock extraction circuit configured to generate a clock signal extracted from the carrier signal; and

a modulator configured to inversely modulate the carrier signal in alternation of a modulated state and an unmodulated state, the modulator comprising:

a first delay circuit configured to generate a first delay,

a second delay circuit configured to generate a second delay; and

a control circuit configured to:

modulating a load at a terminal of the antenna with a non-zero impedance in the unmodulated state;

modulating a load at a terminal of the antenna with zero or nearly zero impedance in the modulated state;

controlling a transition from the modulated state to the unmodulated state at a first time determined by the first delay;

measuring a duration of a clock cycle of the extracted clock signal from a third time instant determined by the second delay, the third time instant determined by the second delay being subsequent to the first time instant of the transition to the unmodulated state; and

generating a modulation control signal at a second time instant determined by the measured duration, the modulation control signal controlling the transition from the unmodulated state to the modulated state.

16. The transponder of claim 15, wherein the first delay circuit is configured to generate an inverse modulation signal to control modulation of the load at the terminals of the antenna to zero impedance or near zero impedance in the modulation state for the duration of the first delay.

17. The transponder of claim 15, wherein the first delay circuit and the second delay circuit are configured to begin measurement of the first delay and measurement of the second delay, respectively, at respective times coordinated with a modulation control signal generated by the control circuit to control the transition to the modulation state, wherein the second delay is greater than the first delay.

18. The transponder of claim 15 wherein the second delay circuit is configured to generate a mask signal for the duration of the second delay to block the extracted clock signal at a constant reference level.

19. The transponder of claim 15 wherein the second delay circuit comprises:

a second capacitance element; and

a second current generator configured to generate a second reference current;

wherein the second delay circuit is configured to obtain the second delay from a time that the second capacitive element is loaded with the second reference current.

20. The transponder of claim 15, wherein the first delay circuit comprises:

a first capacitive element; and

a first current generator configured to generate a first reference current;

wherein the first delay circuit is configured to obtain the first delay from a time that the first capacitive element is loaded with the first reference current.

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